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For SEC including a RNG block version >= 4, special initialization must occur before any descriptor that uses RNG block can be submitted. This initialization is required not only for SEC with version greater than 5.0, but for SEC with RNG version >=4. There may be a case where RNG has already been instantiated by u-boot or boot ROM code.In such SoCs, if RNG is initialized again SEC would returns "Instantiation error". Hence, the initialization status of RNG4 should be also checked before doing RNG init. Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Signed-off-by: Alex Porosanu <alexandru.porosanu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> Reviewed-by: Vakul Garg <vakul@freescale.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
739 lines
23 KiB
C
739 lines
23 KiB
C
/*
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* CAAM hardware register-level view
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*
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* Copyright 2008-2011 Freescale Semiconductor, Inc.
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*/
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#ifndef REGS_H
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#define REGS_H
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#include <linux/types.h>
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#include <linux/io.h>
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/*
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* Architecture-specific register access methods
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*
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* CAAM's bus-addressable registers are 64 bits internally.
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* They have been wired to be safely accessible on 32-bit
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* architectures, however. Registers were organized such
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* that (a) they can be contained in 32 bits, (b) if not, then they
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* can be treated as two 32-bit entities, or finally (c) if they
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* must be treated as a single 64-bit value, then this can safely
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* be done with two 32-bit cycles.
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*
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* For 32-bit operations on 64-bit values, CAAM follows the same
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* 64-bit register access conventions as it's predecessors, in that
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* writes are "triggered" by a write to the register at the numerically
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* higher address, thus, a full 64-bit write cycle requires a write
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* to the lower address, followed by a write to the higher address,
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* which will latch/execute the write cycle.
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*
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* For example, let's assume a SW reset of CAAM through the master
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* configuration register.
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* - SWRST is in bit 31 of MCFG.
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* - MCFG begins at base+0x0000.
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* - Bits 63-32 are a 32-bit word at base+0x0000 (numerically-lower)
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* - Bits 31-0 are a 32-bit word at base+0x0004 (numerically-higher)
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*
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* (and on Power, the convention is 0-31, 32-63, I know...)
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*
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* Assuming a 64-bit write to this MCFG to perform a software reset
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* would then require a write of 0 to base+0x0000, followed by a
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* write of 0x80000000 to base+0x0004, which would "execute" the
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* reset.
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*
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* Of course, since MCFG 63-32 is all zero, we could cheat and simply
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* write 0x8000000 to base+0x0004, and the reset would work fine.
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* However, since CAAM does contain some write-and-read-intended
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* 64-bit registers, this code defines 64-bit access methods for
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* the sake of internal consistency and simplicity, and so that a
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* clean transition to 64-bit is possible when it becomes necessary.
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*
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* There are limitations to this that the developer must recognize.
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* 32-bit architectures cannot enforce an atomic-64 operation,
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* Therefore:
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*
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* - On writes, since the HW is assumed to latch the cycle on the
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* write of the higher-numeric-address word, then ordered
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* writes work OK.
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*
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* - For reads, where a register contains a relevant value of more
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* that 32 bits, the hardware employs logic to latch the other
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* "half" of the data until read, ensuring an accurate value.
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* This is of particular relevance when dealing with CAAM's
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* performance counters.
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*
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*/
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#ifdef __BIG_ENDIAN
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#define wr_reg32(reg, data) out_be32(reg, data)
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#define rd_reg32(reg) in_be32(reg)
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#ifdef CONFIG_64BIT
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#define wr_reg64(reg, data) out_be64(reg, data)
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#define rd_reg64(reg) in_be64(reg)
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#endif
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#else
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#ifdef __LITTLE_ENDIAN
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#define wr_reg32(reg, data) __raw_writel(reg, data)
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#define rd_reg32(reg) __raw_readl(reg)
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#ifdef CONFIG_64BIT
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#define wr_reg64(reg, data) __raw_writeq(reg, data)
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#define rd_reg64(reg) __raw_readq(reg)
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#endif
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#endif
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#endif
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#ifndef CONFIG_64BIT
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static inline void wr_reg64(u64 __iomem *reg, u64 data)
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{
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wr_reg32((u32 __iomem *)reg, (data & 0xffffffff00000000ull) >> 32);
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wr_reg32((u32 __iomem *)reg + 1, data & 0x00000000ffffffffull);
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}
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static inline u64 rd_reg64(u64 __iomem *reg)
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{
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return (((u64)rd_reg32((u32 __iomem *)reg)) << 32) |
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((u64)rd_reg32((u32 __iomem *)reg + 1));
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}
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#endif
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/*
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* jr_outentry
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* Represents each entry in a JobR output ring
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*/
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struct jr_outentry {
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dma_addr_t desc;/* Pointer to completed descriptor */
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u32 jrstatus; /* Status for completed descriptor */
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} __packed;
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/*
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* caam_perfmon - Performance Monitor/Secure Memory Status/
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* CAAM Global Status/Component Version IDs
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*
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* Spans f00-fff wherever instantiated
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*/
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/* Number of DECOs */
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#define CHA_NUM_DECONUM_SHIFT 56
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#define CHA_NUM_DECONUM_MASK (0xfull << CHA_NUM_DECONUM_SHIFT)
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/* CHA Version IDs */
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#define CHA_ID_AES_SHIFT 0
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#define CHA_ID_AES_MASK (0xfull << CHA_ID_AES_SHIFT)
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#define CHA_ID_DES_SHIFT 4
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#define CHA_ID_DES_MASK (0xfull << CHA_ID_DES_SHIFT)
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#define CHA_ID_ARC4_SHIFT 8
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#define CHA_ID_ARC4_MASK (0xfull << CHA_ID_ARC4_SHIFT)
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#define CHA_ID_MD_SHIFT 12
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#define CHA_ID_MD_MASK (0xfull << CHA_ID_MD_SHIFT)
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#define CHA_ID_RNG_SHIFT 16
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#define CHA_ID_RNG_MASK (0xfull << CHA_ID_RNG_SHIFT)
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#define CHA_ID_SNW8_SHIFT 20
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#define CHA_ID_SNW8_MASK (0xfull << CHA_ID_SNW8_SHIFT)
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#define CHA_ID_KAS_SHIFT 24
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#define CHA_ID_KAS_MASK (0xfull << CHA_ID_KAS_SHIFT)
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#define CHA_ID_PK_SHIFT 28
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#define CHA_ID_PK_MASK (0xfull << CHA_ID_PK_SHIFT)
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#define CHA_ID_CRC_SHIFT 32
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#define CHA_ID_CRC_MASK (0xfull << CHA_ID_CRC_SHIFT)
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#define CHA_ID_SNW9_SHIFT 36
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#define CHA_ID_SNW9_MASK (0xfull << CHA_ID_SNW9_SHIFT)
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#define CHA_ID_DECO_SHIFT 56
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#define CHA_ID_DECO_MASK (0xfull << CHA_ID_DECO_SHIFT)
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#define CHA_ID_JR_SHIFT 60
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#define CHA_ID_JR_MASK (0xfull << CHA_ID_JR_SHIFT)
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struct sec_vid {
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u16 ip_id;
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u8 maj_rev;
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u8 min_rev;
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};
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struct caam_perfmon {
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/* Performance Monitor Registers f00-f9f */
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u64 req_dequeued; /* PC_REQ_DEQ - Dequeued Requests */
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u64 ob_enc_req; /* PC_OB_ENC_REQ - Outbound Encrypt Requests */
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u64 ib_dec_req; /* PC_IB_DEC_REQ - Inbound Decrypt Requests */
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u64 ob_enc_bytes; /* PC_OB_ENCRYPT - Outbound Bytes Encrypted */
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u64 ob_prot_bytes; /* PC_OB_PROTECT - Outbound Bytes Protected */
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u64 ib_dec_bytes; /* PC_IB_DECRYPT - Inbound Bytes Decrypted */
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u64 ib_valid_bytes; /* PC_IB_VALIDATED Inbound Bytes Validated */
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u64 rsvd[13];
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/* CAAM Hardware Instantiation Parameters fa0-fbf */
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u64 cha_rev; /* CRNR - CHA Revision Number */
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#define CTPR_QI_SHIFT 57
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#define CTPR_QI_MASK (0x1ull << CTPR_QI_SHIFT)
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u64 comp_parms; /* CTPR - Compile Parameters Register */
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u64 rsvd1[2];
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/* CAAM Global Status fc0-fdf */
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u64 faultaddr; /* FAR - Fault Address */
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u32 faultliodn; /* FALR - Fault Address LIODN */
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u32 faultdetail; /* FADR - Fault Addr Detail */
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u32 rsvd2;
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u32 status; /* CSTA - CAAM Status */
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u64 rsvd3;
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/* Component Instantiation Parameters fe0-fff */
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u32 rtic_id; /* RVID - RTIC Version ID */
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u32 ccb_id; /* CCBVID - CCB Version ID */
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u64 cha_id; /* CHAVID - CHA Version ID */
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u64 cha_num; /* CHANUM - CHA Number */
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u64 caam_id; /* CAAMVID - CAAM Version ID */
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};
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/* LIODN programming for DMA configuration */
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#define MSTRID_LOCK_LIODN 0x80000000
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#define MSTRID_LOCK_MAKETRUSTED 0x00010000 /* only for JR masterid */
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#define MSTRID_LIODN_MASK 0x0fff
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struct masterid {
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u32 liodn_ms; /* lock and make-trusted control bits */
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u32 liodn_ls; /* LIODN for non-sequence and seq access */
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};
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/* Partition ID for DMA configuration */
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struct partid {
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u32 rsvd1;
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u32 pidr; /* partition ID, DECO */
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};
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/* RNGB test mode (replicated twice in some configurations) */
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/* Padded out to 0x100 */
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struct rngtst {
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u32 mode; /* RTSTMODEx - Test mode */
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u32 rsvd1[3];
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u32 reset; /* RTSTRESETx - Test reset control */
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u32 rsvd2[3];
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u32 status; /* RTSTSSTATUSx - Test status */
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u32 rsvd3;
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u32 errstat; /* RTSTERRSTATx - Test error status */
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u32 rsvd4;
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u32 errctl; /* RTSTERRCTLx - Test error control */
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u32 rsvd5;
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u32 entropy; /* RTSTENTROPYx - Test entropy */
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u32 rsvd6[15];
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u32 verifctl; /* RTSTVERIFCTLx - Test verification control */
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u32 rsvd7;
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u32 verifstat; /* RTSTVERIFSTATx - Test verification status */
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u32 rsvd8;
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u32 verifdata; /* RTSTVERIFDx - Test verification data */
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u32 rsvd9;
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u32 xkey; /* RTSTXKEYx - Test XKEY */
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u32 rsvd10;
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u32 oscctctl; /* RTSTOSCCTCTLx - Test osc. counter control */
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u32 rsvd11;
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u32 oscct; /* RTSTOSCCTx - Test oscillator counter */
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u32 rsvd12;
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u32 oscctstat; /* RTSTODCCTSTATx - Test osc counter status */
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u32 rsvd13[2];
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u32 ofifo[4]; /* RTSTOFIFOx - Test output FIFO */
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u32 rsvd14[15];
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};
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/* RNG4 TRNG test registers */
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struct rng4tst {
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#define RTMCTL_PRGM 0x00010000 /* 1 -> program mode, 0 -> run mode */
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u32 rtmctl; /* misc. control register */
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u32 rtscmisc; /* statistical check misc. register */
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u32 rtpkrrng; /* poker range register */
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union {
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u32 rtpkrmax; /* PRGM=1: poker max. limit register */
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u32 rtpkrsq; /* PRGM=0: poker square calc. result register */
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};
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#define RTSDCTL_ENT_DLY_SHIFT 16
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#define RTSDCTL_ENT_DLY_MASK (0xffff << RTSDCTL_ENT_DLY_SHIFT)
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u32 rtsdctl; /* seed control register */
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union {
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u32 rtsblim; /* PRGM=1: sparse bit limit register */
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u32 rttotsam; /* PRGM=0: total samples register */
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};
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u32 rtfrqmin; /* frequency count min. limit register */
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union {
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u32 rtfrqmax; /* PRGM=1: freq. count max. limit register */
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u32 rtfrqcnt; /* PRGM=0: freq. count register */
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};
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u32 rsvd1[40];
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#define RDSTA_IF0 0x00000001
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u32 rdsta;
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u32 rsvd2[15];
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};
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/*
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* caam_ctrl - basic core configuration
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* starts base + 0x0000 padded out to 0x1000
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*/
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#define KEK_KEY_SIZE 8
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#define TKEK_KEY_SIZE 8
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#define TDSK_KEY_SIZE 8
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#define DECO_RESET 1 /* Use with DECO reset/availability regs */
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#define DECO_RESET_0 (DECO_RESET << 0)
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#define DECO_RESET_1 (DECO_RESET << 1)
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#define DECO_RESET_2 (DECO_RESET << 2)
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#define DECO_RESET_3 (DECO_RESET << 3)
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#define DECO_RESET_4 (DECO_RESET << 4)
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struct caam_ctrl {
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/* Basic Configuration Section 000-01f */
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/* Read/Writable */
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u32 rsvd1;
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u32 mcr; /* MCFG Master Config Register */
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u32 rsvd2;
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u32 scfgr; /* SCFGR, Security Config Register */
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/* Bus Access Configuration Section 010-11f */
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/* Read/Writable */
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struct masterid jr_mid[4]; /* JRxLIODNR - JobR LIODN setup */
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u32 rsvd3[12];
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struct masterid rtic_mid[4]; /* RTICxLIODNR - RTIC LIODN setup */
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u32 rsvd4[7];
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u32 deco_rq; /* DECORR - DECO Request */
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struct partid deco_mid[5]; /* DECOxLIODNR - 1 per DECO */
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u32 rsvd5[22];
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/* DECO Availability/Reset Section 120-3ff */
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u32 deco_avail; /* DAR - DECO availability */
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u32 deco_reset; /* DRR - DECO reset */
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u32 rsvd6[182];
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/* Key Encryption/Decryption Configuration 400-5ff */
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/* Read/Writable only while in Non-secure mode */
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u32 kek[KEK_KEY_SIZE]; /* JDKEKR - Key Encryption Key */
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u32 tkek[TKEK_KEY_SIZE]; /* TDKEKR - Trusted Desc KEK */
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u32 tdsk[TDSK_KEY_SIZE]; /* TDSKR - Trusted Desc Signing Key */
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u32 rsvd7[32];
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u64 sknonce; /* SKNR - Secure Key Nonce */
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u32 rsvd8[70];
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/* RNG Test/Verification/Debug Access 600-7ff */
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/* (Useful in Test/Debug modes only...) */
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union {
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struct rngtst rtst[2];
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struct rng4tst r4tst[2];
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};
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u32 rsvd9[448];
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/* Performance Monitor f00-fff */
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struct caam_perfmon perfmon;
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};
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/*
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* Controller master config register defs
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*/
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#define MCFGR_SWRESET 0x80000000 /* software reset */
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#define MCFGR_WDENABLE 0x40000000 /* DECO watchdog enable */
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#define MCFGR_WDFAIL 0x20000000 /* DECO watchdog force-fail */
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#define MCFGR_DMA_RESET 0x10000000
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#define MCFGR_LONG_PTR 0x00010000 /* Use >32-bit desc addressing */
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#define SCFGR_RDBENABLE 0x00000400
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/* AXI read cache control */
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#define MCFGR_ARCACHE_SHIFT 12
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#define MCFGR_ARCACHE_MASK (0xf << MCFGR_ARCACHE_SHIFT)
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/* AXI write cache control */
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#define MCFGR_AWCACHE_SHIFT 8
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#define MCFGR_AWCACHE_MASK (0xf << MCFGR_AWCACHE_SHIFT)
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/* AXI pipeline depth */
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#define MCFGR_AXIPIPE_SHIFT 4
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#define MCFGR_AXIPIPE_MASK (0xf << MCFGR_AXIPIPE_SHIFT)
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#define MCFGR_AXIPRI 0x00000008 /* Assert AXI priority sideband */
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#define MCFGR_BURST_64 0x00000001 /* Max burst size */
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/*
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* caam_job_ring - direct job ring setup
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* 1-4 possible per instantiation, base + 1000/2000/3000/4000
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* Padded out to 0x1000
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*/
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struct caam_job_ring {
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/* Input ring */
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u64 inpring_base; /* IRBAx - Input desc ring baseaddr */
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u32 rsvd1;
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u32 inpring_size; /* IRSx - Input ring size */
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u32 rsvd2;
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u32 inpring_avail; /* IRSAx - Input ring room remaining */
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u32 rsvd3;
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u32 inpring_jobadd; /* IRJAx - Input ring jobs added */
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/* Output Ring */
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u64 outring_base; /* ORBAx - Output status ring base addr */
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u32 rsvd4;
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u32 outring_size; /* ORSx - Output ring size */
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u32 rsvd5;
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u32 outring_rmvd; /* ORJRx - Output ring jobs removed */
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u32 rsvd6;
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u32 outring_used; /* ORSFx - Output ring slots full */
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/* Status/Configuration */
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u32 rsvd7;
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u32 jroutstatus; /* JRSTAx - JobR output status */
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u32 rsvd8;
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u32 jrintstatus; /* JRINTx - JobR interrupt status */
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u32 rconfig_hi; /* JRxCFG - Ring configuration */
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u32 rconfig_lo;
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/* Indices. CAAM maintains as "heads" of each queue */
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u32 rsvd9;
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u32 inp_rdidx; /* IRRIx - Input ring read index */
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u32 rsvd10;
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u32 out_wtidx; /* ORWIx - Output ring write index */
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/* Command/control */
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u32 rsvd11;
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u32 jrcommand; /* JRCRx - JobR command */
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u32 rsvd12[932];
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/* Performance Monitor f00-fff */
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struct caam_perfmon perfmon;
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};
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#define JR_RINGSIZE_MASK 0x03ff
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/*
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* jrstatus - Job Ring Output Status
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* All values in lo word
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* Also note, same values written out as status through QI
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* in the command/status field of a frame descriptor
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*/
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#define JRSTA_SSRC_SHIFT 28
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#define JRSTA_SSRC_MASK 0xf0000000
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#define JRSTA_SSRC_NONE 0x00000000
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#define JRSTA_SSRC_CCB_ERROR 0x20000000
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#define JRSTA_SSRC_JUMP_HALT_USER 0x30000000
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#define JRSTA_SSRC_DECO 0x40000000
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#define JRSTA_SSRC_JRERROR 0x60000000
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#define JRSTA_SSRC_JUMP_HALT_CC 0x70000000
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#define JRSTA_DECOERR_JUMP 0x08000000
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#define JRSTA_DECOERR_INDEX_SHIFT 8
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#define JRSTA_DECOERR_INDEX_MASK 0xff00
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#define JRSTA_DECOERR_ERROR_MASK 0x00ff
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#define JRSTA_DECOERR_NONE 0x00
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#define JRSTA_DECOERR_LINKLEN 0x01
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#define JRSTA_DECOERR_LINKPTR 0x02
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#define JRSTA_DECOERR_JRCTRL 0x03
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#define JRSTA_DECOERR_DESCCMD 0x04
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#define JRSTA_DECOERR_ORDER 0x05
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#define JRSTA_DECOERR_KEYCMD 0x06
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#define JRSTA_DECOERR_LOADCMD 0x07
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#define JRSTA_DECOERR_STORECMD 0x08
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#define JRSTA_DECOERR_OPCMD 0x09
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#define JRSTA_DECOERR_FIFOLDCMD 0x0a
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#define JRSTA_DECOERR_FIFOSTCMD 0x0b
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#define JRSTA_DECOERR_MOVECMD 0x0c
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#define JRSTA_DECOERR_JUMPCMD 0x0d
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#define JRSTA_DECOERR_MATHCMD 0x0e
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#define JRSTA_DECOERR_SHASHCMD 0x0f
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#define JRSTA_DECOERR_SEQCMD 0x10
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#define JRSTA_DECOERR_DECOINTERNAL 0x11
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#define JRSTA_DECOERR_SHDESCHDR 0x12
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#define JRSTA_DECOERR_HDRLEN 0x13
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#define JRSTA_DECOERR_BURSTER 0x14
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#define JRSTA_DECOERR_DESCSIGNATURE 0x15
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#define JRSTA_DECOERR_DMA 0x16
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#define JRSTA_DECOERR_BURSTFIFO 0x17
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#define JRSTA_DECOERR_JRRESET 0x1a
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#define JRSTA_DECOERR_JOBFAIL 0x1b
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#define JRSTA_DECOERR_DNRERR 0x80
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#define JRSTA_DECOERR_UNDEFPCL 0x81
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#define JRSTA_DECOERR_PDBERR 0x82
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#define JRSTA_DECOERR_ANRPLY_LATE 0x83
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#define JRSTA_DECOERR_ANRPLY_REPLAY 0x84
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#define JRSTA_DECOERR_SEQOVF 0x85
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#define JRSTA_DECOERR_INVSIGN 0x86
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#define JRSTA_DECOERR_DSASIGN 0x87
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#define JRSTA_CCBERR_JUMP 0x08000000
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#define JRSTA_CCBERR_INDEX_MASK 0xff00
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#define JRSTA_CCBERR_INDEX_SHIFT 8
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#define JRSTA_CCBERR_CHAID_MASK 0x00f0
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#define JRSTA_CCBERR_CHAID_SHIFT 4
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#define JRSTA_CCBERR_ERRID_MASK 0x000f
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#define JRSTA_CCBERR_CHAID_AES (0x01 << JRSTA_CCBERR_CHAID_SHIFT)
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#define JRSTA_CCBERR_CHAID_DES (0x02 << JRSTA_CCBERR_CHAID_SHIFT)
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#define JRSTA_CCBERR_CHAID_ARC4 (0x03 << JRSTA_CCBERR_CHAID_SHIFT)
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#define JRSTA_CCBERR_CHAID_MD (0x04 << JRSTA_CCBERR_CHAID_SHIFT)
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#define JRSTA_CCBERR_CHAID_RNG (0x05 << JRSTA_CCBERR_CHAID_SHIFT)
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#define JRSTA_CCBERR_CHAID_SNOW (0x06 << JRSTA_CCBERR_CHAID_SHIFT)
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#define JRSTA_CCBERR_CHAID_KASUMI (0x07 << JRSTA_CCBERR_CHAID_SHIFT)
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#define JRSTA_CCBERR_CHAID_PK (0x08 << JRSTA_CCBERR_CHAID_SHIFT)
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#define JRSTA_CCBERR_CHAID_CRC (0x09 << JRSTA_CCBERR_CHAID_SHIFT)
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#define JRSTA_CCBERR_ERRID_NONE 0x00
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#define JRSTA_CCBERR_ERRID_MODE 0x01
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#define JRSTA_CCBERR_ERRID_DATASIZ 0x02
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#define JRSTA_CCBERR_ERRID_KEYSIZ 0x03
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#define JRSTA_CCBERR_ERRID_PKAMEMSZ 0x04
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#define JRSTA_CCBERR_ERRID_PKBMEMSZ 0x05
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#define JRSTA_CCBERR_ERRID_SEQUENCE 0x06
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#define JRSTA_CCBERR_ERRID_PKDIVZRO 0x07
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#define JRSTA_CCBERR_ERRID_PKMODEVN 0x08
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#define JRSTA_CCBERR_ERRID_KEYPARIT 0x09
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#define JRSTA_CCBERR_ERRID_ICVCHK 0x0a
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#define JRSTA_CCBERR_ERRID_HARDWARE 0x0b
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#define JRSTA_CCBERR_ERRID_CCMAAD 0x0c
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#define JRSTA_CCBERR_ERRID_INVCHA 0x0f
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#define JRINT_ERR_INDEX_MASK 0x3fff0000
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#define JRINT_ERR_INDEX_SHIFT 16
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#define JRINT_ERR_TYPE_MASK 0xf00
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#define JRINT_ERR_TYPE_SHIFT 8
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#define JRINT_ERR_HALT_MASK 0xc
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#define JRINT_ERR_HALT_SHIFT 2
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#define JRINT_ERR_HALT_INPROGRESS 0x4
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#define JRINT_ERR_HALT_COMPLETE 0x8
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#define JRINT_JR_ERROR 0x02
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#define JRINT_JR_INT 0x01
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#define JRINT_ERR_TYPE_WRITE 1
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#define JRINT_ERR_TYPE_BAD_INPADDR 3
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#define JRINT_ERR_TYPE_BAD_OUTADDR 4
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#define JRINT_ERR_TYPE_INV_INPWRT 5
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#define JRINT_ERR_TYPE_INV_OUTWRT 6
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#define JRINT_ERR_TYPE_RESET 7
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#define JRINT_ERR_TYPE_REMOVE_OFL 8
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#define JRINT_ERR_TYPE_ADD_OFL 9
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#define JRCFG_SOE 0x04
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#define JRCFG_ICEN 0x02
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#define JRCFG_IMSK 0x01
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#define JRCFG_ICDCT_SHIFT 8
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#define JRCFG_ICTT_SHIFT 16
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#define JRCR_RESET 0x01
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/*
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* caam_assurance - Assurance Controller View
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* base + 0x6000 padded out to 0x1000
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|
*/
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|
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struct rtic_element {
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u64 address;
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u32 rsvd;
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u32 length;
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};
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struct rtic_block {
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struct rtic_element element[2];
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|
};
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|
|
|
struct rtic_memhash {
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|
u32 memhash_be[32];
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|
u32 memhash_le[32];
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|
};
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struct caam_assurance {
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/* Status/Command/Watchdog */
|
|
u32 rsvd1;
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|
u32 status; /* RSTA - Status */
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|
u32 rsvd2;
|
|
u32 cmd; /* RCMD - Command */
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|
u32 rsvd3;
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|
u32 ctrl; /* RCTL - Control */
|
|
u32 rsvd4;
|
|
u32 throttle; /* RTHR - Throttle */
|
|
u32 rsvd5[2];
|
|
u64 watchdog; /* RWDOG - Watchdog Timer */
|
|
u32 rsvd6;
|
|
u32 rend; /* REND - Endian corrections */
|
|
u32 rsvd7[50];
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|
|
|
/* Block access/configuration @ 100/110/120/130 */
|
|
struct rtic_block memblk[4]; /* Memory Blocks A-D */
|
|
u32 rsvd8[32];
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|
|
|
/* Block hashes @ 200/300/400/500 */
|
|
struct rtic_memhash hash[4]; /* Block hash values A-D */
|
|
u32 rsvd_3[640];
|
|
};
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|
|
|
/*
|
|
* caam_queue_if - QI configuration and control
|
|
* starts base + 0x7000, padded out to 0x1000 long
|
|
*/
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|
|
|
struct caam_queue_if {
|
|
u32 qi_control_hi; /* QICTL - QI Control */
|
|
u32 qi_control_lo;
|
|
u32 rsvd1;
|
|
u32 qi_status; /* QISTA - QI Status */
|
|
u32 qi_deq_cfg_hi; /* QIDQC - QI Dequeue Configuration */
|
|
u32 qi_deq_cfg_lo;
|
|
u32 qi_enq_cfg_hi; /* QISEQC - QI Enqueue Command */
|
|
u32 qi_enq_cfg_lo;
|
|
u32 rsvd2[1016];
|
|
};
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|
|
|
/* QI control bits - low word */
|
|
#define QICTL_DQEN 0x01 /* Enable frame pop */
|
|
#define QICTL_STOP 0x02 /* Stop dequeue/enqueue */
|
|
#define QICTL_SOE 0x04 /* Stop on error */
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|
|
|
/* QI control bits - high word */
|
|
#define QICTL_MBSI 0x01
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|
#define QICTL_MHWSI 0x02
|
|
#define QICTL_MWSI 0x04
|
|
#define QICTL_MDWSI 0x08
|
|
#define QICTL_CBSI 0x10 /* CtrlDataByteSwapInput */
|
|
#define QICTL_CHWSI 0x20 /* CtrlDataHalfSwapInput */
|
|
#define QICTL_CWSI 0x40 /* CtrlDataWordSwapInput */
|
|
#define QICTL_CDWSI 0x80 /* CtrlDataDWordSwapInput */
|
|
#define QICTL_MBSO 0x0100
|
|
#define QICTL_MHWSO 0x0200
|
|
#define QICTL_MWSO 0x0400
|
|
#define QICTL_MDWSO 0x0800
|
|
#define QICTL_CBSO 0x1000 /* CtrlDataByteSwapOutput */
|
|
#define QICTL_CHWSO 0x2000 /* CtrlDataHalfSwapOutput */
|
|
#define QICTL_CWSO 0x4000 /* CtrlDataWordSwapOutput */
|
|
#define QICTL_CDWSO 0x8000 /* CtrlDataDWordSwapOutput */
|
|
#define QICTL_DMBS 0x010000
|
|
#define QICTL_EPO 0x020000
|
|
|
|
/* QI status bits */
|
|
#define QISTA_PHRDERR 0x01 /* PreHeader Read Error */
|
|
#define QISTA_CFRDERR 0x02 /* Compound Frame Read Error */
|
|
#define QISTA_OFWRERR 0x04 /* Output Frame Read Error */
|
|
#define QISTA_BPDERR 0x08 /* Buffer Pool Depleted */
|
|
#define QISTA_BTSERR 0x10 /* Buffer Undersize */
|
|
#define QISTA_CFWRERR 0x20 /* Compound Frame Write Err */
|
|
#define QISTA_STOPD 0x80000000 /* QI Stopped (see QICTL) */
|
|
|
|
/* deco_sg_table - DECO view of scatter/gather table */
|
|
struct deco_sg_table {
|
|
u64 addr; /* Segment Address */
|
|
u32 elen; /* E, F bits + 30-bit length */
|
|
u32 bpid_offset; /* Buffer Pool ID + 16-bit length */
|
|
};
|
|
|
|
/*
|
|
* caam_deco - descriptor controller - CHA cluster block
|
|
*
|
|
* Only accessible when direct DECO access is turned on
|
|
* (done in DECORR, via MID programmed in DECOxMID
|
|
*
|
|
* 5 typical, base + 0x8000/9000/a000/b000
|
|
* Padded out to 0x1000 long
|
|
*/
|
|
struct caam_deco {
|
|
u32 rsvd1;
|
|
u32 cls1_mode; /* CxC1MR - Class 1 Mode */
|
|
u32 rsvd2;
|
|
u32 cls1_keysize; /* CxC1KSR - Class 1 Key Size */
|
|
u32 cls1_datasize_hi; /* CxC1DSR - Class 1 Data Size */
|
|
u32 cls1_datasize_lo;
|
|
u32 rsvd3;
|
|
u32 cls1_icvsize; /* CxC1ICVSR - Class 1 ICV size */
|
|
u32 rsvd4[5];
|
|
u32 cha_ctrl; /* CCTLR - CHA control */
|
|
u32 rsvd5;
|
|
u32 irq_crtl; /* CxCIRQ - CCB interrupt done/error/clear */
|
|
u32 rsvd6;
|
|
u32 clr_written; /* CxCWR - Clear-Written */
|
|
u32 ccb_status_hi; /* CxCSTA - CCB Status/Error */
|
|
u32 ccb_status_lo;
|
|
u32 rsvd7[3];
|
|
u32 aad_size; /* CxAADSZR - Current AAD Size */
|
|
u32 rsvd8;
|
|
u32 cls1_iv_size; /* CxC1IVSZR - Current Class 1 IV Size */
|
|
u32 rsvd9[7];
|
|
u32 pkha_a_size; /* PKASZRx - Size of PKHA A */
|
|
u32 rsvd10;
|
|
u32 pkha_b_size; /* PKBSZRx - Size of PKHA B */
|
|
u32 rsvd11;
|
|
u32 pkha_n_size; /* PKNSZRx - Size of PKHA N */
|
|
u32 rsvd12;
|
|
u32 pkha_e_size; /* PKESZRx - Size of PKHA E */
|
|
u32 rsvd13[24];
|
|
u32 cls1_ctx[16]; /* CxC1CTXR - Class 1 Context @100 */
|
|
u32 rsvd14[48];
|
|
u32 cls1_key[8]; /* CxC1KEYR - Class 1 Key @200 */
|
|
u32 rsvd15[121];
|
|
u32 cls2_mode; /* CxC2MR - Class 2 Mode */
|
|
u32 rsvd16;
|
|
u32 cls2_keysize; /* CxX2KSR - Class 2 Key Size */
|
|
u32 cls2_datasize_hi; /* CxC2DSR - Class 2 Data Size */
|
|
u32 cls2_datasize_lo;
|
|
u32 rsvd17;
|
|
u32 cls2_icvsize; /* CxC2ICVSZR - Class 2 ICV Size */
|
|
u32 rsvd18[56];
|
|
u32 cls2_ctx[18]; /* CxC2CTXR - Class 2 Context @500 */
|
|
u32 rsvd19[46];
|
|
u32 cls2_key[32]; /* CxC2KEYR - Class2 Key @600 */
|
|
u32 rsvd20[84];
|
|
u32 inp_infofifo_hi; /* CxIFIFO - Input Info FIFO @7d0 */
|
|
u32 inp_infofifo_lo;
|
|
u32 rsvd21[2];
|
|
u64 inp_datafifo; /* CxDFIFO - Input Data FIFO */
|
|
u32 rsvd22[2];
|
|
u64 out_datafifo; /* CxOFIFO - Output Data FIFO */
|
|
u32 rsvd23[2];
|
|
u32 jr_ctl_hi; /* CxJRR - JobR Control Register @800 */
|
|
u32 jr_ctl_lo;
|
|
u64 jr_descaddr; /* CxDADR - JobR Descriptor Address */
|
|
u32 op_status_hi; /* DxOPSTA - DECO Operation Status */
|
|
u32 op_status_lo;
|
|
u32 rsvd24[2];
|
|
u32 liodn; /* DxLSR - DECO LIODN Status - non-seq */
|
|
u32 td_liodn; /* DxLSR - DECO LIODN Status - trustdesc */
|
|
u32 rsvd26[6];
|
|
u64 math[4]; /* DxMTH - Math register */
|
|
u32 rsvd27[8];
|
|
struct deco_sg_table gthr_tbl[4]; /* DxGTR - Gather Tables */
|
|
u32 rsvd28[16];
|
|
struct deco_sg_table sctr_tbl[4]; /* DxSTR - Scatter Tables */
|
|
u32 rsvd29[48];
|
|
u32 descbuf[64]; /* DxDESB - Descriptor buffer */
|
|
u32 rsvd30[320];
|
|
};
|
|
|
|
/*
|
|
* Current top-level view of memory map is:
|
|
*
|
|
* 0x0000 - 0x0fff - CAAM Top-Level Control
|
|
* 0x1000 - 0x1fff - Job Ring 0
|
|
* 0x2000 - 0x2fff - Job Ring 1
|
|
* 0x3000 - 0x3fff - Job Ring 2
|
|
* 0x4000 - 0x4fff - Job Ring 3
|
|
* 0x5000 - 0x5fff - (unused)
|
|
* 0x6000 - 0x6fff - Assurance Controller
|
|
* 0x7000 - 0x7fff - Queue Interface
|
|
* 0x8000 - 0x8fff - DECO-CCB 0
|
|
* 0x9000 - 0x9fff - DECO-CCB 1
|
|
* 0xa000 - 0xafff - DECO-CCB 2
|
|
* 0xb000 - 0xbfff - DECO-CCB 3
|
|
* 0xc000 - 0xcfff - DECO-CCB 4
|
|
*
|
|
* caam_full describes the full register view of CAAM if useful,
|
|
* although many configurations may choose to implement parts of
|
|
* the register map separately, in differing privilege regions
|
|
*/
|
|
struct caam_full {
|
|
struct caam_ctrl __iomem ctrl;
|
|
struct caam_job_ring jr[4];
|
|
u64 rsvd[512];
|
|
struct caam_assurance assure;
|
|
struct caam_queue_if qi;
|
|
};
|
|
|
|
#endif /* REGS_H */
|