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c1273af4b9
The sor1 clock on Tegra210 is structured in the following way:
+-------+
| pllp |---+
+-------+ | +--------------+ +-----------+
+----| | | sor_safe |
+-------+ | | +-----------+
| plld |--------| | |
+-------+ | | +-----------+
| sor1_src |-------| |
+-------+ | | +-----------+
| plld2 |--------| | |
+-------+ | | |
+----| | |
+-------+ | +--------------+ |
| clkm |---+ +-----------+
+-------+ +--------------+ | |
| sor1_brick |-------| sor1 |
+--------------+ | |
+-----------+
This is impractical to represent in a clock tree, though, because there
is no name for the mux that has sor_safe and sor1_src as parents. It is
also much more cumbersome to deal with the additional mux because users
of these clocks (the display driver) would have to juggle with an extra
mux for no real reason.
To simply things, the above is squashed into two muxes instead, so that
it looks like this:
+-------+
| pllp |---+
+-------+ | +--------------+ +-----------+
+----| | | sor_safe |
+-------+ | | +-----------+
| plld |--------| | |
+-------+ | | +-----------+
| sor1_src |-------| sor1 |
+-------+ | | +-----------+
| plld2 |--------| | | |
+-------+ | | | |
+----| | | |
+-------+ | +--------------+ | |
| clkm |---+ | |
+-------+ +--------------+ | |
| sor1_brick |-----------+---+
+--------------+
This still very accurately represents the hardware. Note that sor1 has
sor1_brick as input twice, that's because bit 1 in the mux selects the
sor1_brick irrespective of bit 0.
Signed-off-by: Thierry Reding <treding@nvidia.com>
314 lines
6.1 KiB
C
314 lines
6.1 KiB
C
/*
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* This header provides IDs for clocks common between several Tegra SoCs
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*/
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#ifndef _TEGRA_CLK_ID_H
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#define _TEGRA_CLK_ID_H
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enum clk_id {
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tegra_clk_actmon,
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tegra_clk_adx,
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tegra_clk_adx1,
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tegra_clk_afi,
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tegra_clk_amx,
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tegra_clk_amx1,
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tegra_clk_apb2ape,
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tegra_clk_apbdma,
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tegra_clk_apbif,
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tegra_clk_ape,
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tegra_clk_audio0,
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tegra_clk_audio0_2x,
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tegra_clk_audio0_mux,
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tegra_clk_audio1,
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tegra_clk_audio1_2x,
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tegra_clk_audio1_mux,
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tegra_clk_audio2,
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tegra_clk_audio2_2x,
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tegra_clk_audio2_mux,
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tegra_clk_audio3,
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tegra_clk_audio3_2x,
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tegra_clk_audio3_mux,
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tegra_clk_audio4,
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tegra_clk_audio4_2x,
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tegra_clk_audio4_mux,
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tegra_clk_blink,
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tegra_clk_bsea,
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tegra_clk_bsev,
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tegra_clk_cclk_g,
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tegra_clk_cclk_lp,
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tegra_clk_cilab,
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tegra_clk_cilcd,
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tegra_clk_cile,
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tegra_clk_clk_32k,
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tegra_clk_clk72Mhz,
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tegra_clk_clk72Mhz_8,
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tegra_clk_clk_m,
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tegra_clk_clk_m_div2,
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tegra_clk_clk_m_div4,
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tegra_clk_clk_out_1,
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tegra_clk_clk_out_1_mux,
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tegra_clk_clk_out_2,
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tegra_clk_clk_out_2_mux,
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tegra_clk_clk_out_3,
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tegra_clk_clk_out_3_mux,
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tegra_clk_cml0,
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tegra_clk_cml1,
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tegra_clk_csi,
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tegra_clk_csite,
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tegra_clk_csite_8,
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tegra_clk_csus,
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tegra_clk_cve,
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tegra_clk_dam0,
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tegra_clk_dam1,
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tegra_clk_dam2,
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tegra_clk_d_audio,
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tegra_clk_dbgapb,
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tegra_clk_dds,
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tegra_clk_dfll_ref,
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tegra_clk_dfll_soc,
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tegra_clk_disp1,
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tegra_clk_disp1_8,
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tegra_clk_disp2,
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tegra_clk_disp2_8,
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tegra_clk_dp2,
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tegra_clk_dpaux,
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tegra_clk_dpaux1,
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tegra_clk_dsialp,
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tegra_clk_dsia_mux,
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tegra_clk_dsiblp,
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tegra_clk_dsib_mux,
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tegra_clk_dtv,
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tegra_clk_emc,
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tegra_clk_entropy,
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tegra_clk_entropy_8,
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tegra_clk_epp,
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tegra_clk_epp_8,
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tegra_clk_extern1,
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tegra_clk_extern2,
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tegra_clk_extern3,
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tegra_clk_fuse,
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tegra_clk_fuse_burn,
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tegra_clk_gpu,
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tegra_clk_gr2d,
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tegra_clk_gr2d_8,
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tegra_clk_gr3d,
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tegra_clk_gr3d_8,
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tegra_clk_hclk,
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tegra_clk_hda,
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tegra_clk_hda_8,
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tegra_clk_hda2codec_2x,
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tegra_clk_hda2codec_2x_8,
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tegra_clk_hda2hdmi,
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tegra_clk_hdmi,
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tegra_clk_hdmi_audio,
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tegra_clk_host1x,
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tegra_clk_host1x_8,
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tegra_clk_host1x_9,
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tegra_clk_hsic_trk,
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tegra_clk_i2c1,
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tegra_clk_i2c2,
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tegra_clk_i2c3,
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tegra_clk_i2c4,
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tegra_clk_i2c5,
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tegra_clk_i2c6,
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tegra_clk_i2cslow,
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tegra_clk_i2s0,
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tegra_clk_i2s0_sync,
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tegra_clk_i2s1,
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tegra_clk_i2s1_sync,
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tegra_clk_i2s2,
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tegra_clk_i2s2_sync,
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tegra_clk_i2s3,
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tegra_clk_i2s3_sync,
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tegra_clk_i2s4,
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tegra_clk_i2s4_sync,
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tegra_clk_isp,
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tegra_clk_isp_8,
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tegra_clk_isp_9,
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tegra_clk_ispb,
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tegra_clk_kbc,
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tegra_clk_kfuse,
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tegra_clk_la,
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tegra_clk_maud,
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tegra_clk_mipi,
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tegra_clk_mipibif,
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tegra_clk_mipi_cal,
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tegra_clk_mpe,
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tegra_clk_mselect,
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tegra_clk_msenc,
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tegra_clk_ndflash,
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tegra_clk_ndflash_8,
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tegra_clk_ndspeed,
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tegra_clk_ndspeed_8,
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tegra_clk_nor,
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tegra_clk_nvdec,
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tegra_clk_nvenc,
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tegra_clk_nvjpg,
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tegra_clk_owr,
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tegra_clk_owr_8,
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tegra_clk_pcie,
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tegra_clk_pclk,
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tegra_clk_pll_a,
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tegra_clk_pll_a_out0,
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tegra_clk_pll_a1,
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tegra_clk_pll_c,
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tegra_clk_pll_c2,
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tegra_clk_pll_c3,
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tegra_clk_pll_c4,
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tegra_clk_pll_c4_out0,
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tegra_clk_pll_c4_out1,
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tegra_clk_pll_c4_out2,
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tegra_clk_pll_c4_out3,
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tegra_clk_pll_c_out1,
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tegra_clk_pll_d,
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tegra_clk_pll_d2,
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tegra_clk_pll_d2_out0,
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tegra_clk_pll_d_out0,
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tegra_clk_pll_dp,
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tegra_clk_pll_e_out0,
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tegra_clk_pll_g_ref,
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tegra_clk_pll_m,
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tegra_clk_pll_m_out1,
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tegra_clk_pll_mb,
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tegra_clk_pll_p,
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tegra_clk_pll_p_out1,
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tegra_clk_pll_p_out2,
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tegra_clk_pll_p_out2_int,
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tegra_clk_pll_p_out3,
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tegra_clk_pll_p_out4,
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tegra_clk_pll_p_out4_cpu,
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tegra_clk_pll_p_out5,
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tegra_clk_pll_p_out_hsio,
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tegra_clk_pll_p_out_xusb,
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tegra_clk_pll_p_out_cpu,
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tegra_clk_pll_p_out_adsp,
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tegra_clk_pll_ref,
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tegra_clk_pll_re_out,
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tegra_clk_pll_re_vco,
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tegra_clk_pll_u,
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tegra_clk_pll_u_out,
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tegra_clk_pll_u_out1,
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tegra_clk_pll_u_out2,
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tegra_clk_pll_u_12m,
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tegra_clk_pll_u_480m,
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tegra_clk_pll_u_48m,
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tegra_clk_pll_u_60m,
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tegra_clk_pll_x,
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tegra_clk_pll_x_out0,
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tegra_clk_pwm,
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tegra_clk_qspi,
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tegra_clk_rtc,
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tegra_clk_sata,
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tegra_clk_sata_8,
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tegra_clk_sata_cold,
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tegra_clk_sata_oob,
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tegra_clk_sata_oob_8,
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tegra_clk_sbc1,
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tegra_clk_sbc1_8,
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tegra_clk_sbc1_9,
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tegra_clk_sbc2,
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tegra_clk_sbc2_8,
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tegra_clk_sbc2_9,
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tegra_clk_sbc3,
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tegra_clk_sbc3_8,
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tegra_clk_sbc3_9,
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tegra_clk_sbc4,
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tegra_clk_sbc4_8,
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tegra_clk_sbc4_9,
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tegra_clk_sbc5,
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tegra_clk_sbc5_8,
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tegra_clk_sbc6,
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tegra_clk_sbc6_8,
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tegra_clk_sclk,
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tegra_clk_sdmmc_legacy,
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tegra_clk_sdmmc1,
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tegra_clk_sdmmc1_8,
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tegra_clk_sdmmc1_9,
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tegra_clk_sdmmc2,
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tegra_clk_sdmmc2_8,
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tegra_clk_sdmmc2_9,
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tegra_clk_sdmmc3,
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tegra_clk_sdmmc3_8,
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tegra_clk_sdmmc3_9,
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tegra_clk_sdmmc4,
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tegra_clk_sdmmc4_8,
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tegra_clk_sdmmc4_9,
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tegra_clk_se,
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tegra_clk_soc_therm,
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tegra_clk_soc_therm_8,
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tegra_clk_sor0,
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tegra_clk_sor0_lvds,
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tegra_clk_sor1,
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tegra_clk_sor1_src,
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tegra_clk_spdif,
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tegra_clk_spdif_2x,
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tegra_clk_spdif_in,
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tegra_clk_spdif_in_8,
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tegra_clk_spdif_in_sync,
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tegra_clk_spdif_mux,
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tegra_clk_spdif_out,
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tegra_clk_timer,
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tegra_clk_trace,
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tegra_clk_tsec,
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tegra_clk_tsec_8,
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tegra_clk_tsecb,
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tegra_clk_tsensor,
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tegra_clk_tvdac,
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tegra_clk_tvo,
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tegra_clk_uarta,
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tegra_clk_uarta_8,
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tegra_clk_uartb,
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tegra_clk_uartb_8,
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tegra_clk_uartc,
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tegra_clk_uartc_8,
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tegra_clk_uartd,
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tegra_clk_uartd_8,
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tegra_clk_uarte,
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tegra_clk_uarte_8,
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tegra_clk_uartape,
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tegra_clk_usb2,
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tegra_clk_usb2_hsic_trk,
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tegra_clk_usb2_trk,
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tegra_clk_usb3,
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tegra_clk_usbd,
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tegra_clk_vcp,
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tegra_clk_vde,
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tegra_clk_vde_8,
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tegra_clk_vfir,
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tegra_clk_vi,
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tegra_clk_vi_8,
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tegra_clk_vi_9,
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tegra_clk_vi_10,
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tegra_clk_vi_i2c,
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tegra_clk_vic03,
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tegra_clk_vic03_8,
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tegra_clk_vim2_clk,
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tegra_clk_vimclk_sync,
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tegra_clk_vi_sensor,
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tegra_clk_vi_sensor_8,
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tegra_clk_vi_sensor_9,
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tegra_clk_vi_sensor2,
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tegra_clk_vi_sensor2_8,
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tegra_clk_xusb_dev,
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tegra_clk_xusb_dev_src,
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tegra_clk_xusb_dev_src_8,
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tegra_clk_xusb_falcon_src,
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tegra_clk_xusb_falcon_src_8,
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tegra_clk_xusb_fs_src,
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tegra_clk_xusb_gate,
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tegra_clk_xusb_host,
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tegra_clk_xusb_host_src,
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tegra_clk_xusb_host_src_8,
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tegra_clk_xusb_hs_src,
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tegra_clk_xusb_hs_src_4,
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tegra_clk_xusb_ss,
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tegra_clk_xusb_ss_src,
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tegra_clk_xusb_ss_src_8,
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tegra_clk_xusb_ss_div2,
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tegra_clk_xusb_ssp_src,
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tegra_clk_sclk_mux,
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tegra_clk_sor_safe,
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tegra_clk_max,
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};
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#endif /* _TEGRA_CLK_ID_H */
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