mirror of
https://github.com/torvalds/linux.git
synced 2024-11-19 18:41:48 +00:00
740a01eee9
This patch adds support for v5 of SYSMMU controller, found in Samsung Exynos 5433 SoCs. The main difference of v5 is support for 36-bit physical address space and some changes in register layout and core clocks hanging. This patch also adds support for ARM64 architecture, which is used by Exynos 5433 SoCs. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Joerg Roedel <jroedel@suse.de>
69 lines
2.8 KiB
Plaintext
69 lines
2.8 KiB
Plaintext
Samsung Exynos IOMMU H/W, System MMU (System Memory Management Unit)
|
|
|
|
Samsung's Exynos architecture contains System MMUs that enables scattered
|
|
physical memory chunks visible as a contiguous region to DMA-capable peripheral
|
|
devices like MFC, FIMC, FIMD, GScaler, FIMC-IS and so forth.
|
|
|
|
System MMU is an IOMMU and supports identical translation table format to
|
|
ARMv7 translation tables with minimum set of page properties including access
|
|
permissions, shareability and security protection. In addition, System MMU has
|
|
another capabilities like L2 TLB or block-fetch buffers to minimize translation
|
|
latency.
|
|
|
|
System MMUs are in many to one relation with peripheral devices, i.e. single
|
|
peripheral device might have multiple System MMUs (usually one for each bus
|
|
master), but one System MMU can handle transactions from only one peripheral
|
|
device. The relation between a System MMU and the peripheral device needs to be
|
|
defined in device node of the peripheral device.
|
|
|
|
MFC in all Exynos SoCs and FIMD, M2M Scalers and G2D in Exynos5420 has 2 System
|
|
MMUs.
|
|
* MFC has one System MMU on its left and right bus.
|
|
* FIMD in Exynos5420 has one System MMU for window 0 and 4, the other system MMU
|
|
for window 1, 2 and 3.
|
|
* M2M Scalers and G2D in Exynos5420 has one System MMU on the read channel and
|
|
the other System MMU on the write channel.
|
|
|
|
For information on assigning System MMU controller to its peripheral devices,
|
|
see generic IOMMU bindings.
|
|
|
|
Required properties:
|
|
- compatible: Should be "samsung,exynos-sysmmu"
|
|
- reg: A tuple of base address and size of System MMU registers.
|
|
- #iommu-cells: Should be <0>.
|
|
- interrupt-parent: The phandle of the interrupt controller of System MMU
|
|
- interrupts: An interrupt specifier for interrupt signal of System MMU,
|
|
according to the format defined by a particular interrupt
|
|
controller.
|
|
- clock-names: Should be "sysmmu" or a pair of "aclk" and "pclk" to gate
|
|
SYSMMU core clocks.
|
|
Optional "master" if the clock to the System MMU is gated by
|
|
another gate clock other core (usually main gate clock
|
|
of peripheral device this SYSMMU belongs to).
|
|
- clocks: Phandles for respective clocks described by clock-names.
|
|
- power-domains: Required if the System MMU is needed to gate its power.
|
|
Please refer to the following document:
|
|
Documentation/devicetree/bindings/power/pd-samsung.txt
|
|
|
|
Examples:
|
|
gsc_0: gsc@13e00000 {
|
|
compatible = "samsung,exynos5-gsc";
|
|
reg = <0x13e00000 0x1000>;
|
|
interrupts = <0 85 0>;
|
|
power-domains = <&pd_gsc>;
|
|
clocks = <&clock CLK_GSCL0>;
|
|
clock-names = "gscl";
|
|
iommus = <&sysmmu_gsc0>;
|
|
};
|
|
|
|
sysmmu_gsc0: sysmmu@13E80000 {
|
|
compatible = "samsung,exynos-sysmmu";
|
|
reg = <0x13E80000 0x1000>;
|
|
interrupt-parent = <&combiner>;
|
|
interrupts = <2 0>;
|
|
clock-names = "sysmmu", "master";
|
|
clocks = <&clock CLK_SMMU_GSCL0>, <&clock CLK_GSCL0>;
|
|
power-domains = <&pd_gsc>;
|
|
#iommu-cells = <0>;
|
|
};
|