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52ea7c0543
Add StarFive JH7110(TX0/TX1/RX channels) SoC support in the designware I2S driver and a flag to check if it is on the JH7110 SoC. These channels need to enable clocks, resets and syscon register on the JH7110 SoC. So add init ops in platform data for the JH7110 SoC to do this. Their resets should be deassert before changing the parent of clocks so these are done in the init ops of platform data. The I2S controllers use DMA controller by platform data on the JH7110 and their settings about snd_dmaengine_dai_dma_data() should be added in the dw_configure_dai_by_pd(). And use dmaengine PCM registration if these do not have IRQ on the JH7110 SoC. Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com> Link: https://lore.kernel.org/r/20230821144151.207339-4-xingyu.wu@starfivetech.com Signed-off-by: Mark Brown <broonie@kernel.org>
68 lines
1.7 KiB
C
68 lines
1.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* Copyright (ST) 2012 Rajeev Kumar (rajeevkumar.linux@gmail.com)
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*/
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#ifndef __SOUND_DESIGNWARE_I2S_H
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#define __SOUND_DESIGNWARE_I2S_H
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#include <linux/dmaengine.h>
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#include <linux/types.h>
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/*
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* struct i2s_clk_config_data - represent i2s clk configuration data
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* @chan_nr: number of channel
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* @data_width: number of bits per sample (8/16/24/32 bit)
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* @sample_rate: sampling frequency (8Khz, 16Khz, 32Khz, 44Khz, 48Khz)
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*/
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struct i2s_clk_config_data {
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int chan_nr;
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u32 data_width;
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u32 sample_rate;
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};
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struct dw_i2s_dev;
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struct i2s_platform_data {
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#define DWC_I2S_PLAY (1 << 0)
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#define DWC_I2S_RECORD (1 << 1)
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#define DW_I2S_SLAVE (1 << 2)
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#define DW_I2S_MASTER (1 << 3)
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unsigned int cap;
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int channel;
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u32 snd_fmts;
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u32 snd_rates;
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#define DW_I2S_QUIRK_COMP_REG_OFFSET (1 << 0)
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#define DW_I2S_QUIRK_COMP_PARAM1 (1 << 1)
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#define DW_I2S_QUIRK_16BIT_IDX_OVERRIDE (1 << 2)
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unsigned int quirks;
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unsigned int i2s_reg_comp1;
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unsigned int i2s_reg_comp2;
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void *play_dma_data;
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void *capture_dma_data;
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bool (*filter)(struct dma_chan *chan, void *slave);
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int (*i2s_clk_cfg)(struct i2s_clk_config_data *config);
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int (*i2s_pd_init)(struct dw_i2s_dev *dev);
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};
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struct i2s_dma_data {
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void *data;
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dma_addr_t addr;
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u32 max_burst;
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enum dma_slave_buswidth addr_width;
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bool (*filter)(struct dma_chan *chan, void *slave);
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};
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/* I2S DMA registers */
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#define I2S_RXDMA 0x01C0
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#define I2S_TXDMA 0x01C8
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#define TWO_CHANNEL_SUPPORT 2 /* up to 2.0 */
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#define FOUR_CHANNEL_SUPPORT 4 /* up to 3.1 */
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#define SIX_CHANNEL_SUPPORT 6 /* up to 5.1 */
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#define EIGHT_CHANNEL_SUPPORT 8 /* up to 7.1 */
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#endif /* __SOUND_DESIGNWARE_I2S_H */
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