Neil Armstrong 72bea132f3 dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: document PHY AUX clock on SM8[456]50 SoCs ... The PCIe Gen4x2 PHY found in the SM8[456]50 SoCs have a second clock named "PHY_AUX_CLK" which is an input of the Global Clock Controller (GCC) which is muxed & gated then returned to the PHY as an input. Document the clock IDs to select the PIPE clock or the AUX clock, also enforce a second clock-output-names and a #clock-cells value of 1 for the PCIe Gen4x2 PHY found in the SM8[456]50 SoCs. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20240322-topic-sm8x50-upstream-pcie-1-phy-aux-clk-v2-1-3ec0a966d52f@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>		2024-04-05 22:34:00 +05:30
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phy-am654-serdes.h
phy-cadence.h	dt-bindings: phy: cadence-sierra: Add clock ID for derived reference clock	2021-12-27 16:35:09 +05:30
phy-imx8-pcie.h	dt-bindings: phy: phy-imx8-pcie: Add binding for the pad modes of imx8 pcie phy	2021-12-14 20:02:32 +05:30
phy-lan966x-serdes.h	dt-bindings: phy: Add constants for lan966x serdes	2021-11-23 13:09:08 +05:30
phy-lantiq-vrx200-pcie.h	dt-bindings: phy: add binding for the Lantiq VRX200 and ARX300 PCIe PHYs	2019-08-23 09:40:46 +05:30
phy-ocelot-serdes.h
phy-pistachio-usb.h	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 422	2019-06-05 17:37:15 +02:00
phy-qcom-qmp.h	dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: document PHY AUX clock on SM8[456]50 SoCs	2024-04-05 22:34:00 +05:30
phy-qcom-qusb2.h
phy-ti.h	dt-bindings: phy: ti,phy-j721e-wiz: Add bindings for AM64 SERDES Wrapper	2021-03-17 12:02:40 +05:30
phy.h	dt-bindings: phy: Add PHY_TYPE_USXGMII definition	2022-08-30 10:42:57 +05:30