linux/drivers/watchdog/octeon-wdt-nmi.S
Bagas Sanjaya a0d261ccd7 watchdog: Convert GPL 2.0 notice to SPDX identifier
Convert the boilerplate to SPDX license identifier. While at it, also
move SPDX identifier for drivers/watchdog/rtd119x_wdt.c to the top of
file (as in other files).

Cc: Ray Lehtiniemi <rayl@mail.com>,
Cc: Alessandro Zummo <a.zummo@towertech.it>
Cc: H Hartley Sweeten <hsweeten@visionengravers.com>
Cc: Deepak Saxena <dsaxena@plexity.net>
Cc: Marc Zyngier <maz@kernel.org>
Cc: Jonas Jensen <jonas.jensen@gmail.com>
Cc: Sylver Bruneau <sylver.bruneau@googlemail.com>
Cc: Denis Turischev <denis@compulab.co.il>
Cc: Mika Westerberg <mika.westerberg@linux.intel.com>
Acked-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Bagas Sanjaya <bagasdotme@gmail.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Acked-by: Ray Lehtiniemi <rayl@mail.com>
Reviewed-by: Guenter Roeck <linux@roeck-us.net>
Link: https://lkml.kernel.org/r/20230517072140.1086660-2-bagasdotme@gmail.com
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Wim Van Sebroeck <wim@linux-watchdog.org>
2023-06-26 14:30:04 +02:00

88 lines
1.9 KiB
ArmAsm

/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (C) 2007-2017 Cavium, Inc.
*/
#include <asm/asm.h>
#include <asm/regdef.h>
#define CVMSEG_BASE -32768
#define CVMSEG_SIZE 6912
#define SAVE_REG(r) sd $r, CVMSEG_BASE + CVMSEG_SIZE - ((32 - r) * 8)($0)
NESTED(octeon_wdt_nmi_stage2, 0, sp)
.set push
.set noreorder
.set noat
/* Clear Dcache so cvmseg works right. */
cache 1,0($0)
/* Use K0 to do a read/modify/write of CVMMEMCTL */
dmfc0 k0, $11, 7
/* Clear out the size of CVMSEG */
dins k0, $0, 0, 6
/* Set CVMSEG to its largest value */
ori k0, k0, 0x1c0 | 54
/* Store the CVMMEMCTL value */
dmtc0 k0, $11, 7
/*
* Restore K0 from the debug scratch register, it was saved in
* the boot-vector code.
*/
dmfc0 k0, $31
/*
* Save all registers to the top CVMSEG. This shouldn't
* corrupt any state used by the kernel. Also all registers
* should have the value right before the NMI.
*/
SAVE_REG(0)
SAVE_REG(1)
SAVE_REG(2)
SAVE_REG(3)
SAVE_REG(4)
SAVE_REG(5)
SAVE_REG(6)
SAVE_REG(7)
SAVE_REG(8)
SAVE_REG(9)
SAVE_REG(10)
SAVE_REG(11)
SAVE_REG(12)
SAVE_REG(13)
SAVE_REG(14)
SAVE_REG(15)
SAVE_REG(16)
SAVE_REG(17)
SAVE_REG(18)
SAVE_REG(19)
SAVE_REG(20)
SAVE_REG(21)
SAVE_REG(22)
SAVE_REG(23)
SAVE_REG(24)
SAVE_REG(25)
SAVE_REG(26)
SAVE_REG(27)
SAVE_REG(28)
SAVE_REG(29)
SAVE_REG(30)
SAVE_REG(31)
/* Write zero to all CVMSEG locations per Core-15169 */
dli a0, CVMSEG_SIZE - (33 * 8)
1: sd zero, CVMSEG_BASE(a0)
daddiu a0, a0, -8
bgez a0, 1b
nop
/* Set the stack to begin right below the registers */
dli sp, CVMSEG_BASE + CVMSEG_SIZE - (32 * 8)
/* Load the address of the third stage handler */
dla $25, octeon_wdt_nmi_stage3
/* Call the third stage handler */
jal $25
/* a0 is the address of the saved registers */
move a0, sp
/* Loop forvever if we get here. */
2: b 2b
nop
.set pop
END(octeon_wdt_nmi_stage2)