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The RENESAS FemtoClock3 Wireless is a high-performance jitter attenuator, frequency translator, and clock synthesizer. The device is comprised of 3 digital PLLs (DPLL) to track CLKIN inputs and three independent low phase noise fractional output dividers (FOD) that output low phase noise clocks. FemtoClock3 supports one Time Synchronization (Time Sync) channel to enable an external processor to control the phase and frequency of the Time Sync channel and to take phase measurements using the TDC. Intended applications are synchronization using the precision time protocol (PTP) and synchronization with 0.5 Hz and 1 Hz signals from GNSS. Signed-off-by: Min Li <min.li.xe@renesas.com> Acked-by: Lee Jones <lee@kernel.org> Signed-off-by: David S. Miller <davem@davemloft.net>
46 lines
1022 B
C
46 lines
1022 B
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* PTP hardware clock driver for the FemtoClock3 family of timing and
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* synchronization devices.
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*
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* Copyright (C) 2023 Integrated Device Technology, Inc., a Renesas Company.
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*/
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#ifndef PTP_IDTFC3_H
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#define PTP_IDTFC3_H
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#include <linux/ktime.h>
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#include <linux/ptp_clock.h>
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#include <linux/regmap.h>
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#define FW_FILENAME "idtfc3.bin"
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#define MAX_FFO_PPB (244000)
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#define TDC_GET_PERIOD (10)
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struct idtfc3 {
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struct ptp_clock_info caps;
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struct ptp_clock *ptp_clock;
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struct device *dev;
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/* Mutex to protect operations from being interrupted */
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struct mutex *lock;
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struct device *mfd;
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struct regmap *regmap;
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struct idtfc3_hw_param hw_param;
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u32 sub_sync_count;
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u32 ns_per_sync;
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int tdc_offset_sign;
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u64 tdc_apll_freq;
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u32 time_ref_freq;
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u16 fod_n;
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u8 lpf_mode;
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/* Time counter */
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u32 last_counter;
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s64 ns;
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u32 ns_per_counter;
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u32 tc_update_period;
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u32 tc_write_timeout;
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s64 tod_write_overhead;
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};
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#endif /* PTP_IDTFC3_H */
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