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8d786149d7
Add support for Xilinx XDMA Soft IP core as Root Port. The Zynq UltraScale+ MPSoCs devices support XDMA soft IP module in programmable logic. The integrated XDMA Soft IP block has integrated bridge function that can act as PCIe Root Port. [kwilczynski: correct indentation and whitespaces, Kconfig help update] Link: https://lore.kernel.org/linux-pci/20231003173453.938190-4-thippeswamy.havalige@amd.com Signed-off-by: Thippeswamy Havalige <thippeswamy.havalige@amd.com> Signed-off-by: Bharat Kumar Gogada <bharat.kumar.gogada@amd.com> Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
32 lines
1.0 KiB
C
32 lines
1.0 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* (C) Copyright 2023, Xilinx, Inc.
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*/
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#include <linux/pci.h>
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#include <linux/pci-ecam.h>
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#include <linux/platform_device.h>
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/* Interrupt registers definitions */
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#define XILINX_PCIE_INTR_LINK_DOWN 0
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#define XILINX_PCIE_INTR_HOT_RESET 3
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#define XILINX_PCIE_INTR_CFG_PCIE_TIMEOUT 4
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#define XILINX_PCIE_INTR_CFG_TIMEOUT 8
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#define XILINX_PCIE_INTR_CORRECTABLE 9
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#define XILINX_PCIE_INTR_NONFATAL 10
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#define XILINX_PCIE_INTR_FATAL 11
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#define XILINX_PCIE_INTR_CFG_ERR_POISON 12
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#define XILINX_PCIE_INTR_PME_TO_ACK_RCVD 15
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#define XILINX_PCIE_INTR_INTX 16
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#define XILINX_PCIE_INTR_PM_PME_RCVD 17
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#define XILINX_PCIE_INTR_MSI 17
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#define XILINX_PCIE_INTR_SLV_UNSUPP 20
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#define XILINX_PCIE_INTR_SLV_UNEXP 21
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#define XILINX_PCIE_INTR_SLV_COMPL 22
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#define XILINX_PCIE_INTR_SLV_ERRP 23
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#define XILINX_PCIE_INTR_SLV_CMPABT 24
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#define XILINX_PCIE_INTR_SLV_ILLBUR 25
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#define XILINX_PCIE_INTR_MST_DECERR 26
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#define XILINX_PCIE_INTR_MST_SLVERR 27
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#define XILINX_PCIE_INTR_SLV_PCIE_TIMEOUT 28
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