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Synopsys DesignWare XPCS IP-core can be synthesized with the device CSRs being accessible over the MCI or APB3 interface instead of the MDIO bus (see the CSR_INTERFACE HDL parameter). Thus all the PCS registers can be just memory mapped and be a subject of the standard MMIO operations of course taking into account the peculiarities of the Clause C45 CSRs mapping. From that perspective the DW XPCS devices would look as just normal platform devices for the kernel. On the other hand in order to have the DW XPCS devices handled by the pcs-xpcs.c driver they need to be registered in the framework of the MDIO-subsystem. So the suggested change is about providing a DW XPCS platform device driver registering a virtual MDIO-bus with a single MDIO-device representing the DW XPCS device. DW XPCS platform device is supposed to be described by the respective compatible string "snps,dw-xpcs" (or with the PMA-specific compatible string), CSRs memory space and optional peripheral bus and reference clock sources. Depending on the INDIRECT_ACCESS IP-core synthesize parameter the memory-mapped reg-space can be represented as either directly or indirectly mapped Clause 45 space. In the former case the particular address is determined based on the MMD device and the registers offset (5 + 16 bits all together) within the device reg-space. In the later case there is only 8 lower address bits are utilized for the registers mapping (255 CSRs). The upper bits are supposed to be written into the respective viewport CSR in order to select the respective MMD sub-page. Note, only the peripheral bus clock source is requested in the platform device probe procedure. The core and pad clocks handling has been implemented in the framework of the xpcs_create() method intentionally since the clocks-related setups are supposed to be performed later, during the DW XPCS main configuration procedures. (For instance they will be required for the DW Gen5 10G PMA configuration.) Signed-off-by: Serge Semin <fancer.lancer@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
134 lines
4.5 KiB
C
134 lines
4.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2020 Synopsys, Inc. and/or its affiliates.
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* Synopsys DesignWare XPCS helpers
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*
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* Author: Jose Abreu <Jose.Abreu@synopsys.com>
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*/
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#include <linux/bits.h>
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#include <linux/pcs/pcs-xpcs.h>
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/* Vendor regs access */
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#define DW_VENDOR BIT(15)
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/* VR_XS_PCS */
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#define DW_USXGMII_RST BIT(10)
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#define DW_USXGMII_EN BIT(9)
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#define DW_VR_XS_PCS_DIG_CTRL1 0x0000
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#define DW_VR_RST BIT(15)
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#define DW_EN_VSMMD1 BIT(13)
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#define DW_CL37_BP BIT(12)
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#define DW_VR_XS_PCS_DIG_STS 0x0010
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#define DW_RXFIFO_ERR GENMASK(6, 5)
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#define DW_PSEQ_ST GENMASK(4, 2)
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#define DW_PSEQ_ST_GOOD FIELD_PREP(GENMASK(4, 2), 0x4)
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/* SR_MII */
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#define DW_USXGMII_FULL BIT(8)
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#define DW_USXGMII_SS_MASK (BIT(13) | BIT(6) | BIT(5))
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#define DW_USXGMII_10000 (BIT(13) | BIT(6))
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#define DW_USXGMII_5000 (BIT(13) | BIT(5))
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#define DW_USXGMII_2500 (BIT(5))
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#define DW_USXGMII_1000 (BIT(6))
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#define DW_USXGMII_100 (BIT(13))
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#define DW_USXGMII_10 (0)
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/* SR_AN */
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#define DW_SR_AN_ADV1 0x10
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#define DW_SR_AN_ADV2 0x11
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#define DW_SR_AN_ADV3 0x12
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/* Clause 73 Defines */
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/* AN_LP_ABL1 */
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#define DW_C73_PAUSE BIT(10)
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#define DW_C73_ASYM_PAUSE BIT(11)
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#define DW_C73_AN_ADV_SF 0x1
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/* AN_LP_ABL2 */
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#define DW_C73_1000KX BIT(5)
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#define DW_C73_10000KX4 BIT(6)
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#define DW_C73_10000KR BIT(7)
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/* AN_LP_ABL3 */
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#define DW_C73_2500KX BIT(0)
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#define DW_C73_5000KR BIT(1)
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/* Clause 37 Defines */
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/* VR MII MMD registers offsets */
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#define DW_VR_MII_MMD_CTRL 0x0000
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#define DW_VR_MII_MMD_STS 0x0001
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#define DW_VR_MII_MMD_STS_LINK_STS BIT(2)
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#define DW_VR_MII_DIG_CTRL1 0x8000
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#define DW_VR_MII_AN_CTRL 0x8001
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#define DW_VR_MII_AN_INTR_STS 0x8002
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/* Enable 2.5G Mode */
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#define DW_VR_MII_DIG_CTRL1_2G5_EN BIT(2)
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/* EEE Mode Control Register */
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#define DW_VR_MII_EEE_MCTRL0 0x8006
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#define DW_VR_MII_EEE_MCTRL1 0x800b
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#define DW_VR_MII_DIG_CTRL2 0x80e1
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/* VR_MII_DIG_CTRL1 */
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#define DW_VR_MII_DIG_CTRL1_MAC_AUTO_SW BIT(9)
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#define DW_VR_MII_DIG_CTRL1_PHY_MODE_CTRL BIT(0)
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/* VR_MII_DIG_CTRL2 */
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#define DW_VR_MII_DIG_CTRL2_TX_POL_INV BIT(4)
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#define DW_VR_MII_DIG_CTRL2_RX_POL_INV BIT(0)
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/* VR_MII_AN_CTRL */
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#define DW_VR_MII_AN_CTRL_8BIT BIT(8)
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#define DW_VR_MII_AN_CTRL_TX_CONFIG_SHIFT 3
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#define DW_VR_MII_TX_CONFIG_MASK BIT(3)
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#define DW_VR_MII_TX_CONFIG_PHY_SIDE_SGMII 0x1
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#define DW_VR_MII_TX_CONFIG_MAC_SIDE_SGMII 0x0
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#define DW_VR_MII_AN_CTRL_PCS_MODE_SHIFT 1
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#define DW_VR_MII_PCS_MODE_MASK GENMASK(2, 1)
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#define DW_VR_MII_PCS_MODE_C37_1000BASEX 0x0
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#define DW_VR_MII_PCS_MODE_C37_SGMII 0x2
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#define DW_VR_MII_AN_INTR_EN BIT(0)
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/* VR_MII_AN_INTR_STS */
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#define DW_VR_MII_AN_STS_C37_ANCMPLT_INTR BIT(0)
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#define DW_VR_MII_AN_STS_C37_ANSGM_FD BIT(1)
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#define DW_VR_MII_AN_STS_C37_ANSGM_SP_SHIFT 2
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#define DW_VR_MII_AN_STS_C37_ANSGM_SP GENMASK(3, 2)
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#define DW_VR_MII_C37_ANSGM_SP_10 0x0
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#define DW_VR_MII_C37_ANSGM_SP_100 0x1
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#define DW_VR_MII_C37_ANSGM_SP_1000 0x2
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#define DW_VR_MII_C37_ANSGM_SP_LNKSTS BIT(4)
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/* SR MII MMD Control defines */
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#define AN_CL37_EN BIT(12) /* Enable Clause 37 auto-nego */
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#define SGMII_SPEED_SS13 BIT(13) /* SGMII speed along with SS6 */
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#define SGMII_SPEED_SS6 BIT(6) /* SGMII speed along with SS13 */
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/* SR MII MMD AN Advertisement defines */
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#define DW_HALF_DUPLEX BIT(6)
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#define DW_FULL_DUPLEX BIT(5)
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/* VR MII EEE Control 0 defines */
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#define DW_VR_MII_EEE_LTX_EN BIT(0) /* LPI Tx Enable */
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#define DW_VR_MII_EEE_LRX_EN BIT(1) /* LPI Rx Enable */
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#define DW_VR_MII_EEE_TX_QUIET_EN BIT(2) /* Tx Quiet Enable */
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#define DW_VR_MII_EEE_RX_QUIET_EN BIT(3) /* Rx Quiet Enable */
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#define DW_VR_MII_EEE_TX_EN_CTRL BIT(4) /* Tx Control Enable */
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#define DW_VR_MII_EEE_RX_EN_CTRL BIT(7) /* Rx Control Enable */
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#define DW_VR_MII_EEE_MULT_FACT_100NS_SHIFT 8
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#define DW_VR_MII_EEE_MULT_FACT_100NS GENMASK(11, 8)
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/* VR MII EEE Control 1 defines */
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#define DW_VR_MII_EEE_TRN_LPI BIT(0) /* Transparent Mode Enable */
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#define DW_XPCS_INFO_DECLARE(_name, _pcs, _pma) \
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static const struct dw_xpcs_info _name = { .pcs = _pcs, .pma = _pma }
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int xpcs_read(struct dw_xpcs *xpcs, int dev, u32 reg);
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int xpcs_write(struct dw_xpcs *xpcs, int dev, u32 reg, u16 val);
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int xpcs_read_vpcs(struct dw_xpcs *xpcs, int reg);
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int xpcs_write_vpcs(struct dw_xpcs *xpcs, int reg, u16 val);
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int nxp_sja1105_sgmii_pma_config(struct dw_xpcs *xpcs);
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int nxp_sja1110_sgmii_pma_config(struct dw_xpcs *xpcs);
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int nxp_sja1110_2500basex_pma_config(struct dw_xpcs *xpcs);
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int txgbe_xpcs_switch_mode(struct dw_xpcs *xpcs, phy_interface_t interface);
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