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Author SHA1 Message Date
Shubham Gaur
e76f79cbe6
Merge 0401bbf56d into baeb9a7d8b 2024-09-20 09:44:56 +05:30
Linus Torvalds
baeb9a7d8b Enable PREEMPT_RT on supported architectures:
After twenty years of development we finally reached the point to enable
   PREEMPT_RT support in the mainline kernel.
 
   All prerequisites are merged, so enable it on the supported architectures
   ARM64, RISCV and X86(32/64-bit).
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Merge tag 'sched-rt-2024-09-17' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip

Pull RT enablement from Thomas Gleixner:
 "Enable PREEMPT_RT on supported architectures:

  After twenty years of development we finally reached the point to
  enable PREEMPT_RT support in the mainline kernel.

  All prerequisites are merged, so enable it on the supported
  architectures ARM64, RISCV and X86(32/64-bit)"

* tag 'sched-rt-2024-09-17' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  riscv: Allow to enable PREEMPT_RT.
  arm64: Allow to enable PREEMPT_RT.
  x86: Allow to enable PREEMPT_RT.
2024-09-20 06:04:27 +02:00
Shubham Gaur
0401bbf56d
Merge branch 'torvalds:master' into master 2024-09-19 14:05:40 +05:30
Shubham Gaur
f1bc834141
Update reboot.c 2024-09-18 16:48:43 +05:30
Sebastian Andrzej Siewior
2638e4e6b1 riscv: Allow to enable PREEMPT_RT.
It is really time.

riscv has all the required architecture related changes, that have been
identified over time, in order to enable PREEMPT_RT. With the recent
printk changes, the last known road block has been addressed.

Allow to enable PREEMPT_RT on riscv.

Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Tested-by: Nam Cao <namcao@linutronix.de> # Visionfive 2
Link: https://lore.kernel.org/all/20240906111841.562402-4-bigeasy@linutronix.de
2024-09-17 11:06:08 +02:00
Sebastian Andrzej Siewior
d8fccd9ca5 arm64: Allow to enable PREEMPT_RT.
It is really time.

arm64 has all the required architecture related changes, that have been
identified over time, in order to enable PREEMPT_RT. With the recent
printk changes, the last known road block has been addressed.

Allow to enable PREEMPT_RT on arm64.

Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Acked-by: Will Deacon <will@kernel.org>
Link: https://lore.kernel.org/all/20240906111841.562402-3-bigeasy@linutronix.de
2024-09-17 11:06:02 +02:00
Sebastian Andrzej Siewior
d2d6422f8b x86: Allow to enable PREEMPT_RT.
It is really time.

x86 has all the required architecture related changes, that have been
identified over time, in order to enable PREEMPT_RT. With the recent
printk changes, the last known road block has been addressed.

Allow to enable PREEMPT_RT on x86.

Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Link: https://lore.kernel.org/all/20240906111841.562402-2-bigeasy@linutronix.de
2024-09-17 11:05:53 +02:00
Shubham Gaur
5049ddba25
reboot.c : changed reboot_default
Made two changes:
1. ARM64 now defaults to hard reboot on kernel panic.
2. reboot_default` flag is now a boolean for better clarity.
2024-08-30 11:27:39 +05:30
4 changed files with 14 additions and 7 deletions

View File

@ -101,6 +101,7 @@ config ARM64
select ARCH_SUPPORTS_NUMA_BALANCING
select ARCH_SUPPORTS_PAGE_TABLE_CHECK
select ARCH_SUPPORTS_PER_VMA_LOCK
select ARCH_SUPPORTS_RT
select ARCH_WANT_BATCHED_UNMAP_TLB_FLUSH
select ARCH_WANT_COMPAT_IPC_PARSE_VERSION if COMPAT
select ARCH_WANT_DEFAULT_BPF_JIT

View File

@ -65,6 +65,7 @@ config RISCV
select ARCH_SUPPORTS_LTO_CLANG_THIN if LLD_VERSION >= 140000
select ARCH_SUPPORTS_PAGE_TABLE_CHECK if MMU
select ARCH_SUPPORTS_PER_VMA_LOCK if MMU
select ARCH_SUPPORTS_RT
select ARCH_SUPPORTS_SHADOW_CALL_STACK if HAVE_SHADOW_CALL_STACK
select ARCH_USE_CMPXCHG_LOCKREF if 64BIT
select ARCH_USE_MEMTEST

View File

@ -124,6 +124,7 @@ config X86
select ARCH_USES_CFI_TRAPS if X86_64 && CFI_CLANG
select ARCH_SUPPORTS_LTO_CLANG
select ARCH_SUPPORTS_LTO_CLANG_THIN
select ARCH_SUPPORTS_RT
select ARCH_USE_BUILTIN_BSWAP
select ARCH_USE_CMPXCHG_LOCKREF if X86_CMPXCHG64
select ARCH_USE_MEMTEST

View File

@ -34,7 +34,11 @@ EXPORT_SYMBOL(cad_pid);
#endif
enum reboot_mode reboot_mode DEFAULT_REBOOT_MODE;
EXPORT_SYMBOL_GPL(reboot_mode);
#if defined(CONFIG_ARM64)
enum reboot_mode panic_reboot_mode = REBOOT_HARD;
#else
enum reboot_mode panic_reboot_mode = REBOOT_UNDEFINED;
#endif
/*
* This variable is used privately to keep track of whether or not
@ -43,7 +47,7 @@ enum reboot_mode panic_reboot_mode = REBOOT_UNDEFINED;
* suppress DMI scanning for reboot quirks. Without it, it's
* impossible to override a faulty reboot quirk without recompiling.
*/
int reboot_default = 1;
bool reboot_default = true;
int reboot_cpu;
enum reboot_type reboot_type = BOOT_ACPI;
int reboot_force;
@ -1016,10 +1020,10 @@ static int __init reboot_setup(char *str)
/*
* Having anything passed on the command line via
* reboot= will cause us to disable DMI checking
* reboot= will cause us to skip DMI checking
* below.
*/
reboot_default = 0;
reboot_default = false;
if (!strncmp(str, "panic_", 6)) {
mode = &panic_reboot_mode;
@ -1151,7 +1155,7 @@ static ssize_t mode_store(struct kobject *kobj, struct kobj_attribute *attr,
else
return -EINVAL;
reboot_default = 0;
reboot_default = false;
return count;
}
@ -1173,7 +1177,7 @@ static ssize_t force_store(struct kobject *kobj, struct kobj_attribute *attr,
if (kstrtobool(buf, &res))
return -EINVAL;
reboot_default = 0;
reboot_default = false;
reboot_force = res;
return count;
@ -1230,7 +1234,7 @@ static ssize_t type_store(struct kobject *kobj, struct kobj_attribute *attr,
else
return -EINVAL;
reboot_default = 0;
reboot_default = false;
return count;
}
@ -1259,7 +1263,7 @@ static ssize_t cpu_store(struct kobject *kobj, struct kobj_attribute *attr,
if (cpunum >= num_possible_cpus())
return -ERANGE;
reboot_default = 0;
reboot_default = false;
reboot_cpu = cpunum;
return count;