Track current nominal voltage as part of struct voltagedomain instead
of omap_vdd_info, which will soon be removed.
Also renames field from curr_volt to nominal_volt.
No functional changes.
Signed-off-by: Kevin Hilman <khilman@ti.com>
Rename voltage scaling related functions to use voltdm_ prefix intead
of omap_voltage_, and cleanup kerneldoc comments in the process.
s/omap_voltage_scale_vdd/voltdm_scale/
s/omap_voltage_reset/voltdm_reset/
Also, in voltdm_reset() s/target_uvdc/target_volt/ to be consistent with
naming throughout the file.
No functional changes.
Signed-off-by: Kevin Hilman <khilman@ti.com>
combine VPCONFIG init voltage setup into common function and use from
both vp_enable and from vp_forceupdate_scale().
NOTE: this patch changes the sequence of when the initVDD bit is
cleared. The bit is now cleared immediately after it was written.
Since only the rising edge of this bit has any affect according to the
TRM, the exact timing of clearing of this bit should not have any
effect.
Signed-off-by: Kevin Hilman <khilman@ti.com>
Reading the VPVOLTAGE field of PRM_VP_*_VOLTAGE registers currently
relies on a u32 -> u8 conversion to mask off the FORCEUPDATEWAIT field
in the upper bits. Make this explicit using the mask symbol
already defined, added as a new field in struct omap_vp_common.
Signed-off-by: Todd Poynor <toddpoynor@google.com>
Signed-off-by: Kevin Hilman <khilman@ti.com>
Function pointer used for actual voltage scaling (e.g. VP force update
or VC bypass) is moved from omap_vdd_info into struct voltagedomain,
resulting in renames s/vdd->volt_scale/voltdm->scale/
No functional changes.
Signed-off-by: Kevin Hilman <khilman@ti.com>
Remove the "runtime" VP data in favor of direct programming of VP registers.
The VP is in the PRM, which is in the wakeup powerdomain, so there is no
need to keep the state dynamically.
Fixes to original version from Nishanth Menon <nm@ti.com>
Signed-off-by: Kevin Hilman <khilman@ti.com>
Create new helper function in VP layer for updating VP error gain.
Currently used during pre-scale for VP force update and VC bypass.
TODO: determine if this can be removed from the pre-scale path and
moved to VP enable path.
Signed-off-by: Kevin Hilman <khilman@ti.com>
Add sys clock name and rate to struct voltage domain. SoC specific
voltagedomain init code initializes sys clock name. After clock
framework is initialized, voltage late init will then use use the
sys_clk rate to calculate the various timing that depend on that rate.
Signed-off-by: Kevin Hilman <khilman@ti.com>
In struct omap_vp_common, the shift value can be derived from the mask
value by using __ffs(), so remove the shift value for the various
VPCONFIG bitfields, and use __ffs() in the code for the shift value.
While here, rename field names in kerneldoc comment to match actual
field names in structure. Also, cleanup indendentaion for other VP
register accesses in omap_vp_init().
No functional changes.
Signed-off-by: Kevin Hilman <khilman@ti.com>
Remove read-only debugfs interface to VP values. Most of the values
are init-time only and never change. Current voltage value should be
retreived from the (eventual) regulator framework interface to the
voltage domain.
Fixes to original version provided by Nishanth Menon <nm@ti.com>
Signed-off-by: Kevin Hilman <khilman@ti.com>
- move VP instance struct from vdd_info into struct voltage domain
- remove _data suffix from structure name
- rename vp_ prefix from vp_common field: accesses are now vp->common
- move vp_enabled bool from vdd_info into VP instance
- remove remaining references to omap_vdd_info
No functional changes.
Signed-off-by: Kevin Hilman <khilman@ti.com>
Instead of reading current vsel value from the VP's voltage register,
just use current nominal voltage translated into vsel via the PMIC.
Doing this allows VC bypass scaling to work even without a VP configured.
Signed-off-by: Kevin Hilman <khilman@ti.com>
On OMAP3+, all VC channels have the the same bitfield ordering for all
VC channels, except the OMAP4 MPU channel. This appears to be a freak
accident as all other VC channel (including OMAP5) have the standard
configuration. Handle the mutant case by adding a per-channel flag
to signal the deformity and handle it during VC init.
Special thanks to Nishanth Menon <nm@ti.com> for finding this problem
and for proposing the initial solution.
Cc: Nishanth Menon <nm@ti.com>
Signed-off-by: Kevin Hilman <khilman@ti.com>
Remove hard-coded I2C configuration in favor of settings that can be
configured from PMIC-specific values. Currently only high-speed mode
and the master-code value are supported, since they were the only
fields currently used, but extending this is now trivial.
Thanks to Nishanth Menon <nm@ti.com> for reporting/fixing a sparse
problem and making omap_vc_i2c_init() static, as well as finding and
fixing a problem with the shift/mask of mcode.
Signed-off-by: Kevin Hilman <khilman@ti.com>
Move structure containing PMIC configurable settings into struct
voltagedomain. In the process, rename from omap_volt_pmic_info to
omap_voltdm_pmic (_info suffix is not helpful.)
No functional changes.
Signed-off-by: Kevin Hilman <khilman@ti.com>
VC channel configuration is programmed based on settings coming from
the PMIC configuration.
Currently, the VC channel to PMIC mapping is a simple one-to-one
mapping. Whenever a VC channel parameter is configured (i2c slave
addres, PMIC register address, on/ret/off command), the corresponding
bits are enabled in the VC channel configuration register.
If necessary, the programmability of channel configuration settings
could be extended to board/PMIC files, however, because this patch
changes the channel configuration to be programmed based on existing
values from the PMIC settings, it may not be required.
Also note that starting with OMAP4, where there are more than 2
channels, one channel is identified as the "default" channel. When
any of the bits in the channel config for the other channels are zero,
it means to use the default channel. The OMAP4 TRM (at least through
NDA version Q) is wrong in describing which is the default channel.
The default channel on OMAP4 is MPU, not CORE as decribed in the TRM.
Signed-off-by: Kevin Hilman <khilman@ti.com>
Configuring the on/onlp/ret/off command values is common to OMAP3 & 4.
Move from OMAP3-only init into common VC init.
Signed-off-by: Kevin Hilman <khilman@ti.com>
- add setup_time field to struct omap_vc_channel (init'd from PMIC data)
- use VC/VP register access helper for read/modify/write
- move VFSM structure from omap_vdd_info into struct voltagedomain
- remove redunant _data suffix from VFSM structures and variables
- remove voltsetup_shift, use ffs() on the mask value to find the shift
Signed-off-by: Kevin Hilman <khilman@ti.com>
The PMIC configurable variables should be isolated to VC initialization.
The rest of the VC functions (like VC bypass) should use the i2c slave address
and voltage register address fields from struct omap_vc_channel.
Signed-off-by: Kevin Hilman <khilman@ti.com>
- support both voltage register address and command register address
for each VC channel
- add fields for voltage register address (volra) and command register
address (cmdra) to struct omap_vc_channel
- use VC/VP register access read/modify/write helper
- remove volra_shift field (use __ffs(mask) for shift value)
- I2C addresses 10-bit, change size to u16
Signed-off-by: Kevin Hilman <khilman@ti.com>
- Add an i2c_slave_address field to the omap_vc_channel
- use VC/VP read/modify/write helper instead of open-coding
- remove smps_sa_shift, use __ffs(mask) for shift value
- I2C addresses 10-bit, change size to u16
Special thanks to Shweta Gulati <shweta.gulati@ti.com> for suggesting
the use of __ffs(x) instead of ffs(x) - 1.
Signed-off-by: Kevin Hilman <khilman@ti.com>
Convert VC/VP register access to use PRM VC/VP accessor functions. In
the process, move the read/write function pointers from vdd_info into
struct voltagedomain.
No functional changes.
Additional cleanup:
- remove prm_mod field from VC/VP data structures, the PRM register
access functions know which PRM module to use.
Signed-off-by: Kevin Hilman <khilman@ti.com>
On OMAP3+, the voltage controller (VC) and voltage processor (VP) are
inside the PRM. Add some PRM helper functions for register access to
these module registers.
Thanks to Nishanth Menon for finding/fixing a sparse problem.
Cc: Nishanth Menon <nm@ti.com>
Signed-off-by: Kevin Hilman <khilman@ti.com>
Replace the VP tranxdone check/clear with helper functions from the
PRM layer.
In the process, remove prm_irqst_* voltage structure fields for IRQ
status checking which are no longer needed.
Since these reads/writes of the IRQ status bits were the only PRM
accesses that were not to VC/VP registers, this allows the rest of the
register accesses in the VC/VP code to use VC/VP specific register
access functions (done in the following patch.)
Signed-off-by: Kevin Hilman <khilman@ti.com>
Add SoC specific PRM VP helper functions for checking and clearing
the VP transaction done status.
Longer term, these events should be handled by the forthcoming PRCM
interrupt handler.
Signed-off-by: Kevin Hilman <khilman@ti.com>
The VC layer can support PMICs with separate voltage and command
registers by putting the different registers in the PRM_VC_SMPS_VOL_RA
and PRCM_VC_SMPS_CMD_RA registers respectively.
The PMIC data must supply at least a voltage register address
(volt_reg_addr). The command register address (cmd_reg_addr) is
optional. If the PMIC data does not supply a separate command
register address, the VC will use the voltage register address for both.
Signed-off-by: Kevin Hilman <khilman@ti.com>
This patch is primarily a move of VP specific code from voltage.c into
its own code in vp.c and adds prototypes to vp.h
No functional changes, except debugfs...
VP debugfs moved to 'vp' subdir of <debugfs>/voltage/ and 'vp_'
prefixes removed from all debugfs filenames.
Signed-off-by: Kevin Hilman <khilman@ti.com>
VC is initialized first, set default scaling method to VC bypass.
If/when VP is initialized, default scaling method will be changed to
VP force-update.
Enabling VC bypass as default as soon as VC is initialized allows for
VC bypass scaling to work when no VP is configured/initialized for a
given voltage domain.
Signed-off-by: Kevin Hilman <khilman@ti.com>
Move the VC instance struct from omap_vdd_info into struct voltagedomain.
While moving, perform some misc. renames for readability.
No functional changes.
Summary of renames:
- rename omap_vc_instance to omap_vc_channel, since there is only
one instance of the VC IP and this actually represents channels
using TRM terminology.
- rename 'vc_common' field of VC channel which led to:
s/vc->vc_common/vc->common/
- remove redundant '_data' suffix
- OMAP3: vc1 --> vc_mpu, vc2 --> vc_core
- omap_vc_bypass_scale_voltage() -> omap_vc_bypass_scale()
Signed-off-by: Kevin Hilman <khilman@ti.com>
merge
As part of the voltage layer cleanup, split out VC specific code into
a dedicated VC layer. This patch primarily just moves VC code from
voltage.c into vc.c, and adds prototypes to vc.h.
No functional changes.
For readability, each function was given a local 'vc' pointer:
struct omap_vc_instance_data *vc = voltdm->vdd->vc_data;
and a global replace of s/vdd->vc_data/vc/ was done.
Also vc_init was renamed to vc_init_channel to reflect that this is
per-VC channel initializtion.
Signed-off-by: Kevin Hilman <khilman@ti.com>
When a powerdomain is registered and it has an associated voltage domain,
add the powerdomain to the voltagedomain using voltdm_add_pwrdm().
Also add voltagedomain iterator helper functions to iterate over all
registered voltagedomains and all powerdomains associated with a
voltagedomain.
Modeled after a similar relationship between clockdomains and powerdomains.
Signed-off-by: Kevin Hilman <khilman@ti.com>
When a powerdomain is registered, lookup the voltage domain by name
and keep a pointer to the containing voltagedomain in the powerdomain
structure.
Modeled after similar method between powerdomain and clockdomain layers.
Signed-off-by: Kevin Hilman <khilman@ti.com>
Add voltage domain name to indicate which voltagedomain each
powerdomain is in.
The fixed voltage domain like ldo_wakeup for emu and wkup power
domain is added too.
Signed-off-by: Benoit Cousson <b-cousson@ti.com>
Cc: Paul Walmsley <paul@pwsan.com>
[khilman@ti.com]: renamed wakeup domain: s/ldo_wakeup/wakeup/
Signed-off-by: Kevin Hilman <khilman@ti.com>
Create basic voltagedomains for OMAP2 and associate OMAP2 powerdomains
with the newly created voltage domains.
While here, update copyright on powerdomain data to 2011.
Signed-off-by: Kevin Hilman <khilman@ti.com>
Each powerdomain is associated with a voltage domain. Add an entry to
struct powerdomain where the enclosing voltagedomain can be
referenced.
Modeled after similar relationship between clockdomains and powerdomains.
Signed-off-by: Kevin Hilman <khilman@ti.com>
Add a 'bool scalable' flag to the struct powerdomain and set it for
the scalable domains on OMAP3 and OMAP4.
Signed-off-by: Kevin Hilman <khilman@ti.com>
Add wakeup voltage domain so that the wakeup powerdomain can have an
associated powerdomain. Note that the scalable flat is not set for
the this voltagedomain, so it will not be fully initialized like
scalable voltage domains.
Signed-off-by: Kevin Hilman <khilman@ti.com>
This voltage domain (a.k.a. VDD1) contains both the MPU and the IVA, so
rename appropriately.
Also fixup any users of the "mpu" name to use "mpu_iva"
Signed-off-by: Kevin Hilman <khilman@ti.com>
Start cleaning up the voltage layer to have a voltage domain layer
that resembles the structure of the existing clock and power domain
layers. To that end:
- move the 'struct voltagedomain' out of 'struct omap_vdd_info' to
become the primary data structure.
- convert any functions taking a pointer to struct omap_vdd_info into
functions taking a struct voltagedomain pointer.
- convert the register & initialize of voltage domains to look like
that of powerdomains
- convert omap_voltage_domain_lookup() to voltdm_lookup(), modeled
after the current powerdomain and clockdomain lookup functions.
- omap_voltage_late_init(): only configure VDD info when
the vdd_info struct is non-NULL
Signed-off-by: Kevin Hilman <khilman@ti.com>
Eliminate need for global variables for the various PRM module offsets by
making them part of the VP/VC common structures
Eventually, these will likely be moved again, or more likely removed
when VP/VC code is isolated, but for now just getting rid of them as
global variabes so that the voltage domain initialization can be
cleaned up.
Signed-off-by: Kevin Hilman <khilman@ti.com>
The voltage domain pointer currently in struct omap_hwmod is not used
and does not belong here. Instead, voltage domains will be associated
with powerdomains in forthcoming patches.
Acked-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Kevin Hilman <khilman@ti.com>
The keypad controller requires a external pull-up for all the keypad
row lines. Fix the incorrect pad configuration for keypad controller
row lines by enabling the pad pull-up for the all row lines of the
keypad controller.
Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
clkdev framework uses global mutex to protect clock tree, so it is not
possible to call clk_get() in interrupt context. This patch fixes this
issue and makes system reset by watchdog call working again.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
According to commit 96d78686d4("ARM: S3C64XX: Add PWM backlight
support on SMDK6410") and commit f00207b255("ARM: SAMSUNG: Create
a common infrastructure for PWM backlight support"), this should
not be used anymore.
And this patch fixes follwing warning:
arch/arm/mach-s3c64xx/mach-smdk6410.c:296: warning: 'smdk6410_backlight_device' defined but not used
Signed-off-by: Banajit Goswami <banajit.g@samsung.com>
[kgene.kim@samsung.com: modified commit message]
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
System resume can't be completed because mct-frc isn't restarted
after system suspends. This patch restarts mct-frc during system
resume.
Reported-by: Jongpill Lee <boyko.lee@samsung.com>
Signed-off-by: Changhwan Youn <chaos.youn@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
The commit 5dfc54e087
("ARM: GIC: avoid routing interrupts to offline CPUs")
prevents routing interrupts to offline CPUs. But in
case of timer on EXYNOS4, the irq_set_affinity() method
is called in percpu_timer_setup() before CPU1 becomes
online. So this patch fixes routing timer interrupt to
offline CPU.
Reported-by: Changhwan Youn <chaos.youn@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
According to commmit af90f10d ("ARM: 6759/1: smp: Select
local timers vs broadcast timer support"), the return type
of local_timer_setup() should be int instead of void.
Reported-by: Changhwan Youn <chaos.youn@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
The PLL4650C is used for VPLL on EXYNOS4 so should be fixed.
Signed-off-by: Jonghwan Choi <jhbird.choi@samsung.com>
[kgene.kim@samsung.com: added message]
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Now that all of the users of the OMAP_CHIP bitfield code have been converted
to use lists, the OMAP_CHIP code, data, and declarations can be removed.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
At Tony's request, remove the OMAP_CHIP* flags from the hwmod data, and
replace it instead with chip family, variant, and ES level-specific lists
of hwmods to register.
Thanks to Gražvydas Ignotas <notasas@gmail.com> for finding a bug in the
AM3517/3505 support, and for other review comments.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Gražvydas Ignotas <notasas@gmail.com>
At Tony's request, remove the omap_chip bitmasks from the powerdomain
definitions. Instead, initialize powerdomains based on one or more
lists that are applicable to a particular SoC family, variant, and
silicon revision.
Gražvydas Ignotas <notasas@gmail.com> found and reported a bug in a
related patch that also applied to this patch - thanks Gražvydas.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Gražvydas Ignotas <notasas@gmail.com>
In preparation for OMAP_CHIP() removal, split pwrdm_init() into three
functions. This allows some of them to be called multiple times: for
example, pwrdm_register_pwrdms() can be called once to register
powerdomains that are common to a group of SoCs, and once to register
powerdomains that are specific to a single SoC.
The appropriate order to call these functions - which is enforced
by the code - is:
1. pwrdm_register_platform_funcs()
2. pwrdm_register_pwrdms() (can be called multiple times)
3. pwrdm_complete_init()
Convert the OMAP2, 3, and 4 powerdomain init code to use these new
functions.
While here, improve documentation, and increase CodingStyle
conformance by shortening some local variable names.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
At Tony's request, remove the omap_chip bitmasks from the clockdomain
and clockdomain dependency definitions. Instead, initialize
clockdomains based on one or more lists that are applicable to a
particular SoC family, variant, and silicon revision.
Tony Lindgren <tony@atomide.com> found a bug in a previous version of this
patch - thanks Tony.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Tony Lindgren <tony@atomide.com>
In preparation for OMAP_CHIP() removal, split clkdm_init() into four
functions. This allows some of them to be called multiple times: for
example, clkdm_register_clkdms() can be called once to register
clockdomains that are common to a group of SoCs, and once to register
clockdomains that are specific to a single SoC.
The appropriate order to call these functions - which is enforced
by the code - is:
1. clkdm_register_platform_funcs()
2. clkdm_register_clkdms() (can be called multiple times)
3. clkdm_register_autodeps() (optional; deprecated)
4. clkdm_complete_init()
Convert the OMAP2, 3, and 4 clockdomain init code to use these new
functions.
While here, improve documentation, and increase CodingStyle
conformance by shortening some local variable names.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
The OMAP_REVBITS_* macros are just used as otherwise meaningless
aliases for the numbers zero through five, so remove these macros.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Tested-by: Igor Grinberg <grinberg@compulab.co.il>
Tested-by: Abhilash Koyamangalath <abhilash.kv@ti.com>
omap3_cpuinfo() contains essentially duplicated code from
omap3_check_revision(), just for the purpose of determining the chip ES level.
Set the cpu_rev char array pointer in omap3_check_revision() instead,
and drop the now-useless code from omap3_cpuinfo().
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Tested-by: Igor Grinberg <grinberg@compulab.co.il>
Tested-by: Abhilash Koyamangalath <abhilash.kv@ti.com>
Emit a warning to the console in omap3_check_revision() if that code
cannot determine what type of SoC the system is currently running on.
Remove some extra whitespace, remove some duplicate code, and
add an appropriate comment to a fallthrough case.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Hemant Pedanekar <hemantp@ti.com>
Tested-by: Igor Grinberg <grinberg@compulab.co.il>
Tested-by: Abhilash Koyamangalath <abhilash.kv@ti.com>
Use explicit revision codes for OMAP/AM 3505/3517 ES levels, as the rest
of the OMAP2+ SoCs do in mach-omap2/cpu.c.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Sanjeev Premi <premi@ti.com>
Tested-by: Igor Grinberg <grinberg@compulab.co.il>
Tested-by: Abhilash Koyamangalath <abhilash.kv@ti.com>
The OMAP3505/AM3505 appears to be based on the same silicon as the
OMAP3517/AM3517, with some features disabled via eFuse bits. Follow
the same practice as OMAP3430 and identify these devices internally as
part of the OMAP3517/AM3517 family.
The OMAP3503/3515/3525/3530 chips appear to be based on the same silicon
as the OMAP3430, with some features disabled via eFuse bits. Identify
these devices internally as part of the OMAP3430 family.
Remove the old OMAP35XX_CLASS, which actually covered two very different
chip families. The OMAP3503/3515/3525/3530 chips will now be covered by
OMAP343X_CLASS, since the silicon appears to be identical. For the
OMAP3517/AM3517 family, create a new class, OMAP3517_CLASS.
Thanks to Tony Lindgren <tony@atomide.com> for some help with the second
revision of this patch.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Sanjeev Premi <premi@ti.com>
Cc: Tony Lindgren <tony@atomide.com>
Tested-by: Igor Grinberg <grinberg@compulab.co.il>
Tested-by: Abhilash Koyamangalath <abhilash.kv@ti.com>
* 'fixes' of git://git.linaro.org/people/arnd/arm-soc:
ARM: CSR: add missing sentinels to of_device_id tables
ARM: cns3xxx: Fix newly introduced warnings in the PCIe code
ARM: cns3xxx: Fix compile error caused by hardware.h removed
ARM: davinci: fix cache flush build error
ARM: davinci: correct MDSTAT_STATE_MASK
ARM: davinci: da850 EVM: read mac address from SPI flash
OMAP: omap_device: fix !CONFIG_SUSPEND case in _noirq handlers
OMAP2430: hwmod: musb: add missing terminator to omap2430_usbhsotg_addrs[]
OMAP3: clock: indicate that gpt12_fck and wdt1_fck are in the WKUP clockdomain
OMAP4: clock: fix compile warning
OMAP4: clock: re-enable previous clockdomain enable/disable sequence
OMAP: clockdomain: Wait for powerdomain to be ON when using clockdomain force wakeup
OMAP: powerdomains: Make all powerdomain target states as ON at init
The of_device_id tables used for matching should be terminated with
empty sentinel values.
Signed-off-by: Jamie Iles <jamie@jamieiles.com>
Signed-off-by: Barry Song <baohua.song@csr.com>
Commit be020f8618, "ARM: entry: abort-macro: specify registers to be
used for macros", while replacing register numbers with macro parameter
names, mismatched the name used for r1. For me, this resulted in user
space built for EABI with -march=armv4t -mtune=arm920t -mthumb-interwork
-mthumb broken on my OMAP1510 based Amstrad Delta (old ABI and no thumb
still worked for me though).
Fix this by using correct parameter name fsr instead of mismatched psr,
used by callers for another purpose.
Signed-off-by: Janusz Krzysztofik <jkrzyszt@tis.icnet.pl>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
commit d5341942d7 ("PCI: Make the struct
pci_dev * argument of pci_fixup_irqs const") did not change argument
of pdev_to_cnspci(), and thus introduced the following warnings:
CHECK arch/arm/mach-cns3xxx/pcie.c
pcie.c:177:60: warning: incorrect type in argument 1 (different modifiers)
pcie.c:177:60: expected struct pci_dev *dev
pcie.c:177:60: got struct pci_dev const *dev
CC arch/arm/mach-cns3xxx/pcie.o
pcie.c: In function 'cns3xxx_pcie_map_irq':
pcie.c:177: warning: passing argument 1 of 'pdev_to_cnspci' discards qualifiers from pointer target type
pcie.c:52: note: expected 'struct pci_dev *' but argument is of type 'const struct pci_dev *'
This patch fixes the issue.
Signed-off-by: Anton Vorontsov <cbouatmailru@gmail.com>
Commit c9d95fbe59 "ARM: convert PCI defines
to variables" deleted cns3xxx' hardware.h, but didn't remove references
for it, so do it now.
This patch removes lines that refer to hardware.h.
Signed-off-by: Tommy Lin <tommy.lin.1101@gmail.com>
Signed-off-by: Imre Kaloz <kaloz@openwrt.org>
Signed-off-by: Anton Vorontsov <cbouatmailru@gmail.com>
The TNET variant of DaVinci compiles some code that it shares
with other DaVinci variants, however it has a V6 CPU rather than
an ARM926T, thus the hardcoded call to arm926_flush_kern_cache_all()
in sleep.S will obviously fail, and we need to build with the
v6_flush_kern_cache_all() call instead. This was triggered by
manually altering the DaVinci config to build the TNET version.
Cc: Dave Martin <dave.martin@linaro.org>
Cc: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Cc: stable@kernel.org
MDSTAT.STATE occupies bits 0..5 according to all available documentation, so fix
the #define MDSTAT_STATE_MASK at last. Using the wrong value seems to have been
harmless though...
Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
DA850/OMAP-L138 EMAC driver uses random mac address instead of
a fixed one because the mac address is not stuffed into EMAC
platform data.
This patch provides a function which reads the mac address
stored in SPI flash (registered as MTD device) and populates the
EMAC platform data. The function which reads the mac address is
registered as a callback which gets called upon addition of MTD
device.
NOTE: In case the MAC address stored in SPI flash is erased, follow
the instructions at [1] to restore it.
[1] http://processors.wiki.ti.com/index.php/GSG:_OMAP-L138_DVEVM_Additional_Procedures#Restoring_MAC_address_on_SPI_Flash
Modifications in v2:
Guarded registering the mtd_notifier only when MTD is enabled.
Earlier this was handled using mtd_has_partitions() call, but
this has been removed in Linux v3.0.
Modifications in v3:
a. Guarded da850_evm_m25p80_notify_add() function and
da850evm_spi_notifier structure with CONFIG_MTD macros.
b. Renamed da850_evm_register_mtd_user() function to
da850_evm_setup_mac_addr() and removed the struct mtd_notifier
argument to this function.
c. Passed the da850evm_spi_notifier structure to register_mtd_user()
function.
Modifications in v4:
Moved the da850_evm_setup_mac_addr() function within the first
CONFIG_MTD ifdef construct.
Signed-off-by: Rajashekhara, Sudhakar <sudhakar.raj@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Cc: stable@kernel.org
Fighting unfixed U-Boots and other beasts that may the cache in
a locked-down state when starting the kernel, we make sure to
disable all cache lock-down when initializing the l2x0 so we
are in a known state.
Cc: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com>
Cc: Rabin Vincent <rabin.vincent@stericsson.com>
Cc: Adrian Bunk <adrian.bunk@movial.com>
Cc: Rob Herring <robherring2@gmail.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Reviewed-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Reported-by: Jan Rinze <janrinze@gmail.com>
Tested-by: Robert Marklund <robert.marklund@stericsson.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
I was intrigued by the fact that the clock stood still on
the Integrator, but it wasn't strange at all, because the
timer was set up all wrong and probably has been for a
while. With this patch the clock starts ticking again:
make the timer periodic (reload), |= on the divisor bit
and load the timer before starting it.
Cc: stable@kernel.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
The suspend/resume _noirq handlers were #ifdef'd out in the
!CONFIG_SUSPEND case, but were still assigned to the dev_pm_ops
struct. Fix by defining them to NULL in the !CONFIG_SUSPEND case.
Reported-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Kevin Hilman <khilman@ti.com>
Add a missing array terminator to omap2430_usbhsotg_addrs[]. Without
this terminator, the omap_hwmod resource building code runs off the
end of the array, resulting in at least this error -- if not worse
behavior:
[ 0.578002] musb-omap2430: failed to claim resource 4
[ 0.583465] omap_device: musb-omap2430: build failed (-16)
[ 0.589294] Could not build omap_device for musb-omap2430 usb_otg_hs
This should have been part of commit
78183f3fdf ("omap_hwmod: use a null
structure record to terminate omap_hwmod_addr_space arrays") but was
evidently missed.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
When ARCH_HAS_HOLES_MEMORYMODEL is selected, pfn_valid calls
memblock_is_memory to test validity of a pfn:
> memblock_is_memory(pfn << PAGE_SHIFT);
On LPAE systems this cuts off the top bits, as the shift occurs before
the value is promoted to a phys_addr_t.
This patch replaces the shift with a call to __pfn_to_phys (which casts
pfn to phys_addr_t before shifting), preventing the loss of significant
bits.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Acked-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Also, clean up error messages by adding missing whitespace, fixing
capitalisations, removing double newlines, and reducing verbosity.
Signed-off-by: Johan Hovold <jhovold@gmail.com>
[khilman@ti.com: minor changelog/subject edits]
Signed-off-by: Kevin Hilman <khilman@ti.com>
Fix misc. typos in various comment and error message.
Signed-off-by: Johan Hovold <jhovold@gmail.com>
[khilman@ti.com: minor changelog/subject edits]
Signed-off-by: Kevin Hilman <khilman@ti.com>
* 'fixes' of master.kernel.org:/home/rmk/linux-2.6-arm:
ARM: pm: avoid writing the auxillary control register for ARMv7
ARM: pm: some ARMv7 requires a dsb in resume to ensure correctness
ARM: pm: arm920/926: fix number of registers saved
ARM: pm: CPU specific code should not overwrite r1 (v:p offset)
ARM: 7066/1: proc-v7: disable SCTLR.TE when disabling MMU
ARM: 7065/1: kexec: ensure new kernel is entered in ARM state
ARM: 7003/1: vexpress: Add clock definition for the SP805.
ARM: 7051/1: cpuimx* boards: fix mach-types errors
ARM: 7019/1: Footbridge: select CLKEVT_I8253 for ARCH_NETWINDER
ARM: 7015/1: ARM errata: Possible cache data corruption with hit-under-miss enabled
ARM: 7014/1: cache-l2x0: Fix L2 Cache size calculation.
ARM: 6967/1: ep93xx: ts72xx: fix board model detection
ARM: 6965/1: ep93xx: add model detection for ts-7300 and ts-7400 boards
ARM: cache: detect VIPT aliasing I-cache on ARMv6
ARM: twd: register clockevents device before enabling PPI
ARM: realview: ensure visibility of writes during reset
ARM: perf: make name of arm_pmu_type consistent
ARM: perf: fix prototype of release_pmu
ARM: fix perf build with uclibc toolchains
Add clock control support for sh7372 CMT hardware blocks.
No upstream sh7372 boards are making use of CMT3 + CMT4,
but the sh7372 hardware happens to come out of reset with
all CMT MSTP clocks _enabled_, so to save power we need
to implement a fix in software to shut down unused clocks.
This patch relies on the recently merged
794d78f drivers: sh: late disabling of clocks V2
to make sure the unused clocks get disabled as expected.
Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Add clock control support for sh7372 MSIOF hardware blocks.
No upstream sh7372 boards are making use of MSIOF0->2,
but the sh7372 hardware happens to come out of reset with
all MSIOF MSTP clocks _enabled_, so to save power we need
to implement a fix in software to shut down unused clocks.
This patch relies on the recently merged
794d78f drivers: sh: late disabling of clocks V2
to make sure the unused clocks get disabled as expected.
Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
USB-DMAC1 needs SMSTPCR4/MSTP407 controls, not MSTP214
this patch tested on mackerel board
Reported-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This patch removes support for the SGX interrupt source in
the sh7372 INTCS controller.
The SGX hardware block included in sh7372 is already hooked
up to the ARM Cortex-A8 core using the INTCA controller,
so SGX users are encouraged to make use of that interrupt
source instead.
Removing support for the SGX interrupt source in INTCS
simplifies the sh7372 power management code by allowing
us to assume that only INTCA needs to be powered on to
operate the SGX hardware.
If the INTCS interrupt source would be kept then the kernel
would be forced to deal with additional dependencies that does
not follow the regular power domain hiearachy. With this
patch in place we can safely power down INTCS while the
SGX is operating.
Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
For ARMv7 kernels running in the non-secure world, writing to the
auxillary control register causes an abort, so we must avoid directly
writing the auxillary control register. If the ACR has already been
reinitialized by SoC code, don't try to restore it.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Add a dsb after the isb to ensure that the previous writes to the
CP15 registers take effect before we enable the MMU.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
ARM920 and ARM926 save four registers, not three. Fix the size of
the suspend region required.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
r1 stores the v:p offset from the CPU invariant resume code, and is
expected to be preserved by the CPU specific code. Overwriting it is
not a good idea.
We've managed to get away with it on sa1100 platforms because most
happen to have PHYS_OFFSET == PAGE_OFFSET, but that may not be the
case depending on kernel configuration. So fix this latent bug.
This fixes xsc3 as well which was saving and restoring this register
independently.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
cpu_v7_reset disables the MMU and then branches to the provided address.
On Thumb-2 kernels, we should take care to clear the Thumb Exception
enable bit in the System Control Register, otherwise this may wreak
havok in the code to which we are branching (for example, an ARM kernel
image via kexec).
Reviewed-by: Dave Martin <dave.martin@linaro.org>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Commit 540b5738 ("ARM: 6999/1: head, zImage: Always Enter the kernel in
ARM state") mandates that the kernel should be entered in ARM state.
If a Thumb-2 kernel kexecs a new kernel image, we need to ensure that
we change state when branching to the new code. This patch replaces a
mov pc, lr with a bx lr on Thumb-2 kernels so that we transition to ARM
state if need be.
Reviewed-by: Dave Martin <dave.martin@linaro.org>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This patch updates the recently submitted
"Associate the HDMI clock together with LCDC1 on sh7372"
to V2 with the following change:
- Use lcdc1_device on AP4EVB to build properly.
Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl>
commit 20d5d55149 (OMAP2: PM debug:
remove register dumping) left some code lying around which doesn't
do anything. Clean it up.
Signed-off-by: Michael Jones <michael.jones@matrix-vision.de>
Signed-off-by: Kevin Hilman <khilman@ti.com>
The nfsservctl system call is now gone, so we should remove all
linkage for it.
Signed-off-by: NeilBrown <neilb@suse.de>
Signed-off-by: J. Bruce Fields <bfields@redhat.com>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
This patch fixes following building error:
--
arch/arm/mach-footbridge/dc21285.c: In function 'dc21285_preinit':
arch/arm/mach-footbridge/dc21285.c:299:2: error: 'vga_base' undeclared (first use in this function)
arch/arm/mach-footbridge/dc21285.c:299:2: note: each undeclared identifier is reported only once for each function it appears in
make[1]: *** [arch/arm/mach-footbridge/dc21285.o] Error 1
--
Signed-off-by: Bryan Wu <bryan.wu@canonical.com>
Acked-by: Rob Herring <rob.herring@calxeda.com>
This patch fixed following building error:
--
arch/arm/mach-orion5x/pci.c: In function 'orion5x_pci_sys_setup':
arch/arm/mach-orion5x/pci.c:563:2: error: 'vga_base' undeclared (first use in this function)
arch/arm/mach-orion5x/pci.c:563:2: note: each undeclared identifier is reported only once for each function it appears in
make[1]: *** [arch/arm/mach-orion5x/pci.o] Error 1
make[1]: *** Waiting for unfinished jobs....
--
Signed-off-by: Bryan Wu <bryan.wu@canonical.com>
Acked-by: Rob Herring <rob.herring@calxeda.com>
Upstream commit d5341942d7 "PCI: Make the
struct pci_dev * argument of pci_fixup_irqs const." leaked an extra
"const" into an actual call site (vs a proto/decl) which causes this:
arch/arm/mach-orion5x/dns323-setup.c: In function 'dns323_pci_map_irq':
arch/arm/mach-orion5x/dns323-setup.c:80: error: expected expression before 'const'
arch/arm/mach-orion5x/dns323-setup.c:80: error: too few arguments to function 'orion5x_pci_map_irq'
make[3]: *** [arch/arm/mach-orion5x/dns323-setup.o] Error 1
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Acked-by: Nicolas Pitre <nico@fluxnic.net>
Acked-by: Ralf Baechle <ralf@linux-mips.org>
Commit c03f007a8b (OMAP: PM:
omap_device: add system PM methods for PM domain handling) mistakenly
used SET_SYSTEM_SLEEP_PM_OPS() when trying to configure custom methods
for the PM domains noirq methods. Fix that by setting only the
suspend_noirq and resume_noirq methods with custom versions.
Note that all other PM domain methods (including the "normal"
suspend/resume methods) are populated using USE_PLATFORM_PM_SLEEP_OPS,
which configures them all to the default subsystem (platform_bus)
methods.
Reported-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Tested-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Kevin Hilman <khilman@ti.com>
Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl>
Associate the HDMI clock together with LCDC1 on sh7372.
Without this patch Suspend-to-RAM hangs on the boards
AP4EVB and Mackerel. The code hangs in the LCDC driver
where the software is waiting forever for the hardware to
power down. By explicitly associating the HDMI clock with
LCDC1 we can make sure the HDMI clock is enabled using
Runtime PM whenever the driver is accessing the hardware.
This HDMI and LCDC1 dependency is documented in the sh7372
data sheet. Older kernels did work as expected but the
recently merged (3.1-rc)
794d78f drivers: sh: late disabling of clocks V2
introduced code to turn off clocks lacking software reference
which happens to include the HDMI clock that is needed by
LCDC1 to operate as expected.
Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl>
Introduce them for each omap variant and just make them all call
omap2_init_common_infrastructure for now. Do this for each board-*.c
file except for board-generic and board-omap3beagle as they use
the same machine ID for multiple SoCs.
No functional changes.
Signed-off-by: Tony Lindgren <tony@atomide.com>
There's no need to call omap2_init_common_devices from init_early.
It no longer does anything else except reprogram the memory timings
for some boards, so it's better to do it later so we have a chance
to get console messages if something goes wrong.
Move it to happen after omap_serial_init gets called. And while
patching it anyways, rename it to omap_sdrc_init as suggested by
Benoit Cousson <b-cousson@ti.com>.
Signed-off-by: Tony Lindgren <tony@atomide.com>
This was a typo in clockdev declaration for at91sam9261 SoC.
Fix the kernel hanging when switching clocksource to TC (tcb_clksrc).
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Acked-by: Remy Bohmer <linux@bohmer.net>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
It seems that an entry for the SP805 watchdog in the table of clocks was
missing. This results in the sp805_wdt driver rejecting the device with
the following errors:
sp805-wdt mb:wdt: Clock not found
sp805-wdt mb:wdt: Probe Failed!!!
sp805-wdt: probe of mb:wdt failed with error -2
While not obviously stated in the hardware docs, the onboard SP810's
"REFCLK" is connected to a 32.768KHz crystal, and this drives the
watchdog. Add a struct clk and corresponding lookup entry for it.
Signed-off-by: Nick Bowler <nbowler@elliptictech.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
As noted by Grant Likely <grant.likely@secretlab.ca>, omap2+ Makefile unnecessarily
repeats entries for common device init code instead of using Kconfig symbol.
Remove references to hsmmc.o and board-flash.o. Also omap_phy_internal.o
references can be removed once it has some Kconfig symbol to use.
Signed-off-by: Tony Lindgren <tony@atomide.com>
The oscillator that supplies GPT12_FCLK and WDT1_FCLK exists in the
WKUP powerdomain[1]. This resolves at least one boot-time warning:
omap_hwmod: gpt12_fck: missing clockdomain for gpt12_fck.
1. _OMAP34xx Multimedia High Security (HS) Device Silicon Revision 3.1.x
Security Addendum Version K (SWPU119K)_ Figure 3-29. August 2010.
I made some changes to the entry in the ARM Machine Registry after
submission which was the wrong thing to do.
This patch should help to fix this error.
Signed-off-by: Eric Bénard <eric@eukrea.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Fix the following compile warning:
arch/arm/mach-omap2/clock44xx_data.c: In function 'omap4xxx_clk_init':
arch/arm/mach-omap2/clock44xx_data.c:3371:6: warning: 'cpu_clkflg' may be used uninitialized in this function
The approach taken here is intended to work if omap4xxx_clk_init() is
converted into an initcall.
Thanks to Bjarne Steinsbo <bsteinsbo@gmail.com> for proposing another
approach.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Bjarne Steinsbo <bsteinsbo@gmail.com>
After commit 665d001338 ("OMAP2+: hwmod:
Follow the recommended PRCM module enable sequence"), device drivers
for OMAP IP blocks that do not use runtime PM can cause oopses or
kernel instability[1][2].
This is because those non-runtime PM drivers do not use the hwmod
code, which implements the correct IP block enable and disable
sequence.
Several options for dealing with this problem have been proposed:
1. Add a new field to the OMAP struct clk to mark clocks that are
currently used by non-runtime PM drivers. Modify the clock code to
use the old clockdomain sequence for these marked clocks. As
drivers are converted to use runtime PM, remove the annotation from
the clocks.
2. Similar to #1, but associate the flag with the struct omap_clk
instead.
3. Add IDLEST wait support to the OMAP4 clock code, similar to the way
it is implemented for OMAP2/3, and enable it in each struct clk
currently used by non-runtime PM drivers. As drivers are converted
to use runtime PM, remove the annotation from the clocks.
4. Do nothing; leave the problem to those responsible for the
unconverted drivers.
5. Re-enable clock-based clockdomain control in the OMAP4 clock code.
This would revert back to the behavior of Linux 3.0, simply with a
slightly longer module enable/disable latency.
Unfortunately, no approach seemed particularly good. Options 1
through 3 seemed unwise due to the following reasons:
A. The OMAP struct clks are intended primarily to describe hardware
clock nodes, and the intention is that no driver-specific data
should be stored there (applies to #1)
B. The resulting patch would have been quite large for the -rc series
(applies to #1, #2, #3)
C. The patch would have been a new, yet temporary hack; and similar fixes
have drawn negative comments in the recent past (see for example [3])
Option 4 is undesirable because commit
665d001338 ("OMAP2+: hwmod: Follow the
recommended PRCM module enable sequence") has resulted in a less
stable kernel; and kernel stability is more important than OMAP4 power
management.
Option 5 is the approach taken in this patch. This seemed to be the
least intrusive approach for 3.1-rc.
The approach in this patch was originally proposed by Ohad Ben-Cohen
<ohad@wizery.com>. I'm simply writing the commit message and passing
it along.
...
Thanks to Luciano Coelho <coelho@ti.com> for reporting the problem.
Thanks to Ohad Ben-Cohen <ohad@wizery.com> for tracking the problem
down, generating a temporary workaround, and proposing a patch to deal
with the problem. Thanks to Rajendra Nayak <rnayak@ti.com> for
proposing another patch to deal with the problem. Thanks to Felipe
Balbi <balbi@ti.com> for comments.
1. Coelho, Luciano <coelho@ti.com>. _Re: Oops on ehci_hcd when
booting 3.0.0-rc2 on panda_. Tue, 09 Aug 2011 14:26:08 +0300.
Posted to the <linux-omap@vger.kernel.org> mailing list. Available
from (among others)
http://www.spinics.net/linux/lists/linux-omap/msg55213.html
2. Munegowda, Keshava <keshava_mgowda@ti.com>. _Re: Oops on ehci_hcd
when booting 3.0.0-rc2 on panda_. Thu, 11 Aug 2011 13:51:05 +0530.
Posted to the <linux-omap@vger.kernel.org> mailing list. Available
from (among others)
http://www.spinics.net/linux/lists/linux-omap/msg55371.html
3. King, Russell <linux@arm.linux.org.uk>. _Re: [PATCH 5/8] OMAP4:
PM: TEMP: Prevent l3init from idling/force sleep_. Thu, 23 Jun
2011 16:22:49 +0100. Posted to the <linux-omap@vger.kernel.org>
mailing list. Available from (among others)
http://www.mail-archive.com/linux-omap@vger.kernel.org/msg51392.html
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Luciano Coelho <coelho@ti.com>
Cc: Ohad Ben-Cohen <ohad@wizery.com>
Cc: Rajendra Nayak <rnayak@ti.com>
Cc: Benoît Cousson <b-cousson@ti.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
While using clockdomain force wakeup method, not waiting for powerdomain
to be effectively ON may end up locking the clockdomain FSM until a
next wakeup event occurs.
One such issue was seen on OMAP4430, where L4_PER was periodically
getting stuck in in-transition state when transitioning from from OSWR to ON.
This issue was reported and investigated by Patrick Titiano <p-titiano@ti.com>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Reported-by: Patrick Titiano <p-titiano@ti.com>
Cc: Kevin Hilman <khilman@ti.com>
Cc: Benoit Cousson <b-cousson@ti.com>
Cc: Paul Walmsley <paul@pwsan.com>
[paul@pwsan.com: updated to apply; added transition wait on clkdm_deny_idle();
remove two superfluous pwrdm_wait_transition() calls]
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Program all powerdomain target state as ON; this is to prevent domains
from hitting low power states (if bootloader has target states set to
something other than ON) and potentially even losing context while PM
is not fully initialized, which can cause the system to crash. The PM
late init code can then program the desired target state for all the
power domains.
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
[paul@pwsan.com: dropped comment typo hunk; fixed comment indent and moved
to kerneldoc; moved code to pwrdm_init(); changed pwrdm_init() argument name
to prevent clash; cleaned up patch description]
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Should be passing the parent clk object when
calling for parent rate.
Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This patch increases reset delay from 50 usec to 80 usec for
USB HOST PHY. In order to reset USB HOST PHY controller properly,
a little extra time is required during its reset cycle.
Signed-off-by: Yulgon Kim <yulgon.kim@samsung.com>
Signed-off-by: Jingoo Han <jg1.han@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This patch adds chained IRQ enter/exit functions to gpio interrupt
handler in order to function correctly on primary controllers with
different methods of flow control.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This patch adds chained IRQ enter/exit functions to external interrupt
handler in order to function correctly on primary controllers with
different methods of flow control.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This patch adds chained IRQ enter/exit functions to timer
interrupt handler in order to function correctly on primary
controllers with different methods of flow control.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
When S3C_PM_DEBUG_LED_SMDK is enabled for suspend/resume debugging, the following
compilation error occurs:
arch/arm/mach-s3c64xx/pm.c: In function 's3c_pm_debug_smdkled':
arch/arm/mach-s3c64xx/pm.c:41: error: implicit declaration of function 'gpio_set_value'
arch/arm/mach-s3c64xx/pm.c:41: error: implicit declaration of function 'S3C64XX_GPN'
arch/arm/mach-s3c64xx/pm.c: In function 's3c64xx_pm_init':
arch/arm/mach-s3c64xx/pm.c:184: error: implicit declaration of function 'gpio_request'
arch/arm/mach-s3c64xx/pm.c:188: error: implicit declaration of function 'gpio_direction_output'
Fix the error by including linux/gpio.h
Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Fixed the following warning for S5PV210.
arch/arm/mach-s5pv210/pm.c: In function 's5pv210_pm_add':
arch/arm/mach-s5pv210/pm.c:139: warning: assignment from
incompatible pointer type
Also, staticized the function.
Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This is a regression fix after migration to the external GIC.
The breakage has been introduced in commit 69644a8e23
("ARM: EXYNOS4: modify interrupt mappings for external GIC")
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
[kgene.kim@samsung.com: added commit id]
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
WARNING: vmlinux.o(.text+0xf47c): Section mismatch in reference from the function samsung_bl_set() to the (unknown reference) .init.data:(unknown)
The function samsung_bl_set() references
the (unknown reference) __initdata (unknown).
This is often because samsung_bl_set lacks a __initdata
annotation or the annotation of (unknown) is wrong.
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
According to commit 659fb32d1b
("replace irq_gc_ack() with {set,clr}_bit variants"), this
should be fixed.
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Since commit 8560a6cfc9
"arm: Footbridge: Use common i8253 clockevent",
ARCH_NETWINDER needs to select CLKEVT_I8253.
This patch fixes below build error with "make netwinder_defconfig".
LD .tmp_vmlinux1
arch/arm/mach-footbridge/built-in.o: In function `isa_timer_init':
isa-rtc.c:(.init.text+0x12c8): undefined reference to `clockevent_i8253_init'
isa-rtc.c:(.init.text+0x12d0): undefined reference to `i8253_clockevent'
arch/arm/mach-footbridge/built-in.o:(.data+0x198): undefined reference to `i8253_clockevent'
make: *** [.tmp_vmlinux1] Error 1
Signed-off-by: Axel Lin <axel.lin@gmail.com>
Acked-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This patch is a workaround for the 364296 ARM1136 r0p2 erratum (possible
cache data corruption with hit-under-miss enabled). It sets the
undocumented bit 31 in the auxiliary control register and the FI bit in
the control register, thus disabling hit-under-miss without putting the
processor into full low interrupt latency mode.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Tested-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This patch fixes L2 Cache size calculations for L2C-210, L2C-310 and
PL310, by changing the L2X0_AUX_CTRL_WAY_SIZE_MASK from 2 bits to 3
bits.
The Auxiliary Control Register for L2C-210, L2C-310 and PL310 has 3bits
[19:17] for Way size, however the existing code only uses 2 bits to
get this value. This results in incorrect cachesize calculations.
It also results in performing operations on the whole cache when we
erroneously decide that the range is big enough (due to l2x0_size being
too small) and also prints incorrect cachesize.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@st.com>
Acked-by: Will Deacon <will.deacon@arm.com>
Cc: stable@kernel.org
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Fix the obvious error in board detection logic, because according to the TS's
manual, the model is stored in the least three significant bits. For example
the byte read on my ts-7300 is 0x23 and the detection then fails.
Cc: Ryan Mallon <ryan@bluewatersys.com>
Acked-by: H Hartley Sweeten <hsweeten@visionengravers.com>
Signed-off-by: Petr Štetiar <ynezz@true.cz>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Cc: Ryan Mallon <ryan@bluewatersys.com>
Acked-by: H Hartley Sweeten <hsweeten@visionengravers.com>
Signed-off-by: Petr Štetiar <ynezz@true.cz>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* 'fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/linux-arm-soc: (32 commits)
ARM: mmp: Change the way we use timer 0 as clockevent timer.
ARM: mmp: Switch to using timer 1 as clocksource timer.
ARM: mmp: Also start timer 1 on boot.
ARM: pxa168/gplugd: free correct GPIO
ARM: pxa168/gplugd: get rid of mfp-gplugd.h
ARM: pxa: fix logic error in PJ4 iWMMXt handling
mach-sa1100: fix PCI build problem
omap: timer: Set dmtimer used as clocksource in autoreload mode
OMAP3: am3517crane: remove NULL board_mux from board file
arm: mach-omap2: mux: use kstrdup()
arch:arm:plat-omap:iovmm: remove unused variable 'va'
Update Nook Color machine 3284 to common Encore name
am3505/3517: Various platform defines for UART4
OMAP: hwmod: fix build break on non-OMAP4 multi-OMAP2 builds
OMAP: Fix linking error in twl-common.c for OMAP2/3/4 only builds
iMX: Fix build for iMX53
ARM: mx5: board-cpuimx51.c fixup irq_to_gpio() usage
OMAP2+: PM: SmartReflex: use put_sync_suspend for IRQ-safe disabling
OMAP3: beagle: don't touch omap_device internals
OMAP1: enable GENERIC_IRQ_CHIP
...
The current cache detection code does not check for an aliasing
I-cache if the D-cache is found to be VIPT aliasing.
This patch fixes the problem by always checking for an aliasing
I-cache on v6 and later.
Signed-off-by: Will Deacon <will.deacon@arm.com>
The smp_twd clockevents driver currently enables the local timer PPI
before the clockevents device is registered. This can lead to a kernel
panic if a spurious timer interrupt is generated before registration
has completed since the kernel will treat it as an IPI timer.
This patch moves the clockevents device registration before the IRQ
unmasking so that we can always handle timer interrupts once they can
occur.
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
