This is the second go through of the old DMA_nBIT_MASK macro,and there're not
so many of them left,so I put them into one patch.I hope this is the last round.
After this the definition of the old DMA_nBIT_MASK macro could be removed.
Signed-off-by: Yang Hongyang <yanghy@cn.fujitsu.com>
Cc: Russell King <rmk@arm.linux.org.uk>
Cc: Tony Lindgren <tony@atomide.com>
Cc: "David S. Miller" <davem@davemloft.net>
Cc: James Bottomley <James.Bottomley@HansenPartnership.com>
Cc: Greg KH <greg@kroah.com>
Cc: Takashi Iwai <tiwai@suse.de>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Replace all DMA_32BIT_MASK macro with DMA_BIT_MASK(32)
Signed-off-by: Yang Hongyang<yanghy@cn.fujitsu.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
with while (timeout-- > 0); timeout reaches -1 after the loop, so the tests
below are off by one. also don't do an '< 0' test on an unsigned.
Signed-off-by: Roel Kluin <roel.kluin@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
All JMC250 chips have no problem with higher bits support.
Adding it back.
Found-by: Ethan Hsiao <ethanhsiao@jmicron.com>
Signed-off-by: Guo-Fu Tseng <cooldavid@cooldavid.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
Clear all modified GHC register flags.
Fixed-by: Ethan Hsiao <ethanhsiao@jmicron.com>
Signed-off-by: Guo-Fu Tseng <cooldavid@cooldavid.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
We should sync ring descriptor to pci device after modifying it.
Signed-off-by: Guo-Fu Tseng <cooldavid@cooldavid.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
This patch modifies messages to display correct hardware version.
Signed-off-by: Guo-Fu Tseng <cooldavid@cooldavid.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
When the napi api was changed to separate its 1:1 binding to the net_device
struct, the netif_rx_[prep|schedule|complete] api failed to remove the now
vestigual net_device structure parameter. This patch cleans up that api by
properly removing it..
Signed-off-by: Neil Horman <nhorman@tuxdriver.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Although the hardware supports the 64bit DMA address in design,
but later found that it actually not working.
This patch reduced the rang to 32bit.
Found-by: "Ethan" <ethanhsiao@jmicron.com>
Signed-off-by: "Guo-Fu Tseng" <cooldavid@cooldavid.org>
Acked-by: Jeff Garzik <jgarzik@redhat.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Due to the hardware design, except the first chip on the market,
other chips needs to setup the clock source for MAC processor
implicitly through Global Host Control Register(GHC).
(Strange design huh?)
10/100M uses the PCI-E as clock source, and 1G uses GPHY.
And I reordered the code a little, to make it easier to read.
Found-by: "Ethan" <ethanhsiao@jmicron.com>
Fixed-by: "akeemting" <akeem@jmicron.com>
Signed-off-by: "Guo-Fu Tseng" <cooldavid@cooldavid.org>
Acked-by: Jeff Garzik <jgarzik@redhat.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Convert driver to new net_device_ops. Compile tested only.
Signed-off-by: Stephen Hemminger <shemminger@vyatta.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This is the minimal patch to fix endian mismatches. These are
probably bugs on big-endian arches, noops on little endian.
jme_rxsum_ok could be improved to directly take a __le16 and
change all of the masks/sets to be in little-endian, but
has not been done here to keep the patch small.
Signed-off-by: Harvey Harrison <harvey.harrison@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
The generic packet receive code takes care of setting
netdev->last_rx when necessary, for the sake of the
bonding ARP monitor.
Drivers need not do it any more.
Some cases had to be skipped over because the drivers
were making use of the ->last_rx value themselves.
Signed-off-by: David S. Miller <davem@davemloft.net>
A number of places still use %02x:...:%02x because it's
in debug statements or for no real reason. Make a few
of them use %pM.
Signed-off-by: Johannes Berg <johannes@sipsolutions.net>
Signed-off-by: David S. Miller <davem@davemloft.net>
2.6.27-git2 kernel build fails with allyesconfig on powerpc with
build error
<introduced by commit 01f2e4ead2c51226ed1283ef6a8388ca6f4cff8f>
CC drivers/net/enic/enic_main.o
drivers/net/enic/enic_main.c: In function âenic_queue_wq_skb_tsoâ:
drivers/net/enic/enic_main.c:576: error: implicit declaration of function âcsum_ipv6_magicâ
make[3]: *** [drivers/net/enic/enic_main.o] Error 1
<introduced by commit c4e84bde1d595d857d3c74b49b9c45cc770df792>
drivers/net/qlge/qlge_main.c: In function âql_tsoâ:
drivers/net/qlge/qlge_main.c:1862: error: implicit declaration of function âcsum_ipv6_magicâ
make[3]: *** [drivers/net/qlge/qlge_main.o] Error 1
<introduced by commit 95252236e73e789dd186ce796a2abc60b3a61ebe>
drivers/net/jme.c: In function âjme_tx_tsoâ:
drivers/net/jme.c:1784: error: implicit declaration of function âcsum_ipv6_magicâ
make[2]: *** [drivers/net/jme.o] Error 1
Signed-off-by: Kamalesh Babulal <kamalesh@linux.vnet.ibm.com>
Signed-off-by: Ron Mercer <ron.mercer@qlogic.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
The file(s) below do not use LINUX_VERSION_CODE nor KERNEL_VERSION.
drivers/net/jme.c
This patch removes the said #include <version.h>.
Signed-off-by: Huang Weiyi <weiyi.huang@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
drivers/net/jme.c:1598: warning: ‘jme_set_100m_half’ defined but not used
drivers/net/jme.c:1618: warning: ‘jme_wait_link’ defined but not used
Signed-off-by: David S. Miller <davem@davemloft.net>
Fix IRQ handle bug when interrupt mode.
The driver was incorrectly handled and returned IRQ_HANDLED
while the device is not generating the interrupt.
It happened due to faulty determination of interrupt status register.
Found by: "Ethan" <ethanhsiao@jmicron.com>
Fixed by: "akeemting" <akeem@jmicron.com>
Signed-off-by: Guo-Fu Tseng <cooldavid@cooldavid.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
1. Set bit 5 of GPREG1 to 1 to enable hardware workaround for half-duplex
mode. Which the MAC processor generates CRS/COL by itself instead of
receive it from PHY processor.
2. Set bit 6 of GPREG1 to 1 to enable hardware workaround that masks the
MAC processor working right while calculating IPv6 RSS in 10/100
mode.
3. Group the workaround codes all together.
Signed-off-by: Guo-Fu Tseng <cooldavid@cooldavid.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
