Ben Skeggs
c20ab3e1cb
drm/nvd9/disp: stub some more api hooks so we don't oops on resume
...
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-09-20 16:12:08 +10:00
Ben Skeggs
37b034a64b
drm/nvd0/disp: tidy up what we have so far
...
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-09-20 16:07:49 +10:00
Ben Skeggs
ee41779e76
drm/nvd0/disp: rewrite irq handler, should be somewhat sturdier now
...
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-09-20 16:07:46 +10:00
Ben Skeggs
f20ce9629f
drm/nvd0/disp: do modeset irq handling from tasklet
...
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-09-20 16:07:42 +10:00
Ben Skeggs
3b6d83d1b9
drm/nvd0/disp: untested LVDS support
...
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-09-20 16:07:36 +10:00
Ben Skeggs
c6f2f71dae
drm/nvd0/disp: track down fb positioning method
...
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-09-20 16:07:32 +10:00
Ben Skeggs
ff8ff50342
drm/nvd0/disp: determine U table config in or_mode_set()
...
Takes a gamble and presumes that we can safely store something random in
OR_MODE_CTRL+4, the hw doesn't seem to mind...
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-09-20 16:07:29 +10:00
Ben Skeggs
b681993f7a
drm/nvd0/disp: dac load detect
...
VBIOS does more than this, as does nv50/nvc0 driver in nouveau. Traces
of the NVIDIA binary driver however, show pretty much just this being
done... Seems to work for me, it'll be fine for the moment.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-09-20 16:07:22 +10:00
Ben Skeggs
629c1b9207
drm/nvd0/disp: handle sync polarity, kill off some unknown
...
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-09-20 16:07:18 +10:00
Ben Skeggs
f3fdc52dd7
drm/nvd0/disp: scaling
...
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-09-20 16:07:15 +10:00
Ben Skeggs
a46232ee09
drm/nvd0/disp: push the update button in mode_set_base()
...
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-09-20 16:07:09 +10:00
Ben Skeggs
8ea0d4aa60
drm/nvd0/disp: fixup clut so it actually works
...
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-09-20 16:07:05 +10:00
Ben Skeggs
3a89cd0292
drm/nvd0/disp: initial attempt at modeset irq handling
...
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-09-20 16:07:01 +10:00
Ben Skeggs
b6d8e7ec38
drm/nvd0/disp: stub dac load detect, prevents oops
...
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-09-20 16:06:57 +10:00
Ben Skeggs
8eaa9669f8
drm/nvd0/disp: dac encoder module
...
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-09-20 16:06:50 +10:00
Ben Skeggs
a36f04c044
drm/nvd0/disp: extend the init voodoo to cover crtcs
...
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-09-20 16:06:47 +10:00
Ben Skeggs
c0cc92a115
drm/nvd0/disp: remove lp reordering from vram dmaobj, create fb dmaobjs
...
Fixes CLUT being messed up. Mostly.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-09-20 16:06:44 +10:00
Ben Skeggs
1d6e7a59f7
drm/nvd0/disp: some magic to make evo happeir
...
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-09-20 16:06:37 +10:00
Ben Skeggs
438d99e3b1
drm/nvd0/disp: initial crtc object implementation
...
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-09-20 16:06:30 +10:00
Ben Skeggs
270a574780
drm/nvd0/disp: skeletal handling of modeset interrupts
...
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-09-20 16:06:24 +10:00
Ben Skeggs
83fc083cbb
drm/nvd0/disp: start on SOR encoder functions
...
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-09-20 16:06:21 +10:00
Ben Skeggs
efd272a7a0
drm/nvd0/disp: setup a couple of dma objects we'll need
...
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-09-20 16:06:07 +10:00
Ben Skeggs
4600522a8f
drm/nvd0/disp: start on interrupt handling
...
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-09-20 16:06:01 +10:00
Ben Skeggs
51beb428e4
drm/nvd0/disp: whip up some basic dma handling for the evo channels
...
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-09-20 16:05:57 +10:00
Ben Skeggs
26f6d88b32
drm/nvd0/disp: very initial evo setup
...
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-09-20 16:05:54 +10:00
