Commit 87c614175b (spi: spi-imx: fix MX51_ECSPI_* macros when cs >
3) ensured that the argument passed to the macros was masked with &3,
so that we no longer write outside the intended fields in the various
control registers. When all chip selects are gpios, this works just
fine.
However, when a mix of native and gpio chip selects are in use, that
masking is too naive. Say, for example, that SS0 is muxed as native
chip select, and there is also a chip at 4 (obviously with a gpio
cs). In that case, when accessing the latter chip, both the SS0 pin
and the gpio pin will be asserted low.
The fix for this is to use the ->unused_native_cs value as channel
number for any spi device which uses a gpio as chip select.
Signed-off-by: Rasmus Villemoes <linux@rasmusvillemoes.dk>
Link: https://lore.kernel.org/r/20230602115731.708883-1-linux@rasmusvillemoes.dk
Signed-off-by: Mark Brown <broonie@kernel.org>
Just drop a redundant empty line from the dw_spi_debugfs_init() function
left in the framework of the commit 0178f1e5d9 ("spi-dw-core.c: Fix
error checking for debugfs_create_dir") after removing the last return
statement.
Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Link: https://lore.kernel.org/r/20230530221725.26319-1-Sergey.Semin@baikalelectronics.ru
Signed-off-by: Mark Brown <broonie@kernel.org>
Having no DMA is not an error. The simplest reason is not having it
configured. SPI will still be usable, so raise a warning instead to
get still some attention.
Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
Link: https://lore.kernel.org/r/20230531072850.739021-1-alexander.stein@ew.tq-group.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Merge series from Boerge Struempfel <boerge.struempfel@gmail.com>:
Some spi controller switch the mosi line to high, whenever they are
idle. This may not be desired in all use cases. For example neopixel
leds can get confused and flicker due to misinterpreting the idle state.
Therefore, we introduce a new spi-mode bit, with which the idle behaviour
can be overwritten on a per device basis.
Merge series from Uwe Kleine-König <u.kleine-koenig@pengutronix.de>:
Hello,
compared to (implicit) v1 sent in March with Message-Id:
<20230309094704.2568531-1-u.kleine-koenig@pengutronix.de>, I reworked
patch 1 on feedback by AngeloGioacchino Del Regno. Patches 2 and 3 got
his Reviewed-by.
Best regards
Uwe
Uwe Kleine-König (3):
spi: mt65xx: Properly handle failures in .remove()
spi: mt65xx: Convert to platform remove callback returning void
spi: mt65xx: Don't disguise a "return 0" as "return ret"
drivers/spi/spi-mt65xx.c | 30 +++++++++++++++++-------------
1 file changed, 17 insertions(+), 13 deletions(-)
base-commit: ac9a78681b
--
2.39.2
By default, the spi-imx controller pulls the mosi line high, whenever it
is idle. This behaviour can be inverted per CS by setting the
corresponding DATA_CTL bit in the config register of the controller.
Also, since the controller mode-bits have to be touched anyways, the
SPI_CPOL and SPI_CPHA are replaced by the combined SPI_MODE_X_MASK flag.
Signed-off-by: Boerge Struempfel <boerge.struempfel@gmail.com>
Link: https://lore.kernel.org/r/20230530141641.1155691-3-boerge.struempfel@gmail.com
Signed-off-by: Mark Brown <broonie@kernel.org>
This patch fixes the error checking in spi-dw-core.c in
debugfs_create_dir. The DebugFS kernel API is developed in
a way that the caller can safely ignore the errors that
occur during the creation of DebugFS nodes.
Signed-off-by: Osama Muhammad <osmtendev@gmail.com>
Link: https://lore.kernel.org/r/20230520224025.14928-1-osmtendev@gmail.com
Signed-off-by: Mark Brown <broonie@kernel.org>
The `width_available` array is currently placed on the
`f_ospi_supports_op_width()` function's stack.
But the array is never modified. Make it `static const`. This makes the
code slightly smaller and more efficient.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Link: https://lore.kernel.org/r/20230528195830.164669-3-lars@metafoo.de
Signed-off-by: Mark Brown <broonie@kernel.org>
Replace the combination of devm_clk_get_enable() plus clk_prepare_enable()
with devm_clk_get_enabled(). Slightly reduces the amount of boilerplate
code.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Link: https://lore.kernel.org/r/20230528195830.164669-1-lars@metafoo.de
Signed-off-by: Mark Brown <broonie@kernel.org>
Because of the earlier
if (ret)
return ret;
ret is always zero at the end of mtk_spi_suspend(). Write it as explicit
return 0 for slightly improved clearness.
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Link: https://lore.kernel.org/r/20230530081648.2199419-4-u.kleine-koenig@pengutronix.de
Signed-off-by: Mark Brown <broonie@kernel.org>
The .remove() callback for a platform driver returns an int which makes
many driver authors wrongly assume it's possible to do error handling by
returning an error code. However the value returned is (mostly) ignored
and this typically results in resource leaks. To improve here there is a
quest to make the remove callback return void. In the first step of this
quest all drivers are converted to .remove_new() which already returns
void.
Trivially convert this driver from always returning zero in the remove
callback to the void returning variant.
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Link: https://lore.kernel.org/r/20230530081648.2199419-3-u.kleine-koenig@pengutronix.de
Signed-off-by: Mark Brown <broonie@kernel.org>
Returning an error code in a platform driver's remove function is wrong
most of the time and there is an effort to make the callback return
void. To prepare this rework the function not to exit early.
There wasn't a real problem because if pm runtime resume failed the only
step missing was pm_runtime_disable() which isn't an issue.
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20230530081648.2199419-2-u.kleine-koenig@pengutronix.de
Signed-off-by: Mark Brown <broonie@kernel.org>
It is usually better to request all necessary resources (clocks,
regulators, ...) before starting to make use of them. That way they do
not change state in case one of the resources is not available yet and
probe deferral (-EPROBE_DEFER) is necessary. This is particularly
important for DMA channels and IOMMUs which are not enforced by
fw_devlink yet (unless you use fw_devlink.strict=1).
spi-qup does this in the wrong order, the clocks are enabled and
disabled again when the DMA channels are not available yet.
This causes issues in some cases: On most SoCs one of the SPI QUP
clocks is shared with the UART controller. When using earlycon UART is
actively used during boot but might not have probed yet, usually for
the same reason (waiting for the DMA controller). In this case, the
brief enable/disable cycle ends up gating the clock and further UART
console output will halt the system completely.
Avoid this by requesting the DMA channels before changing the clock
state.
Fixes: 612762e82a ("spi: qup: Add DMA capabilities")
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Link: https://lore.kernel.org/r/20230518-spi-qup-clk-defer-v1-1-f49fc9ca4e02@gerhold.net
Signed-off-by: Mark Brown <broonie@kernel.org>
After commit b8a1a4cd5a ("i2c: Provide a temporary .probe_new()
call-back type"), all drivers being converted to .probe_new() and then
03c835f498 ("i2c: Switch .probe() to not take an id parameter")
convert back to (the new) .probe() to be able to eventually drop
.probe_new() from struct i2c_driver.
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Link: https://lore.kernel.org/r/20230525211047.735789-1-u.kleine-koenig@pengutronix.de
Signed-off-by: Mark Brown <broonie@kernel.org>
this patch advertise the availability of Dual and Quad SPI mode
for ipm design.
Signed-off-by: Qii Wang <qii.wang@mediatek.com>
Signed-off-by: Tim.Kuo <Tim.kuo@mediatek.com>
Link: https://lore.kernel.org/r/20230523112608.10298-1-qii.wang@mediatek.com
Signed-off-by: Mark Brown <broonie@kernel.org>
When all bits of IER are set to 0, we still can observe the lpspi irq events
when using DMA mode to transfer data.
So disable irq to avoid the too much irq events.
Signed-off-by: Clark Wang <xiaoning.wang@nxp.com>
Link: https://lore.kernel.org/r/20230505063557.3962220-1-xiaoning.wang@nxp.com
Signed-off-by: Mark Brown <broonie@kernel.org>
The ecspi IP block on imx51/imx53/imx6 have four native chip
selects. Tell that to the spi core so that any non-gpio chip selects
get validated against that upper bound.
Also set the SPI_MASTER_GPIO_SS so that the core verifies that, in the
case where both native and gpio chip selects are in use, there is at
least one leftover native chip select (or "channel", in the ecspi
language) for use by the slaves sitting on gpio chip selects.
Signed-off-by: Rasmus Villemoes <linux@rasmusvillemoes.dk>
Link: https://lore.kernel.org/r/20230425134527.483607-3-linux@rasmusvillemoes.dk
Signed-off-by: Mark Brown <broonie@kernel.org>
Near the top of the function, spi_imx->controller is set to
controller (and is of course never modified again). The rest of the
function uses a mix of the two expressions.
For consistency, readability and better code generation, drop all the
spi_imx-> indirections.
Signed-off-by: Rasmus Villemoes <linux@rasmusvillemoes.dk>
Link: https://lore.kernel.org/r/20230425134527.483607-2-linux@rasmusvillemoes.dk
Signed-off-by: Mark Brown <broonie@kernel.org>
When working in slave mode it seems the timing is exceedingly tight.
The TX FIFO can never empty, because the master is driving the clock so
zeros would be sent for those bytes where the FIFO is empty.
Return to interleaving the writing of the TX FIFO and the reading
of the RX FIFO to try to ensure the data is available when required.
Fixes: a84c11e16d ("spi: spi-cadence: Avoid read of RX FIFO before its ready")
Signed-off-by: Charles Keepax <ckeepax@opensource.cirrus.com>
Link: https://lore.kernel.org/r/20230518093927.711358-1-ckeepax@opensource.cirrus.com
Signed-off-by: Mark Brown <broonie@kernel.org>
The function debugfs_create_dir returns ERR_PTR if an error occurs,
and the appropriate way to verify for errors is to use the inline
function IS_ERR. The patch will substitute the null-comparison with
IS_ERR.
Suggested-by: Ivan Orlov <ivan.orlov0322@gmail.com
Signed-off-by: Yeqi Fu <asuk4.q@gmail.com
Link: https://lore.kernel.org/r/20230518052515.368978-1-asuk4.q@gmail.com
Signed-off-by: Mark Brown <broonie@kernel.org
The AMD Pensando Elba SoC has the Cadence QSPI controller integrated.
The quirk CQSPI_NEEDS_APB_AHB_HAZARD_WAR is added and if enabled
a dummy readback from the controller is performed to ensure
synchronization.
Signed-off-by: Brad Larson <blarson@amd.com
Link: https://lore.kernel.org/r/20230515181606.65953-8-blarson@amd.com
Signed-off-by: Mark Brown <broonie@kernel.org
New set/get APIs for accessing spi->chip_select were introduced by
'commit 9e264f3f85 ("spi: Replace all spi->chip_select and spi->cs_gpiod
references with function call")', but the 'commit 2c8606040a ("spi: dw:
Add support for AMD Pensando Elba SoC")' uses the old interface by directly
accessing spi->chip_select. So, replace all spi->chip_select references
in the driver with new get/set APIs.
Signed-off-by: Amit Kumar Mahapatra <amit.kumar-mahapatra@amd.com
Acked-by: Serge Semin <fancer.lancer@gmail.com
Link: https://lore.kernel.org/r/20230515130343.63770-1-amit.kumar-mahapatra@amd.com
Signed-off-by: Mark Brown <broonie@kernel.org
n_bytes variable in the driver represents the number of bytes per word
that needs to be sent/copied to fifo. Bits/word can be between 8 and 32
bits from the client but in memory they are a power of 2, same is mentioned
in spi.h header:
"
* @bits_per_word: Data transfers involve one or more words; word sizes
* like eight or 12 bits are common. In-memory wordsizes are
* powers of two bytes (e.g. 20 bit samples use 32 bits).
* This may be changed by the device's driver, or left at the
* default (0) indicating protocol words are eight bit bytes.
* The spi_transfer.bits_per_word can override this for each transfer.
"
Hence, round of n_bytes to a power of 2 to avoid values like 3 which
would generate unalligned/odd accesses to memory/fifo.
* tested on Baikal-T1 based system with DW SPI-looped back interface
transferring a chunk of data with DFS:8,12,16.
Fixes: a51acc2400 ("spi: dw: Add support for 32-bits max xfer size")
Suggested-by: Andy Shevchenko <andriy.shevchenko@intel.com
Signed-off-by: Joy Chakraborty <joychakr@google.com
Reviewed-by: Serge Semin <fancer.lancer@gmail.com
Tested-by: Serge Semin <fancer.lancer@gmail.com
Link: https://lore.kernel.org/r/20230512104746.1797865-4-joychakr@google.com
Signed-off-by: Mark Brown <broonie@kernel.org
Store address width capabilities of DMA controller during init and check
the same per transfer to make sure the bits/word requirement can be met.
Current DW DMA driver requires both tx and rx channel to be configured
and functional hence a subset of both tx and rx channel address width
capability is checked with the width requirement(n_bytes) for a
transfer.
* tested on Baikal-T1 based system with DW SPI-looped back interface
transferring a chunk of data with DFS:8,12,16.
Signed-off-by: Joy Chakraborty <joychakr@google.com
Reviewed-by: Serge Semin <fancer.lancer@gmail.com
Tested-by: Serge Semin <fancer.lancer@gmail.com
Link: https://lore.kernel.org/r/20230512104746.1797865-3-joychakr@google.com
Signed-off-by: Mark Brown <broonie@kernel.org
Check capabilities of DMA controller during init to make sure it is
capable of handling MEM2DEV for tx channel, DEV2MEM for rx channel.
Current DW DMA driver requires both tx and rx channel to be configured
and functional for any kind of transfers to take effect including
half duplex. Hence, check for both tx and rx direction and fail on
unavailbility of either.
* tested on Baikal-T1 based system with DW SPI-looped back interface
transferring a chunk of data with DFS:8,12,16.
Signed-off-by: Joy Chakraborty <joychakr@google.com
Reviewed-by: Serge Semin <fancer.lancer@gmail.com
Tested-by: Serge Semin <fancer.lancer@gmail.com
Link: https://lore.kernel.org/r/20230512104746.1797865-2-joychakr@google.com
Signed-off-by: Mark Brown <broonie@kernel.org
Commit b1b90514ea ("spi: spi-cadence: Add support for Slave mode")
updated the code to trigger the IRQ when the FIFO was half empty,
overlapping filling more data into the FIFO and sending what is left.
This appears to cause regressions on the Zynq 7000, for transactions
longer than the FIFO size, below that no overlapping occurs.
It would appear from my testing that any attempt to put new data into
the FIFO whilst data is still transmitting causes data corruption
on both send and receive. If I am reading the commit message right
on commit 49530e6411 ("spi: cadence: Add usleep_range() for
cdns_spi_fill_tx_fifo()"), that would also seem to imply this is the
case.
On the assumption that this isn't an issue on the platform
the original slave mode support was added for, update the
cdns_transfer_one to only set the watermark to 50% of the FIFO size
when in slave mode. There by retaining the new behaviour for slave
mode but reverting to the older behaviour when the SPI is used a
master.
Fixes: b1b90514ea ("spi: spi-cadence: Add support for Slave mode")
Signed-off-by: Charles Keepax <ckeepax@opensource.cirrus.com
Link: https://lore.kernel.org/r/20230509164153.3907694-2-ckeepax@opensource.cirrus.com
Signed-off-by: Mark Brown <broonie@kernel.org
Recent changes to cdns_spi_irq introduced some issues.
Firstly, when writing the end of a longer transaction, the code in
cdns_spi_irq will write data into the TX FIFO, then immediately
fall into the if (!xspi->tx_bytes) path and attempt to read data
from the RX FIFO. However this required waiting for the TX FIFO to
empty before the RX data was ready.
Secondly, the variable trans_cnt is now rather inaccurately named
since in cases, where the watermark is set to 1, trans_cnt will be
1 but the count of bytes transferred would be much longer.
Finally, when setting up the transaction we set the watermark to 50%
of the FIFO if the transaction is great than 50% of the FIFO. However,
there is no need to split a tranaction that is smaller than the
whole FIFO, so anything up to the FIFO size can be done in a single
transaction.
Tidy up the code a little, to avoid repeatedly calling
cdns_spi_read_rx_fifo with a count of 1, and correct the three issues
noted above.
Fixes: b1b90514ea ("spi: spi-cadence: Add support for Slave mode")
Signed-off-by: Charles Keepax <ckeepax@opensource.cirrus.com
Link: https://lore.kernel.org/r/20230509164153.3907694-1-ckeepax@opensource.cirrus.com
Signed-off-by: Mark Brown <broonie@kernel.org
These SoCs has two SPI controllers. One of it is quite similar to previous
ones, but with internal clock divider removed; the other added MIPI DBI
Type-C offload based on the first one.
Add basical support for these controllers. As we're not going to
support the DBI functionality now, just implement the two kinds of
controllers as the same.
Co-developed-by: Icenowy Zheng <icenowy@aosc.io
Signed-off-by: Maksim Kiselev <bigunclemax@gmail.com
Reviewed-by: Andre Przywara <andre.przywara@arm.com
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com
Link: https://lore.kernel.org/r/20230510081121.3463710-5-bigunclemax@gmail.com
Signed-off-by: Mark Brown <broonie@kernel.org
Previously SPI controllers in Allwinner SoCs has a clock divider inside.
However now the clock divider is removed and to set the transfer clock
rate it's only needed to set the SPI module clock to the target value
and configure a proper work mode.
According to the datasheet there are three work modes:
| SPI Sample Mode | SDM(bit13) | SDC(bit11) | Run Clock |
|-------------------------|------------|------------|-----------|
| normal sample | 1 | 0 | <= 24 MHz |
| delay half cycle sample | 0 | 0 | <= 40 MHz |
| delay one cycle sample | 0 | 1 | >= 80 MHz |
Add a quirk for this kind of SPI controllers.
Co-developed-by: Icenowy Zheng <icenowy@aosc.io
Signed-off-by: Maksim Kiselev <bigunclemax@gmail.com
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com
Reviewed-by: Andre Przywara <andre.przywara@arm.com
Link: https://lore.kernel.org/r/20230510081121.3463710-4-bigunclemax@gmail.com
Signed-off-by: Mark Brown <broonie@kernel.org
As we're adding more properties to the OF match data, convert it to a
struct now.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io
Signed-off-by: Maksim Kiselev <bigunclemax@gmail.com
Reviewed-by: Samuel Holland <samuel@sholland.org
Reviewed-by: Andre Przywara <andre.przywara@arm.com
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com
Link: https://lore.kernel.org/r/20230510081121.3463710-3-bigunclemax@gmail.com
Signed-off-by: Mark Brown <broonie@kernel.org
Fixing the problem of enabling DMA mode and IRQ mode at the same time.
In this case, a value of more than 6bits is written to RDY_LVL, it can
cause an invasion of other registers, potentially leading to SPI
transfer failure.
Fixes: 1ee806718d ("spi: s3c64xx: support interrupt based pio mode")
Signed-off-by: Jaewon Kim <jaewon02.kim@samsung.com
Reported-by: Marek Szyprowski <m.szyprowski@samsung.com
Tested-by: Marek Szyprowski <m.szyprowski@samsung.com
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org
Link: https://lore.kernel.org/r/20230510113942.89994-1-jaewon02.kim@samsung.com
Signed-off-by: Mark Brown <broonie@kernel.org
Spi geni driver switches between FIFO and DMA modes based on xfer length.
FIFO mode relies on M_CMD_DONE_EN interrupt for completion while DMA mode
relies on XX_DMA_DONE.
During dynamic switching, if FIFO mode is chosen, FIFO related interrupts
are enabled and DMA related interrupts are disabled. And viceversa.
Chip select shares M_CMD_DONE_EN interrupt with FIFO to check completion.
Now, if a chip select operation is preceded by a DMA xfer, M_CMD_DONE_EN
interrupt would have been disabled and hence it will never receive one
resulting in timeout.
For chip select, in addition to setting the xfer mode to FIFO,
select_mode() to FIFO so that required interrupts are enabled.
Fixes: e5f0dfa78a ("spi: spi-geni-qcom: Add support for SE DMA mode")
Suggested-by: Praveen Talari <quic_ptalari@quicinc.com
Signed-off-by: Vijaya Krishna Nivarthi <quic_vnivarth@quicinc.com
Reviewed-by: Douglas Anderson <dianders@chromium.org
Link: https://lore.kernel.org/r/1683626496-9685-1-git-send-email-quic_vnivarth@quicinc.com
Signed-off-by: Mark Brown <broonie@kernel.org
Merge series from Joy Chakraborty <joychakr@google.com>:
This Patch series adds support for 32 bits per word trasfers using DMA
and some defensive checks around dma controller capabilities.
Merge series from Vijaya Krishna Nivarthi <quic_vnivarth@quicinc.com>:
There are large number of QSPI irqs that fire during boot/init and later
on every suspend/resume.
This could be made faster by doing DMA instead of PIO.
Below is comparison for number of interrupts raised in 2 scenarios...
Boot up and stabilise
Suspend/Resume
Sequence PIO DMA
=======================
Boot-up 69088 19284
S/R 5066 3430
Speed test results...
spi-nor read times in sec after 2 min uptime
============================================
PIO - Iterations-1000, min=3.18, max=3.74, avg=3.53
DMA - Iterations-1000, min=1.21, max=2.28, avg=1.79
spi-nor write times in sec after 2 min uptime
=============================================
PIO - Iterations-1000, min=3.20, max=8.24, avg=3.58
DMA - Iterations-1000, min=1.25, max=5.13, avg=1.82
Further testing performed...
a) multiple entries in sgt (simulated by max_dma_len = 1024)
b) fallback to pio (simulated by dma setup failure)
Merge series from Jaewon Kim <jaewon02.kim@samsung.com>:
Previously, polling mode was supported as quirk for SOC without DMA.
In order to use it more flexibly, it is supported when there is
no dmas property in devicetree, and the issue of using excessive CPU
usage in polling mode is solved by adding sleep during transfer time and
supporting interrupt mode.
Changes in V3.
- Fix patch commit message.
- Change of_find_property() to of_property_present() with code cleanup
- Remove cpu_relax() related patch.
- Changes use_irq variable type to bool
Changes in V2.
- Switched to polling mode if there is no dmas property in devicetree.
- Add cpu_releax() in polling loop
- Add lower limit in IRQ mode
Jaewon Kim (3):
spi: s3c64xx: change polling mode to optional
spi: s3c64xx: add sleep during transfer
spi: s3c64xx: support interrupt based pio mode
drivers/spi/spi-s3c64xx.c | 81 +++++++++++++++++++----
include/linux/platform_data/spi-s3c64xx.h | 1 +
2 files changed, 70 insertions(+), 12 deletions(-)
--
2.17.1
The CS_TOGGLE bit when set is supposed to instruct FW to
toggle CS line between words. The driver with intent of
disabling this behaviour has been unsetting BIT(0). This has
not caused any trouble so far because the original BIT(1)
is untouched and BIT(0) likely wasn't being used.
Correct this to prevent a potential future bug.
Signed-off-by: Vijaya Krishna Nivarthi <quic_vnivarth@quicinc.com
Acked-by: Konrad Dybcio <konrad.dybcio@linaro.org
Fixes: 561de45f72 ("spi: spi-geni-qcom: Add SPI driver support for GENI based QUP")
Reviewed-by: Douglas Anderson <dianders@chromium.org
Link: https://lore.kernel.org/r/1682412128-1913-1-git-send-email-quic_vnivarth@quicinc.com
Signed-off-by: Mark Brown <broonie@kernel.org
Move dw_spi_can_dma() implementation below dw_spi_dma_convert_width()
for handing compile dependency in future patches.
* tested on Baikal-T1 based system with DW SPI-looped back interface
transferring a chunk of data with DFS:8,12,16.
Signed-off-by: Joy Chakraborty <joychakr@google.com
Reviewed-by: Serge Semin <fancer.lancer@gmail.com
Tested-by: Serge Semin <fancer.lancer@gmail.com
Link: https://lore.kernel.org/r/20230427123314.1997152-3-joychakr@google.com
Signed-off-by: Mark Brown <broonie@kernel.org
Add Support for AxSize = 4 bytes configuration from dw dma driver if
n_bytes i.e. number of bytes per write to fifo is 4.
Number of bytes written to fifo per write is depended on the bits/word
configuration being used which the DW core driver translates to n_bytes.
Hence, for bits per word values between 17 and 32 n_bytes should be
equal to 4.
* tested on Baikal-T1 based system with DW SPI-looped back interface
transferring a chunk of data with DFS:8,12,16.
Signed-off-by: Joy Chakraborty <joychakr@google.com
Reviewed-by: Serge Semin <fancer.lancer@gmail.com
Tested-by: Serge Semin <fancer.lancer@gmail.com
Link: https://lore.kernel.org/r/20230427123314.1997152-2-joychakr@google.com
Signed-off-by: Mark Brown <broonie@kernel.org
Support interrupt based pio mode to optimize cpu usage.
When transmitting data size is larget than 32 bytes, operates with
interrupt based pio mode.
By using the FIFORDY INT, an interrupt can be triggered when
the desired size of data has been received. Using this, we can support
interrupt based pio mode.
Signed-off-by: Jaewon Kim <jaewon02.kim@samsung.com
Link: https://lore.kernel.org/r/20230502062813.112434-4-jaewon02.kim@samsung.com
Signed-off-by: Mark Brown <broonie@kernel.org
In polling mode, the status register is continuously read to check data
transfer completion. It can cause excessive CPU usage.
To reduce this, we can calculate the transfer time and put the sleep during
transfer.
When test on ExynosAuto9 SADK board, throughput remained the same, but
100% CPU utilization decreased to 40%.
Signed-off-by: Jaewon Kim <jaewon02.kim@samsung.com
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org
Link: https://lore.kernel.org/r/20230502062813.112434-3-jaewon02.kim@samsung.com
Signed-off-by: Mark Brown <broonie@kernel.org
Previously, Polling mode was supported as quirk for SOC without DMA.
To provide more flexible support for polling mode, it changed to polling
mode when the 'dmas' property is not present in the devicetree, rather than
using a quirk.
Signed-off-by: Jaewon Kim <jaewon02.kim@samsung.com
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org
Link: https://lore.kernel.org/r/20230502062813.112434-2-jaewon02.kim@samsung.com
Signed-off-by: Mark Brown <broonie@kernel.org
Current driver supports only PIO mode.
HW supports DMA, so add DMA mode support to the driver
for better performance for larger xfers.
Signed-off-by: Vijaya Krishna Nivarthi <quic_vnivarth@quicinc.com
Reviewed-by: Douglas Anderson <dianders@chromium.org
Link: https://lore.kernel.org/r/1682328761-17517-6-git-send-email-quic_vnivarth@quicinc.com
Signed-off-by: Mark Brown <broonie@kernel.org
