Commit Graph

5 Commits

Author SHA1 Message Date
Antoine Ténart
bd13251f71 reset: add the Berlin reset controller driver
Add a reset controller for Marvell Berlin SoCs which is used by the
USB PHYs drivers (for now).

Signed-off-by: Antoine Ténart <antoine.tenart@free-electrons.com>
Acked-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
2014-10-20 16:51:56 +02:00
Steffen Trumtrar
a39a493932 reset: add driver for socfpga
Add a reset-controller driver for the socfpga platform.
The reset-controller has four banks with up to 32 entries all encapsulated in
one module block.

Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Acked-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
---

Notes:
    Changes since v2:
        - remove superfluous ret in probe function
        - add Acked-by

    Changes since v1:
        - use BITS_PER_LONG everywhere instead of MAX_BANK_WIDTH
        - print pdev->dev.of_node->full_name on error
        - use proper IS_ERR/PTR_ERR
2014-04-25 17:40:08 -05:00
Stephen Gallimore
e5d76075d9 drivers: reset: STi SoC system configuration reset controller support
This patch adds a reset controller implementation for STMicroelectronics
STi family SoCs; it allows a group of related reset like controls found
in multiple system configuration registers to be represented by a single
controller device. System configuration registers are accessed through
the regmap framework and the mfd/syscon driver.

The implementation optionally supports waiting for the reset action to
be acknowledged in a separate status register and supports both
active high and active low reset lines. These properties are common across
all the reset channels in a specific reset controller instance, hence
all channels in a paritcular controller are expected to behave in the
same way.

Signed-off-by: Stephen Gallimore <stephen.gallimore@st.com>
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@st.com>
Acked-by: Philipp Zabel <p.zabel@pengutronix.de>
2014-03-11 10:47:23 +00:00
Maxime Ripard
8f1ae77f46 reset: Add Allwinner SoCs Reset Controller Driver
The Allwinner A31 and most of the other Allwinner SoCs have an IP
maintaining a few other IPs in the SoC in reset by default. Among these
IPs are the A31's High Speed Timers, hence why we can't use the regular
driver construct in every cases, and need to call the registering
function directly during machine initialisation.

Apart from this, the implementation is fairly straightforward, and could
easily be moved to a generic MMIO-based reset controller driver if the
need ever arise.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Philipp Zabel <p.zabel@pengutronix.de>
2013-11-22 21:20:36 +01:00
Philipp Zabel
61fc413176 reset: Add reset controller API
This adds a simple API for devices to request being reset
by separate reset controller hardware and implements the
reset signal device tree binding.

Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Shawn Guo <shawn.guo@linaro.org>
Reviewed-by: Marek Vasut <marex@denx.de>
Reviewed-by: Pavel Machek <pavel@ucw.cz>
2013-04-12 10:26:23 +02:00