MediaTek UFS host now supports 2 lanes. Modify the lane count to 2.
This modification shall not impact old 1-lane host because
PA_CONNECTEDRXDATALANES and PA_CONNECTEDTXDATALANES will limit the target
lanes properly during power mode change. So we could relax the limitation
in ufs_dev_params.
Link: https://lore.kernel.org/r/20200819084340.7021-1-stanley.chu@mediatek.com
Reviewed-by: Stanley Chu <stanley.chu@mediatek.com>
Reviewed-by: Avri Altman <avri.altman@wdc.com>
Signed-off-by: Andy Teng <andy.teng@mediatek.com>
Signed-off-by: Stanley Chu <stanley.chu@mediatek.com>
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
Add inline encryption support to ufs-mediatek.
The standards-compliant parts, such as querying the crypto capabilities and
enabling crypto for individual UFS requests, are already handled by
ufshcd-crypto.c, which itself is wired into the blk-crypto framework.
However MediaTek UFS host requires a vendor-specific hce_enable operation
to allow crypto-related registers being accessed normally in kernel. After
this step, MediaTek UFS host can work as standard-compliant host for
inline-encryption related functions.
Link: https://lore.kernel.org/r/20200712003226.7593-1-stanley.chu@mediatek.com
Reviewed-by: Avri Altman <avri.altman@wdc.com>
Signed-off-by: Stanley Chu <stanley.chu@mediatek.com>
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
MediaTek UFS clocks are separated to two parts and controlled by different
modules: ufs-mediatek and phy-ufs-mediatek.
If both Auto-Hibern8 and clk-gating feature are enabled, mphy power control
is not balanced thus unbalanced control also happens to the clocks probed
by phy-ufs-mediatek module.
Fix this issue by:
- Promise usage of phy_power_on/off balanced
- Remove phy_power_on/off control in suspend/resume vops since both can be
handled in setup_clock vops only
Link: https://lore.kernel.org/r/20200601104646.15436-5-stanley.chu@mediatek.com
Reviewed-by: Peter Wang <peter.wang@mediatek.com>
Signed-off-by: Stanley Chu <stanley.chu@mediatek.com>
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
Currently ref-clk control timeout is implemented by jiffies. However
jiffies is not accurate enough thus "false timeout" may happen.
Use more accurate delay mechanism instead, i.e. ktime.
Link: https://lore.kernel.org/r/20200601104646.15436-2-stanley.chu@mediatek.com
Reviewed-by: Andy Teng <andy.teng@mediatek.com>
Reviewed-by: Avri Altman <avri.altman@wdc.com>
Signed-off-by: Stanley Chu <stanley.chu@mediatek.com>
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
MediaTek platform and UFS controller can dynamically customize the delay
for host enabling according to different scenarios.
For example, if UniPro enters lower-power mode, such delay can be
minimized, otherwise longer delay shall be expected.
Link: https://lore.kernel.org/r/20200318104016.28049-8-stanley.chu@mediatek.com
Reviewed-by: Avri Altman <avri.altman@wdc.com>
Signed-off-by: Stanley Chu <stanley.chu@mediatek.com>
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
Some delays may be required either after gating or before ungating
reference clock for device according to vendor requirements.
Note that in UFS 3.0, the delay time after gating reference
clock can be defined by attribute bRefClkGatingWaitTime. Use the
formal value instead if it can be queried from device.
Link: https://lore.kernel.org/r/20200220134848.8807-2-stanley.chu@mediatek.com
Reviewed-by: Bean Huo <beanhuo@micron.com>
Signed-off-by: Stanley Chu <stanley.chu@mediatek.com>
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
In current UFS driver design, hba->uic_link_state will not be changed after
link enters Hibern8 state by Auto-Hibern8 mechanism. In this case,
reference clock gating will be skipped unless special handling is
implemented in vendor's callbacks.
Support reference clock gating during Auto-Hibern8 period in MediaTek
Chipsets: If link state is already in Hibern8 while Auto-Hibern8 feature is
enabled, gate reference clock in setup_clocks callback.
Link: https://lore.kernel.org/r/20200129105251.12466-5-stanley.chu@mediatek.com
Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com>
Reviewed-by: Bean Huo <beanhuo@micron.com>
Signed-off-by: Stanley Chu <stanley.chu@mediatek.com>
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
Add dbg_register_dump variant vendor implementation in MediaTek UFS driver.
Link: https://lore.kernel.org/r/20200117035108.19699-2-stanley.chu@mediatek.com
Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com>
Signed-off-by: Stanley Chu <stanley.chu@mediatek.com>
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
Introduce reference clock control in MediaTek Chipset in order to disable
it if it is not necessary by UFS device to save system power.
Currently reference clock can be disabled during system suspend, runtime
suspend and clock-gating after link enters hibernate state.
Cc: Alim Akhtar <alim.akhtar@samsung.com>
Cc: Avri Altman <avri.altman@wdc.com>
Cc: Bart Van Assche <bvanassche@acm.org>
Cc: Bean Huo <beanhuo@micron.com>
Cc: Can Guo <cang@codeaurora.org>
Cc: Florian Fainelli <f.fainelli@gmail.com>
Cc: Matthias Brugger <matthias.bgg@gmail.com>
Link: https://lore.kernel.org/r/1577683950-1702-4-git-send-email-stanley.chu@mediatek.com
Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com>
Signed-off-by: Stanley Chu <stanley.chu@mediatek.com>
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
This patch adds UFS support for MediaTek SoC chips.
Signed-off-by: Stanley Chu <stanley.chu@mediatek.com>
Reviewed-by: Avri Altman <avri.altman@wdc.com>
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
