When flipping the polarity will be generated interrupt under certain
circumstances, but GPIO external signal has not changed.
Then, mask the interrupt before polarity setting, and clear the
unexpected interrupt after trigger type setting completed.
Remove mtk_eint_flip_edge: because mtk_eint_unmask already calls it.
Signed-off-by: Hailong Fan <hailong.fan@mediatek.com>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
Link: https://lore.kernel.org/r/20210125041753.2214-1-hailong.fan@mediatek.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
SAMA7G5 supports slew rate configuration. Adapt the driver for this.
For output switching frequencies lower than 50MHz the slew rate needs to
be enabled. Since most of the pins on SAMA7G5 fall into this category
enabled the slew rate by default.
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Acked-by: Ludovic Desroches <ludovic.desroches@microchip.com>
Link: https://lore.kernel.org/r/1611747945-29960-3-git-send-email-claudiu.beznea@microchip.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
I happened to apply the v1 of the patch restriction the
selection to ARM or ARM64, sorry for my sloppiness.
Fixing up the mistake as I can't back the patch out now.
Fixes: 5784921f7b ("pinctrl: actions: Add the platform dependency to drivers")
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
pcs_add_function() fails to set the function name in struct pcs_function
when adding a new function. As a result this line in pcs_set_mux():
dev_dbg(pcs->dev, "enabling %s function%i\n",
func->name, fselector);
prints "(null)" for the function:
pinctrl-single 44e10800.pinmux: enabling (null) function0
pinctrl-single 44e10800.pinmux: enabling (null) function1
pinctrl-single 44e10800.pinmux: enabling (null) function2
pinctrl-single 44e10800.pinmux: enabling (null) function3
With this fix, the output is now:
pinctrl-single 44e10800.pinmux: enabling pinmux-uart0-pins function0
pinctrl-single 44e10800.pinmux: enabling pinmux-mmc0-pins function1
pinctrl-single 44e10800.pinmux: enabling pinmux-i2c0-pins function2
pinctrl-single 44e10800.pinmux: enabling pinmux-mmc0-pins function3
Cc: Jason Kridner <jkridner@beagleboard.org>
Cc: Robert Nelson <robertcnelson@beagleboard.org>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Tony Lindgren <tony@atomide.com>
Signed-off-by: Drew Fustini <drew@beagleboard.org>
Acked-by: Tony Lindgren <tony@atomide.com>
Link: https://lore.kernel.org/r/20210125203542.51513-1-drew@beagleboard.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Add pinctrl driver for the sc8180x TLMM block.
A noteworthy difference from previous TLMM blocks is that the registers
for GPIO 177 through 189 are for some reason offset from the typical
layout. Other than that the driver is same old...
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20210126042650.1725176-3-bjorn.andersson@linaro.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This adds pincontrol driver for tlmm block found in SM8350 SoC
This patch is based on initial code downstream by Raghavendra.
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Link: https://lore.kernel.org/r/20210205140132.274242-3-vkoul@kernel.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Convert spin_[lock|unlock] functions of pin bank to
raw_spinlock to support preempt-rt for pinctrl-s3c64xx. Below patch
converted spinlock_t to raw_spinlock_t but it didn't convert the
s3c64xx's spinlock.
Fixes: 1f306ecbe0 ("pinctrl: samsung: use raw_spinlock for locking")
Cc: Tomasz Figa <tomasz.figa@gmail.com>
Cc: Krzysztof Kozlowski <krzk@kernel.org>
Cc: Sylwester Nawrocki <s.nawrocki@samsung.com>
Cc: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Chanho Park <chanho61.park@samsung.com>
Link: https://lore.kernel.org/r/20210127001631.91209-1-chanho61.park@samsung.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* Enable pin control on Intel Alder Lake-P
* Traverse through capabilities, convert them to features for the future use
The following is an automated git shortlog grouped by driver:
intel:
- Convert capability list to features
- Drop unnecessary check for predefined features
- Split intel_pinctrl_add_padgroups() for better maintenance
tigerlake:
- Add Alder Lake-P ACPI ID
-----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEqaflIX74DDDzMJJtb7wzTHR8rCgFAmAQEgEACgkQb7wzTHR8
rCgJcg/9Hw1Vi6Pe9l+SM7Gt4Cm/aRkYZGdfnDw0e1FgkAfdCmgi/zsBLYNIjiUD
cvjKLYf2JSgtA90dprPZWN0SBLdTpY1Yh88TzwGh23Pt8OnDoBP+JcrK07hH/cJ+
u0aUMd+MFNE+Vi3F1s4ENdABJ+uA9kJRpRzA/JGr2UgtII9N7hO+2iq+stfGNiIf
lonKkq+MgUfXxLYqRdkoIU/l0G+O86tSlMy1vhdOewyin06kL+FirGQgtoQg/WgD
qUXwG3qTZMcwum2q8TDtJioplRR/Vv1o888CdL6KWS25dsZZ13C8k0HNwR04nwFg
pzKqrq0Z0IeDNYNP2ThP6/FQ2L1haK4dHjSVdQsbRzI+lQaRL/OAmMBc5Q2HwwbD
c7XdJIFfB1ptq+gQF5tpZ0gZKbRNYZuperO/RfJuTPU+Vmtzk8aDi4Zu8GkilcaD
JFO5ZX+/6fs/k90TfCNCuoNAEAoKTHjofOh8BXqTtzKT24Sldtchz9YFD7UcvivN
H42hMq98XX1ZrcR0xQPLwfC43g4bRwIsZXInQ8z+BNOVpMEQgopxjqZxLGxTPOlA
rBjivbEYKdCSp+T3MOz+2tQ160jTg9wAO4Rq/KRT0hxVr+ABGSJGRUcQgNXdvofe
Q73iZqiSFTlGPQr0CAFT78tK8cb2mv9b583SeLTgAcZ/wxZP7NA=
=9BMa
-----END PGP SIGNATURE-----
Merge tag 'intel-pinctrl-v5.12-1' of gitolite.kernel.org:pub/scm/linux/kernel/git/pinctrl/intel into devel
intel-pinctrl for v5.12-1
* Enable pin control on Intel Alder Lake-P
* Traverse through capabilities, convert them to features for the future use
The following is an automated git shortlog grouped by driver:
intel:
- Convert capability list to features
- Drop unnecessary check for predefined features
- Split intel_pinctrl_add_padgroups() for better maintenance
tigerlake:
- Add Alder Lake-P ACPI ID
Add the function selector to the pinmux-functions debugfs output. This
is an integer which is the index into the pinmux function tree. It will
make it easier to correlate function name to function selector without
having to count the lines in the output.
Example output of "pinmux-functions":
function 0: pinmux-uart0-pins, groups = [ pinmux-uart0-pins ]
function 1: pinmux-uart1-pins, groups = [ pinmux-uart1-pins ]
function 2: pinmux-uart2-pins, groups = [ pinmux-uart2-pins ]
function 3: pinmux-mmc0-pins, groups = [ pinmux-mmc0-pins ]
function 3: pinmux-mmc1-pins, groups = [ pinmux-mmc1-pins ]
function 5: pinmux-i2c0-pins, groups = [ pinmux-i2c0-pins ]
function 6: pinmux-i2c1-pins, groups = [ pinmux-i2c1-pins ]
function 7: pinmux-i2c2-pins, groups = [ pinmux-i2c2-pins ]
function 8: pinmux-pwm0-pins, groups = [ pinmux-pwm0-pins ]
function 9: pinmux-pwm1-pins, groups = [ pinmux-pwm1-pins ]
function 10: pinmux-adc-pins, groups = [ pinmux-adc-pins ]
Cc: Jason Kridner <jkridner@beagleboard.org>
Cc: Robert Nelson <robertcnelson@beagleboard.org>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Andy Shevchenko <andy.shevchenko@gmail.com>
Cc: Alexandre Belloni <alexandre.belloni@bootlin.com>
Signed-off-by: Drew Fustini <drew@beagleboard.org>
Link: https://lore.kernel.org/r/20210123202212.528046-1-drew@beagleboard.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This patch converts spin_[lock|unlock] functions of pin bank to
raw_spinlock to support preempt-rt. This can avoid BUG() assertion when
irqchip callbacks are triggerred. Spinlocks can be converted rt_mutex
which is preemptible when we apply preempt-rt patches.
According to "Documentation/driver-api/gpio/driver.rst",
"Realtime considerations: a realtime compliant GPIO driver should not
use spinlock_t or any sleepable APIs (like PM runtime) as part of its
irqchip implementation.
- spinlock_t should be replaced with raw_spinlock_t.[1]
"
Cc: Tomasz Figa <tomasz.figa@gmail.com>
Cc: Krzysztof Kozlowski <krzk@kernel.org>
Cc: Sylwester Nawrocki <s.nawrocki@samsung.com>
Cc: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Chanho Park <chanho61.park@samsung.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Link: https://lore.kernel.org/r/20210121030009.25673-1-chanho61.park@samsung.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The Actions Semi pinctrl drivers are a mix of both ARM32 and ARM64
platforms. So let's add the correct platform dependency to avoid them
being selected on the other.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Link: https://lore.kernel.org/r/20210121062547.27173-1-manivannan.sadhasivam@linaro.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
There are only two pins left now, used to connect to the PMIC via I2C.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <mripard@kernel.org>
Reviewed-by: Jernej Skrabec <jernej.skrabec@siol.net>
Link: https://lore.kernel.org/r/20210118020848.11721-6-andre.przywara@arm.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Port A is used for an internal connection to some analogue circuitry
which looks like an AC200 IP (as in the H6), though this is not
mentioned in the manual.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <mripard@kernel.org>
Link: https://lore.kernel.org/r/20210118020848.11721-5-andre.przywara@arm.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
- Add otg function and otg-vbus group.
- Add lcd-8bit, lcd-16bit, lcd-18bit, lcd-generic and lcd-special
groups. Change the lcd-24bit group so that it only selects the pins
that aren't in the lcd-18bit and lcd-generic groups (which breaks
Device Tree in theory, but there is none out there for any JZ4760
based board, yet). Remove the lcd-no-pins group which is just useless.
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Link: https://lore.kernel.org/r/20210120110722.20133-1-paul@crapouillou.net
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The ST-Ericsson U300 platform is getting removed, so this driver is no
longer needed.
Cc: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Link: https://lore.kernel.org/r/20210120132045.2127659-6-arnd@kernel.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The ST-Ericsson U300 platform is getting removed, so this driver is no
longer needed.
Cc: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Link: https://lore.kernel.org/r/20210120132045.2127659-5-arnd@kernel.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The CSR SiRF prima2/atlas platforms are getting removed, so this driver
is no longer needed.
Cc: Barry Song <baohua@kernel.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Barry Song <baohua@kernel.org>
Link: https://lore.kernel.org/r/20210120132045.2127659-4-arnd@kernel.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The zte zx platform is getting removed, so this driver is no
longer needed.
Cc: Jun Nie <jun.nie@linaro.org>
Cc: Shawn Guo <shawnguo@kernel.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Link: https://lore.kernel.org/r/20210120132045.2127659-3-arnd@kernel.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Tested on a JZ4740 system (ARCH=mips make qi_lb60_defconfig), this saves
about 14 KiB, by allowing the compiler to garbage-collect all the
functions and tables that correspond to SoCs that were disabled in the
config.
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Link: https://lore.kernel.org/r/20201213235447.138271-2-paul@crapouillou.net
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
- Restrict debug runtime-checks to Renesas platforms,
- Initial support for the R-Car V3U SoC.
-----BEGIN PGP SIGNATURE-----
iHUEABYIAB0WIQQ9qaHoIs/1I4cXmEiKwlD9ZEnxcAUCYAFgRQAKCRCKwlD9ZEnx
cEWIAP40TrUerqfnQgJ7iNYLh9WfSk48w9Gxzm92E7FanXaJBAD/dmkieXwQBBig
zKNuoWL2ZlK7O5MMkzpNnhLNS95SEQs=
=vIxg
-----END PGP SIGNATURE-----
Merge tag 'renesas-pinctrl-for-v5.12-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel
pinctrl: renesas: Updates for v5.12
- Restrict debug runtime-checks to Renesas platforms,
- Initial support for the R-Car V3U SoC.
In Linux, if a driver does disable_irq() and later does enable_irq()
on its interrupt, I believe it's expecting these properties:
* If an interrupt was pending when the driver disabled then it will
still be pending after the driver re-enables.
* If an edge-triggered interrupt comes in while an interrupt is
disabled it should assert when the interrupt is re-enabled.
If you think that the above sounds a lot like the disable_irq() and
enable_irq() are supposed to be masking/unmasking the interrupt
instead of disabling/enabling it then you've made an astute
observation. Specifically when talking about interrupts, "mask"
usually means to stop posting interrupts but keep tracking them and
"disable" means to fully shut off interrupt detection. It's
unfortunate that this is so confusing, but presumably this is all the
way it is for historical reasons.
Perhaps more confusing than the above is that, even though clients of
IRQs themselves don't have a way to request mask/unmask
vs. disable/enable calls, IRQ chips themselves can implement both.
...and yet more confusing is that if an IRQ chip implements
disable/enable then they will be called when a client driver calls
disable_irq() / enable_irq().
It does feel like some of the above could be cleared up. However,
without any other core interrupt changes it should be clear that when
an IRQ chip gets a request to "disable" an IRQ that it has to treat it
like a mask of that IRQ.
In any case, after that long interlude you can see that the "unmask
and clear" can break things. Maulik tried to fix it so that we no
longer did "unmask and clear" in commit 71266d9d39 ("pinctrl: qcom:
Move clearing pending IRQ to .irq_request_resources callback"), but it
only handled the PDC case and it had problems (it caused
sc7180-trogdor devices to fail to suspend). Let's fix.
>From my understanding the source of the phantom interrupt in the
were these two things:
1. One that could have been introduced in msm_gpio_irq_set_type()
(only for the non-PDC case).
2. Edges could have been detected when a GPIO was muxed away.
Fixing case #1 is easy. We can just add a clear in
msm_gpio_irq_set_type().
Fixing case #2 is harder. Let's use a concrete example. In
sc7180-trogdor.dtsi we configure the uart3 to have two pinctrl states,
sleep and default, and mux between the two during runtime PM and
system suspend (see geni_se_resources_{on,off}() for more
details). The difference between the sleep and default state is that
the RX pin is muxed to a GPIO during sleep and muxed to the UART
otherwise.
As per Qualcomm, when we mux the pin over to the UART function the PDC
(or the non-PDC interrupt detection logic) is still watching it /
latching edges. These edges don't cause interrupts because the
current code masks the interrupt unless we're entering suspend.
However, as soon as we enter suspend we unmask the interrupt and it's
counted as a wakeup.
Let's deal with the problem like this:
* When we mux away, we'll mask our interrupt. This isn't necessary in
the above case since the client already masked us, but it's a good
idea in general.
* When we mux back will clear any interrupts and unmask.
Fixes: 4b7618fdc7 ("pinctrl: qcom: Add irq_enable callback for msm gpio")
Fixes: 71266d9d39 ("pinctrl: qcom: Move clearing pending IRQ to .irq_request_resources callback")
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Maulik Shah <mkshah@codeaurora.org>
Tested-by: Maulik Shah <mkshah@codeaurora.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Link: https://lore.kernel.org/r/20210114191601.v7.4.I7cf3019783720feb57b958c95c2b684940264cd1@changeid
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
In commit 4b7618fdc7 ("pinctrl: qcom: Add irq_enable callback for
msm gpio") we tried to Ack interrupts during unmask. However, that
patch forgot to check "intr_ack_high" so, presumably, it only worked
for a certain subset of SoCs.
Let's add a small accessor so we don't need to open-code the logic in
both places.
This was found by code inspection. I don't have any access to the
hardware in question nor software that needs the Ack during unmask.
Fixes: 4b7618fdc7 ("pinctrl: qcom: Add irq_enable callback for msm gpio")
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Maulik Shah <mkshah@codeaurora.org>
Tested-by: Maulik Shah <mkshah@codeaurora.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20210114191601.v7.3.I32d0f4e174d45363b49ab611a13c3da8f1e87d0f@changeid
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
When the Qualcomm pinctrl driver wants to Ack an interrupt, it does a
read-modify-write on the interrupt status register. On some SoCs it
makes sure that the status bit is 1 to "Ack" and on others it makes
sure that the bit is 0 to "Ack". Presumably the first type of
interrupt controller is a "write 1 to clear" type register and the
second just let you directly set the interrupt status register.
As far as I can tell from scanning structure definitions, the
interrupt status bit is always in a register by itself. Thus with
both types of interrupt controllers it is safe to "Ack" interrupts
without doing a read-modify-write. We can do a simple write.
It should be noted that if the interrupt status bit _was_ ever in a
register with other things (like maybe status bits for other GPIOs):
a) For "write 1 clear" type controllers then read-modify-write would
be totally wrong because we'd accidentally end up clearing
interrupts we weren't looking at.
b) For "direct set" type controllers then read-modify-write would also
be wrong because someone setting one of the other bits in the
register might accidentally clear (or set) our interrupt.
I say this simply to show that the current read-modify-write doesn't
provide any sort of "future proofing" of the code. In fact (for
"write 1 clear" controllers) the new code is slightly more "future
proof" since it would allow more than one interrupt status bits to
share a register.
NOTE: this code fixes no bugs--it simply avoids an extra register
read.
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Maulik Shah <mkshah@codeaurora.org>
Tested-by: Maulik Shah <mkshah@codeaurora.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20210114191601.v7.2.I3635de080604e1feda770591c5563bd6e63dd39d@changeid
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
There's currently a comment in the code saying function 0 is GPIO.
Instead of hardcoding it, let's add a member where an SoC can specify
it. No known SoCs use a number other than 0, but this just makes the
code clearer. NOTE: no SoC code needs to be updated since we can rely
on zero-initialization.
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Reviewed-by: Maulik Shah <mkshah@codeaurora.org>
Tested-by: Maulik Shah <mkshah@codeaurora.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20210114191601.v7.1.I3ad184e3423d8e479bc3e86f5b393abb1704a1d1@changeid
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Fix the following coccicheck warning:
./drivers/pinctrl/sprd/pinctrl-sprd.c:690:8-23: WARNING: Comparison to
bool
Reported-by: Abaci Robot <abaci@linux.alibaba.com>
Signed-off-by: YANG LI <abaci-bugfix@linux.alibaba.com>
Reviewed-by: Baolin Wang <baolin.wang7@gmail.com>
Link: https://lore.kernel.org/r/1610440080-68600-1-git-send-email-abaci-bugfix@linux.alibaba.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Add pins, groups and functions for the 16-Bit Timer Pulse Unit outputs
on the R-Car R8A779A0 (V3U) SoC.
Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu>
Link: https://lore.kernel.org/r/20210112165929.31002-13-uli+renesas@fpond.eu
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Add pins, groups, and function for the Interrupt Controller for External
Devices (INTC-EX) on the R-Car R8A779A0 (V3U) SoC.
Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu>
Link: https://lore.kernel.org/r/20210112165929.31002-7-uli+renesas@fpond.eu
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This patch adds HSCIF0-3 pins, groups and functions to the R8A779A0
(V3U) SoC.
Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu>
Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/20210112165929.31002-6-uli+renesas@fpond.eu
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This patch adds groups and function for AVB PHY, LINK, MAGIC, RGMII and
PTP pins for the R8A779A0 (V3U) SoC.
Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu>
Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/20210112165929.31002-3-uli+renesas@fpond.eu
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This patch adds I2C0-6 pins, groups and functions to the R8A779A0 (V3U)
SoC.
Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu>
Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/20210112165929.31002-2-uli+renesas@fpond.eu
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This patch adds SCIF0, 1, 3 and 4 pins, groups and functions for the
R8A779A0 (V3U) SoC.
Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu>
Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/20210112165912.30876-6-uli+renesas@fpond.eu
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This patch adds initial pinctrl support for the R8A779A0 (V3U) SoC,
including bias, drive strength and voltage control.
Based on patch by LUU HOAI <hoai.luu.ub@renesas.com>.
Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu>
Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/20210112165912.30876-5-uli+renesas@fpond.eu
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This patch adds config macros describing the voltage levels available on
a pin. The current default (3.3V/1.8V) maps to zero to avoid having to
change existing PFC implementations.
Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu>
Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/20210112165912.30876-3-uli+renesas@fpond.eu
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
The V3U SoC has several unlock registers, one per register group. They
reside at offset zero in each 0x200 bytes-sized block.
To avoid adding yet another table to the PFC implementation, this
patch adds the option to specify an address mask instead of the fixed
address in sh_pfc_soc_info::unlock_reg.
Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu>
Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/20210112165912.30876-2-uli+renesas@fpond.eu
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
When DEBUG is defined (e.g. if CONFIG_DEBUG_PINCTRL=y), the Renesas pin
control driver runs sanity checks against the pin control tables. This
may cause lots of output on the console, and can be annoying in ARM
multi-platform kernels. Fix this by only running the checks when
running on SuperH, or on a DT platform supported by the Renesas pin
controller driver.
Suggested-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Arnd Bergmann <arnd@arndb.de>
Link: https://lore.kernel.org/r/20210111165013.496897-1-geert+renesas@glider.be
Intel Alder Lake-P PCH has the same GPIO hardware than Tiger Lake-LP
PCH but the ACPI ID is different. Add this new ACPI ID to the list of
supported devices.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Communities can have features provided in the capability list.
Traverse the list and convert to respective features.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
None of the drivers is overriding features. Remove unnecessary check.
While here, rename rev to value to make easier further development.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Currently the intel_pinctrl_add_padgroups() is twisted a bit due to
a different nature of the pin control hardware implementations. Thus,
its maintenance is a bit hard. Besides that some pieces of code
are run on all hardware and make this code slightly inefficient,
and moreover, validation for one case is done in a wrong time in a flow
which makes it even slower.
Split intel_pinctrl_add_padgroups() to two functions, one per hardware
implementation, for better maintenance and readability.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
As there is an RSB controller in the H6 SoC, there should be some pin
configuration for it. While no such configuration is documented, the
"s_i2c" pins are suspiciously on the "alternate" function 3, with no
primary function 2 given. This suggests the primary function for these
pins is actually RSB, and that is indeed the case.
Add the "s_rsb" pin functions so the RSB controller can be used.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <mripard@kernel.org>
Link: https://lore.kernel.org/r/20210103100007.32867-3-samuel@sholland.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Some SoCs, eg. mt8183, are using a pinconfig operation bias_set_combo.
The fallback path in mtk_pinconf_adv_pull_set() should also try this
operation.
Fixes: cafe19db77 ("pinctrl: mediatek: Backward compatible to previous Mediatek's bias-pull usage")
Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org>
Acked-by: Sean Wang <sean.wang@kernel.org>
Link: https://lore.kernel.org/r/20201228090425.2130569-1-hsinyi@chromium.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Clang warns:
drivers/pinctrl/nomadik/pinctrl-nomadik.c:952:8: warning: unused
variable 'wake' [-Wunused-variable]
bool wake;
^
1 warning generated.
There were two wake declarations added to nmk_gpio_dbg_show_one when
converting it to use irq_has_action but only one is used within its
scope. Remove the unused one so there is no more warning.
Fixes: f3925032d7 ("pinctrl: nomadik: Use irq_has_action()")
Reported-by: Arnd Bergmann <arnd@arndb.de>
Tested-by: Andrew Halaney <ajhalaney@gmail.com>
Reviewed-by: Andrew Halaney <ajhalaney@gmail.com>
Reported-by: Hulk Robot <hulkci@huawei.com>
Reported-by: Ye Bin <yebin10@huawei.com>
Signed-off-by: Nathan Chancellor <natechancellor@gmail.com>
Link: https://lore.kernel.org/r/20201229204710.1129033-1-natechancellor@gmail.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Remove all empty lines at the end of functions in pinctrl subsystem,
and make the code neat.
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Reviewed-by: Geert Uytterhoeven <geert@linux-m68k.org>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Signed-off-by: Zhaoyu Liu <zackaryliu@yeah.net>
Link: https://lore.kernel.org/r/X98NP6NFK1Afzrgd@manjaro
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The SCU offset for signal PWM8 in group PWM8G0 is wrong, fix it from
SCU414 to SCU4B4.
Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com>
Fixes: 2eda1cdec4 ("pinctrl: aspeed: Add AST2600 pinmux support")
Reviewed-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
Link: https://lore.kernel.org/r/20201217024912.3198-1-billy_tsai@aspeedtech.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Kernel test robot reported the following warning:
'warning: no previous prototype for 'rt2880_pinmux_init''.
This function is the entry point for the platform driver and
it is private to this driver. Hence declare it 'static' which is
the correct thing to do fixing also this warning.
Reported-by: kernel test robot <lkp@intel.com>
Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
Link: https://lore.kernel.org/r/20201228064727.30098-1-sergio.paracuellos@gmail.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Some paths in probe function are returning '-EINVAL'
instead of preserve original code from called functions.
Change them to preserve all of them.
Reported-by: Dan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20201213161721.6514-7-sergio.paracuellos@gmail.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
When '-ENOMEM' is returned there is not need at all to
add custom error messages. Hence delete it.
Reported-by: Dan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20201213161721.6514-6-sergio.paracuellos@gmail.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Memory is being requested to the kernel but there is
a missing check for NULL. Hence, add it.
Reported-by: Dan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20201213161721.6514-5-sergio.paracuellos@gmail.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Double pointer is being used and assigned in a bit dirty way to
assign functions in pinctrl. Instead of doing this just avoid it
and use directly 'p->func' instead.
Reported-by: Dan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20201213161721.6514-3-sergio.paracuellos@gmail.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Now that JZ4760 support has been fixed, it looks wrong to have
JZ4760_GPIO_* registers being written if the SoC is a JZ4770 or later.
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Link: https://lore.kernel.org/r/20201211232810.261565-2-paul@crapouillou.net
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
- JZ4760 and JZ4760B have a similar register layout as the JZ4740, and
don't use the new register layout, which was introduced with the
JZ4770 SoC and not the JZ4760 or JZ4760B SoCs.
- The JZ4740 code path only expected two function modes to be
configurable for each pin, and wouldn't work with more than two. Fix
it for the JZ4760, which has four configurable function modes.
Fixes: 0257595a5c ("pinctrl: Ingenic: Add pinctrl driver for JZ4760 and JZ4760B.")
Cc: <stable@vger.kernel.org> # 5.3
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Link: https://lore.kernel.org/r/20201211232810.261565-1-paul@crapouillou.net
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
accesses, inefficient and disfunctional code. The goal is to remove the
export of irq_to_desc() to prevent these things from creeping up again.
-----BEGIN PGP SIGNATURE-----
iQJHBAABCgAxFiEEQp8+kY+LLUocC4bMphj1TA10mKEFAl/ifgsTHHRnbHhAbGlu
dXRyb25peC5kZQAKCRCmGPVMDXSYoYm6EACAo8sObkuY3oWLagtGj1KHxon53oGZ
VfDw2LYKM+rgJjDWdiyocyxQU5gtm6loWCrIHjH2adRQ4EisB5r8hfI8NZHxNMyq
8khUi822NRBfFN6SCpO8eW9o95euscNQwCzqi7gV9/U/BAKoDoSEYzS4y0YmJlup
mhoikkrFiBuFXplWI0gbP4ihb8S/to2+kTL6o7eBoJY9+fSXIFR3erZ6f3fLjYZG
CQUUysTywdDhLeDkC9vaesXwgdl2XnaPRwcQqmK8Ez0QYNYpawyILUHLD75cIHDu
bHdK2ZoDv/wtad/3BoGTK3+wChz20a/4/IAnBIUVgmnSLsPtW8zNEOPWNNc0aGg+
rtafi5bvJ1lMoSZhkjLWQDOGU6vFaXl9NkC2fpF+dg1skFMT2CyLC8LD/ekmocon
zHAPBva9j3m2A80hI3dUH9azo/IOl1GHG8ccM6SCxY3S/9vWSQChNhQDLe25xBEO
VtKZS7DYFCRiL8mIy9GgwZWof8Vy2iMua2ML+W9a3mC9u3CqSLbCFmLMT/dDoXl1
oHnMdAHk1DRatA8pJAz83C75RxbAS2riGEqtqLEQ6OaNXn6h0oXCanJX9jdKYDBh
z6ijWayPSRMVktN6FDINsVNFe95N4GwYcGPfagIMqyMMhmJDic6apEzEo7iA76lk
cko28MDqTIK4UQ==
=BXv+
-----END PGP SIGNATURE-----
Merge tag 'irq-core-2020-12-23' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull irq updates from Thomas Gleixner:
"This is the second attempt after the first one failed miserably and
got zapped to unblock the rest of the interrupt related patches.
A treewide cleanup of interrupt descriptor (ab)use with all sorts of
racy accesses, inefficient and disfunctional code. The goal is to
remove the export of irq_to_desc() to prevent these things from
creeping up again"
* tag 'irq-core-2020-12-23' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (30 commits)
genirq: Restrict export of irq_to_desc()
xen/events: Implement irq distribution
xen/events: Reduce irq_info:: Spurious_cnt storage size
xen/events: Only force affinity mask for percpu interrupts
xen/events: Use immediate affinity setting
xen/events: Remove disfunct affinity spreading
xen/events: Remove unused bind_evtchn_to_irq_lateeoi()
net/mlx5: Use effective interrupt affinity
net/mlx5: Replace irq_to_desc() abuse
net/mlx4: Use effective interrupt affinity
net/mlx4: Replace irq_to_desc() abuse
PCI: mobiveil: Use irq_data_get_irq_chip_data()
PCI: xilinx-nwl: Use irq_data_get_irq_chip_data()
NTB/msi: Use irq_has_action()
mfd: ab8500-debugfs: Remove the racy fiddling with irq_desc
pinctrl: nomadik: Use irq_has_action()
drm/i915/pmu: Replace open coded kstat_irqs() copy
drm/i915/lpe_audio: Remove pointless irq_to_desc() usage
s390/irq: Use irq_desc_kstat_cpu() in show_msi_interrupt()
parisc/irq: Use irq_desc_kstat_cpu() in show_interrupts()
...
New drivers:
- New driver for the Microchip Serial GPIO "SGPIO".
- Qualcomm SM8250 LPASS (Low Power Audio Subsystem) GPIO driver.
New subdrivers:
- Intel Lakefield subdriver.
- Intel Elkhart Lake subdriver.
- Intel Alder Lake-S subdriver.
- Qualcomm MSM8953 subdriver.
- Qualcomm SDX55 subdriver.
- Qualcomm SDX55 PMIC subdriver.
- Ocelot Luton SoC subdriver.
- Ocelot Serval SoC subdriver.
Modularization:
- The Meson driver can now be built as modules.
- The Qualcomm driver(s) can now be built as modules.
Incremental improvements:
- The Intel driver now supports pin configuration for GPIO-related
configurations.
- A bunch of Renesas PFC drivers have been augmented with support
for QSPI pins, groups and functions.
- Non-critical fixes to the irq handling in the Allwinner Sunxi
driver.
-----BEGIN PGP SIGNATURE-----
iQIzBAABCAAdFiEElDRnuGcz/wPCXQWMQRCzN7AZXXMFAl/ab9AACgkQQRCzN7AZ
XXOp5w/7B3JTngCneTa8jBG8rPv94zWMpnqvXBPhK1AZPB53IR48F2ssJMIhwJsj
4QRVjPhnrowqEZjOxr5Ia+pjnQvPL5JP8F/xKiZf5BpS6ccvQQFKdUcDHYzllffr
davHSReb1YIDSST8M/iO9Iqjl2r6/5wLg0OQR26CpDhJc29I93xQA08OuLhqa33v
SibmlCeizScn39gCcwZmfrdvJMPYcUE7zE1v38LgDAp9vt2dsdwAUQ6n8GBQYJF9
NgBA4LwLYlbVHEdhd/I8mNmAbKSpeHxFgKSEWyAaqYRDZkBmsHAEiliWVcnnBmW3
kH76FC+jMHW5dDII8vMAKB5c1Col/7GM4722+NnolPO9vTs93hT0aNy3l5Eh/nWN
DUIZOqvMW4c5M5XZ8prKuTdBfCc3jC3BKiaTKQm/wJMY4SQpTjerB4jnWqRrzTus
tlndz8bezQxwKkx8BAhLc5pE1zQEn5ZznLXqy62RMwd6ymdtOg4ZALQ9nyj2luaP
cGoODMHNHA7BuaZ+dcIoikElCdeSiTNEfO53/UQiVi8BOx0zNT6ul9VlIgC+Utsk
DVYAExg+yF5qw+2xhJxBoK4DqqVSe7xTbqrcY1oLdnWhfz8yGkHh91ONos+9u1sY
2vnjNW4BIfSgEApbZIb7KRS0VCKXh4BzdI9+W9uKhsn6JIYyo1g=
=e5sV
-----END PGP SIGNATURE-----
Merge tag 'pinctrl-v5.11-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
Pull pin control updates from Linus Walleij:
"This is the bulk of pin control changes for the v5.11 kernel.
Drivers, drivers and drivers. Not a single core change.
Some new stuff, especially a bunch of new Intel, Qualcomm and Ocelot
SoCs.
As part of the modularization attempt, I applied one patch affecting
the firmware subsystem as a functional (not syntactic/semantic)
dependency and then it blew up in our face, so I had to revert it,
bummer. It will come in later, through that subsystem, I guess.
New drivers:
- New driver for the Microchip Serial GPIO "SGPIO".
- Qualcomm SM8250 LPASS (Low Power Audio Subsystem) GPIO driver.
New subdrivers:
- Intel Lakefield subdriver.
- Intel Elkhart Lake subdriver.
- Intel Alder Lake-S subdriver.
- Qualcomm MSM8953 subdriver.
- Qualcomm SDX55 subdriver.
- Qualcomm SDX55 PMIC subdriver.
- Ocelot Luton SoC subdriver.
- Ocelot Serval SoC subdriver.
Modularization:
- The Meson driver can now be built as modules.
- The Qualcomm driver(s) can now be built as modules.
Incremental improvements:
- The Intel driver now supports pin configuration for GPIO-related
configurations.
- A bunch of Renesas PFC drivers have been augmented with support for
QSPI pins, groups and functions.
- Non-critical fixes to the irq handling in the Allwinner Sunxi
driver"
* tag 'pinctrl-v5.11-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (80 commits)
pinctrl/spear: simplify the return expression of spear300_pinctrl_probe()
pinctrl: mediatek: simplify the return expression of mtk_pinconf_bias_disable_set_rev1()
dt-bindings: pinctrl: pinctrl-microchip-sgpio: Add irq support
pinctrl: pinctrl-microchip-sgpio: Add irq support (for sparx5)
pinctrl: qcom: Add sm8250 lpass lpi pinctrl driver
dt-bindings: pinctrl: qcom: Add sm8250 lpass lpi pinctrl bindings
pinctrl: qcom-pmic-gpio: Add support for pmx55
dt-bindings: pinctrl: qcom-pmic-gpio: Add pmx55 support
pinctrl: pinctrl-microchip-sgpio: Mark some symbols with static keyword
pinctrl: at91-pio4: Make PINCTRL_AT91PIO4 depend on HAS_IOMEM to fix build error
pinctrl: mtk: Fix low level output voltage issue
pinctrl: falcon: add missing put_device() call in pinctrl_falcon_probe()
pinctrl: actions: pinctrl-s500: Constify s500_padinfo[]
pinctrl: pinctrl-microchip-sgpio: Add OF config dependency
pinctrl: pinctrl-microchip-sgpio: Add pinctrl driver for Microsemi Serial GPIO
dt-bindings: pinctrl: Add bindings for pinctrl-microchip-sgpio driver
pinctrl: at91-pio4: add support for fewer lines on last PIO bank
pinctrl: sunxi: Always call chained_irq_{enter, exit} in sunxi_pinctrl_irq_handler
pinctrl: sunxi: Mark the irq bank not found in sunxi_pinctrl_irq_handler() with WARN_ON
pinctrl: sunxi: fix irq bank map for the Allwinner A100 pin controller
...
Here is the big staging and IIO driver pull request for 5.11-rc1
Lots of different things in here:
- loads of driver updates
- so many coding style cleanups
- new IIO drivers
- Android ION code is finally removed from the tree
- wimax drivers are moved to staging on their way out of the kernel
Nothing really exciting, just the constant grind of kernel development :)
All have been in linux-next for a while with no reported issues.
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
-----BEGIN PGP SIGNATURE-----
iG0EABECAC0WIQT0tgzFv3jCIUoxPcsxR9QN2y37KQUCX9iCdw8cZ3JlZ0Brcm9h
aC5jb20ACgkQMUfUDdst+yn44QCguVCsIkhxYmnuTAkrPQP74CbJoJwAoLVoPM5K
LJRbMYjGfRc4gZehlrIV
=clR4
-----END PGP SIGNATURE-----
Merge tag 'staging-5.11-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/staging
Pull staging / IIO driver updates from Greg KH:
"Here is the big staging and IIO driver pull request for 5.11-rc1
Lots of different things in here:
- loads of driver updates
- so many coding style cleanups
- new IIO drivers
- Android ION code is finally removed from the tree
- wimax drivers are moved to staging on their way out of the kernel
Nothing really exciting, just the constant grind of kernel development :)
All have been in linux-next for a while with no reported issues"
* tag 'staging-5.11-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/staging: (341 commits)
staging: olpc_dcon: Do not call platform_device_unregister() in dcon_probe()
staging: most: Fix spelling mistake "tranceiver" -> "transceiver"
staging: qlge: remove duplicate word in comment
staging: comedi: mf6x4: Fix AI end-of-conversion detection
staging: greybus: Add TODO item about modernizing the pwm code
pinctrl: ralink: add a pinctrl driver for the rt2880 family
dt-bindings: pinctrl: rt2880: add binding document
staging: rtl8723bs: remove ELEMENT_ID enum
staging: rtl8723bs: remove unused macros
staging: rtl8723bs: replace EID_EXTCapability
staging: rtl8723bs: replace EID_BSSIntolerantChlReport
staging: rtl8723bs: replace EID_BSSCoexistence
staging: rtl8723bs: replace _MME_IE_
staging: rtl8723bs: replace _WAPI_IE_
staging: rtl8723bs: replace _EXT_SUPPORTEDRATES_IE_
staging: rtl8723bs: replace _ERPINFO_IE_
staging: rtl8723bs: replace _CHLGETXT_IE_
staging: rtl8723bs: replace _COUNTRY_IE_
staging: rtl8723bs: replace _IBSS_PARA_IE_
staging: rtl8723bs: replace _TIM_IE_
...
This adds 'interrupt-controller' features for the signals available on
the Microchip SGPIO controller, however only for controller versions
on the Sparx5 platform (or later).
Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com>
Link: https://lore.kernel.org/r/20201209142753.683208-2-lars.povlsen@microchip.com
[Select GPIOLIB_IRQCHIP in Kconfig]
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Mistakenly the buffers (input and output) become enabled together for a short
period of time during GPIO request. This is problematic, because instead of
initial motive to disable them in the commit af7e3eeb84
("pinctrl: intel: Disable input and output buffer when switching to GPIO"),
the driven value on the pin, which might be used as an IRQ line, brings
firmwares of some touch pads to an awkward state that needs a full power off
to recover. Fix this, as stated in the culprit commit, by disabling the buffers.
Fixes: af7e3eeb84 ("pinctrl: intel: Disable input and output buffer when switching to GPIO")
BugLink: https://bugzilla.kernel.org/show_bug.cgi?id=210497
Reported-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Tested-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Tested-by: Kai-Heng Feng <kai.heng.feng@canonical.com>
Link: https://lore.kernel.org/r/20201208182403.40435-1-andriy.shevchenko@linux.intel.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
These Socs have 1-3 banks of 8-32 gpios. Rather then setting the muxing of each
pin individually, these socs have mux groups that when set will effect 1-N pins.
Pin groups have a 2, 4 or 8 different muxes.
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
Link: https://lore.kernel.org/r/20201208075523.7060-3-sergio.paracuellos@gmail.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Commit 6726fbff19bf ("pinctrl: aspeed: Fix GPI only function problem.")
fixes access to GPIO banks T and U on the AST2600. Both banks contain
input-only pins and the GPIO pin function is named GPITx and GPIUx
respectively. Unfortunately the fix had a negative impact on GPIO banks
D and E for the AST2400 and AST2500 where the GPIO pass-through
functions take similar "GPI"-style names. The net effect on the older
SoCs was that when the GPIO subsystem requested a pin in banks D or E be
muxed for GPIO, they were instead muxed for pass-through mode.
Mistakenly muxing pass-through mode e.g. breaks booting the host on
IBM's Witherspoon (AC922) platform where GPIOE0 is used for FSI.
Further exploit the names in the provided expression structure to
differentiate pass-through from pin-specific GPIO modes.
This follow-up fix gives the expected behaviour for the following tests:
Witherspoon BMC (AST2500):
1. Power-on the Witherspoon host
2. Request GPIOD1 be muxed via /sys/class/gpio/export
3. Request GPIOE1 be muxed via /sys/class/gpio/export
4. Request the balls for GPIOs E2 and E3 be muxed as GPIO pass-through
("GPIE2" mode) via a pinctrl hog in the devicetree
Rainier BMC (AST2600):
5. Request GPIT0 be muxed via /sys/class/gpio/export
6. Request GPIU0 be muxed via /sys/class/gpio/export
Together the tests demonstrate that all three pieces of functionality
(general GPIOs via 1, 2 and 3, input-only GPIOs via 5 and 6, pass-through
mode via 4) operate as desired across old and new SoCs.
Fixes: 9b92f5c51e ("pinctrl: aspeed: Fix GPI only function problem.")
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Tested-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Cc: Billy Tsai <billy_tsai@aspeedtech.com>
Cc: Joel Stanley <joel@jms.id.au>
Link: https://lore.kernel.org/r/20201126063337.489927-1-andrew@aj.id.au
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Add initial pinctrl driver to support pin configuration for
LPASS (Low Power Audio SubSystem) LPI (Low Power Island) pinctrl
on SM8250.
This IP is an additional pin control block for Audio Pins on top the
existing SoC Top level pin-controller.
Hardware setup looks like:
TLMM GPIO[146 - 159] --> LPASS LPI GPIO [0 - 13]
This pin controller has some similarities compared to Top level
msm SoC Pin controller like 'each pin belongs to a single group'
and so on. However this one is intended to control only audio
pins in particular, which can not be configured/touched by the
Top level SoC pin controller except setting them as gpios.
Apart from this, slew rate is also available in this block for
certain pins which are connected to SLIMbus or SoundWire Bus.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20201202163443.26499-3-srinivas.kandagatla@linaro.org
[Add some dependencies]
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Fix the following sparse warnings:
drivers/pinctrl/pinctrl-microchip-sgpio.c:63:31: warning: symbol 'properties_luton' was not declared. Should it be static?
drivers/pinctrl/pinctrl-microchip-sgpio.c:68:31: warning: symbol 'properties_ocelot' was not declared. Should it be static?
drivers/pinctrl/pinctrl-microchip-sgpio.c:73:31: warning: symbol 'properties_sparx5' was not declared. Should it be static?
Signed-off-by: Zou Wei <zou_wei@huawei.com>
Link: https://lore.kernel.org/r/1606218173-3722-1-git-send-email-zou_wei@huawei.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
If CONFIG_HAS_IOMEM is not set, devm_platform_ioremap_resource() will
be not built in drivers/base/platform.c and then there exists a build
error about undefined reference to "devm_platform_ioremap_resource"
in pinctrl-at91-pio4.c under COMPILE_TEST and CONFIG_PINCTRL_AT91PIO4,
make PINCTRL_AT91PIO4 depend on HAS_IOMEM to fix it.
Reported-by: kernel test robot <lkp@intel.com>
Signed-off-by: Tiezhu Yang <yangtiezhu@loongson.cn>
Link: https://lore.kernel.org/r/1606209423-4742-1-git-send-email-yangtiezhu@loongson.cn
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This patch is used to fix low level output voltage issue.
A pin is changed from input pull-up to output high.
The Dout value of the pin is default as 0.
If we change the direction of the pin before the dout value of the pin,
It maybe produce a low level output voltage between "input pull-up" and
"output high".
Signed-off-by: Zhiyong Tao <zhiyong.tao@mediatek.com>
Link: https://lore.kernel.org/r/20201120093058.7248-2-zhiyong.tao@mediatek.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
if of_find_device_by_node() succeed, pinctrl_falcon_probe() doesn't have
a corresponding put_device(). Thus add put_device() to fix the exception
handling for this function implementation.
Fixes: e316cb2b16 ("OF: pinctrl: MIPS: lantiq: adds support for FALCON SoC")
Signed-off-by: Yu Kuai <yukuai3@huawei.com>
Link: https://lore.kernel.org/r/20201119011219.2248232-1-yukuai3@huawei.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
s500_padinfo[] is never modified and should be made 'const' to allow
the compiler to optimize code generation, i.e. put it in the text
section instead of the data section.
Before:
text data bss dec hex filename
12503 5088 0 17591 44b7 drivers/pinctrl/actions/pinctrl-s500.o
After:
text data bss dec hex filename
14435 3156 0 17591 44b7 drivers/pinctrl/actions/pinctrl-s500.o
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
Link: https://lore.kernel.org/r/24505deb08d050eb4ce38f186f4037d7541ea217.1605722628.git.cristian.ciocaltea@gmail.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The pinctrl-microchip-sgpio driver needs OF support, so add that to
Kconfig.
Reported-by: Randy Dunlap <rdunlap@infradead.org>
Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com>
Acked-by: Randy Dunlap <rdunlap@infradead.org>
Link: https://lore.kernel.org/r/20201125122014.11237-1-lars.povlsen@microchip.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This adds a pinctrl driver for the Microsemi/Microchip Serial GPIO
(SGPIO) device used in various SoC's.
The driver is added as a pinctrl driver, albeit only having just GPIO
support currently. The hardware supports other functions that will be
added following.
Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com>
Link: https://lore.kernel.org/r/20201113145151.68900-3-lars.povlsen@microchip.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Only a cleanup of unneeded breaks.
-----BEGIN PGP SIGNATURE-----
iQJEBAABCgAuFiEE3dJiKD0RGyM7briowTdm5oaLg9cFAl/Gq5QQHGtyemtAa2Vy
bmVsLm9yZwAKCRDBN2bmhouD16axD/9yC9QmPTOSFxEX/gyEHz1lQRFrRcOOsXIp
h9pxLtRU+rp0m280/AQyb34HhnDs8plknI2ekw/puPnxVOJ9CvgiqZsV1K0nNwZn
d7bYYgwMjAslkr92WcbBUhS/qj0VtOEPy3WFsjllxp4E2ZPyDvrL5r1A2d1IaS5/
D353WxFCHT6m0afmDxZvvHx7qr/p1y1aV9Fc0ddrZQpUXciSjnYPaQalOrs4zJaS
j5MM25YRl5YKfn2wVsD/kKWCaFprLXz0fUFeMkx8IVrcoRSORaTQF068e5wPtzFI
+v9e4GWqfLxg3BnL5+GqXuGjg3dtHPb+I9e4squ3SZpKRqTEpEGSDOUMZ0PrKoj6
YKOR9mCXUdUh8mh4V8WjIyn0sv0JZ6X/kluje8R9/Aov+22G9+vM9z0hDZx1+QML
nWTu+B3RsQXYs1F3QL2DTon/eGozj1+qrMdKH4bTfgcCkSrxLConlWwTYVv9Ho4h
XO2mUzVEadkfUuec4zE3LtA9c/Pllgpv4UdhMNAXBkJuV6Kq+iDhULta+dmVWwJ0
6YhvikUX2Z4r4BlFbx+7L0pMotClAbs+++mBs26YX0WgZdtf01ubAgo0oKcDLtJI
GICr+bCEYnO1zwFcpy8NxjsqaFfTQ19LeDTcZHhnqT5F8yATkUQEZPnVdshUbliq
bzOiJMf1Zg==
=wzy/
-----END PGP SIGNATURE-----
Merge tag 'samsung-pinctrl-5.11' of https://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/samsung into devel
Samsung pinctrl drivers changes for v5.11
Only a cleanup of unneeded breaks.
- Add QSPI pin groups on R-Car E3, H3, M3-W/W+, and M3-N,
- A small fix for a Clang warning.
-----BEGIN PGP SIGNATURE-----
iHUEABYIAB0WIQQ9qaHoIs/1I4cXmEiKwlD9ZEnxcAUCX8D/lAAKCRCKwlD9ZEnx
cLu+APwPXWg+/eDeGMft7GROw5SbCxhYcB8Gaouno7oYY7Z6mAD/cC9TJXrdZKV2
dRsTFT3bSyQD8iSVd+J/4AcqmoTHHQM=
=TRxU
-----END PGP SIGNATURE-----
Merge tag 'renesas-pinctrl-for-v5.11-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel
pinctrl: renesas: Updates for v5.11 (take two)
- Add QSPI pin groups on R-Car E3, H3, M3-W/W+, and M3-N,
- A small fix for a Clang warning.
Some products, like sama7g5, do not have a full last bank of PIO lines.
In this case for example, sama7g5 only has 8 lines for the PE bank.
PA0-31, PB0-31, PC0-31, PD0-31, PE0-7, in total 136 lines.
To cope with this situation, added a data attribute that is product dependent,
to specify the number of lines of the last bank.
In case this number is different from the macro ATMEL_PIO_NPINS_PER_BANK,
adjust the total number of lines accordingly.
This will avoid advertising 160 lines instead of the actual 136, as this
product supports, and to avoid reading/writing to invalid register addresses.
Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
Acked-by: Ludovic Desroches <ludovic.desroches@microchip.com>
Link: https://lore.kernel.org/r/20201113132429.420940-1-eugen.hristev@microchip.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* Add Intel Alder Lake-S pin controller support
* Add Intel Elkhart Lake pin controller support
* Add Intel Lakefield driver pin controller support
* Miscellaneous fixes for Intel Lynxpoint driver
The following is an automated git shortlog grouped by driver:
intel:
- Add Intel Alder Lake-S pin controller support
- Add Intel Elkhart Lake pin controller support
- Add blank line before endif in Kconfig
- Add Intel Lakefield pin controller support
lynxpoint:
- Enable pin configuration setting for GPIO chip
- Use defined constant for disabled bias explicitly
- Unify initcall location in the code
-----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEqaflIX74DDDzMJJtb7wzTHR8rCgFAl+9F/kACgkQb7wzTHR8
rCgIdA//S5ngGCIWeob63cJOXngX3A/AqXbhOJ4RCtKRsIUkMDc9kLlKRHvCVLQu
3+pWFsPU9KLQ4zqKek6V0PA4C6gfDLYD45icfvUcSEmsAj8imBscUr8CUQgNJ85B
PvtsHcMFvEICrkf26MZstqWhYKSVZy3pZAAhOGXVGknPgOANXk6ec7zR2qfmLU7J
mKYpg9znG0LzqRjqHYFl+E+263idvKRSfQc+uCige8y9Xn/u69c329axaEsSn5rq
TdyyYVi9EXrUDvv4oa9UGxN+leOaMa40zeXbJtS0vIUzubHqLM1Xs8G0yvta8mq3
gw4bnKLSHUSn6akTUIfswTWA60vVfpH6wI/+BrKBItrCtNvcOZMzyUf99hHKLXXo
Qh+YYnh3QhMmI1Cz/wsDoh6SLXjtH/gpVZ2KzAmQAxXLhd3cOEhggOabQruC10jz
JndNxBULwtTf8LnD5I1Xy+IHAYuvepLvW5jDYzIgc0iYQ+S7e+VfRriETEId2jtj
yXkeGWb0KSx6XfJc4HIf97jmJ8juolv3gHLzd+PPay7r6yU602239uLsPnps8Qxs
W2fi8eecWilYYrZJkfh1hrMK5NG6nvoxew9yhNTAmIgCCTFXqzKPOopWc1wSbsl9
T9wlxdtxqV8KYPyrEhUmE/Olmi4+SS4OADw5uFyG+qAOl+VhrOQ=
=e2B8
-----END PGP SIGNATURE-----
Merge tag 'intel-pinctrl-v5.11-1' of gitolite.kernel.org:pub/scm/linux/kernel/git/pinctrl/intel into devel
intel-pinctrl for v5.11-1
* Add Intel Alder Lake-S pin controller support
* Add Intel Elkhart Lake pin controller support
* Add Intel Lakefield driver pin controller support
* Miscellaneous fixes for Intel Lynxpoint driver
The following is an automated git shortlog grouped by driver:
intel:
- Add Intel Alder Lake-S pin controller support
- Add Intel Elkhart Lake pin controller support
- Add blank line before endif in Kconfig
- Add Intel Lakefield pin controller support
lynxpoint:
- Enable pin configuration setting for GPIO chip
- Use defined constant for disabled bias explicitly
- Unify initcall location in the code
It is found on many allwinner soc that there is a low probability that
the interrupt status cannot be read in sunxi_pinctrl_irq_handler. This
will cause the interrupt status of a gpio bank to always be active on
gic, preventing gic from responding to other spi interrupts correctly.
So we should call the chained_irq_* each time enter sunxi_pinctrl_irq_handler().
Signed-off-by: Yangtao Li <frank@allwinnertech.com>
Cc: stable@vger.kernel.org
Link: https://lore.kernel.org/r/85263ce8b058e80cea25c6ad6383eb256ce96cc8.1604988979.git.frank@allwinnertech.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The interrupt descriptor cannot be found in the interrupt processing
function, and this situation cannot happen when the system is running
normally. It doesn't seem right to return directly to the status of not
handling gic. In this case, it must be a bug, let's mark it with
WARN_ON.
Signed-off-by: Yangtao Li <frank@allwinnertech.com>
Link: https://lore.kernel.org/r/470ebae22fc5434ad5409c4f6e29255467b3cef6.1604988979.git.frank@allwinnertech.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
One fixup following my patch commit be117ca322 ("pinctrl:
qcom: Kconfig: Rework PINCTRL_MSM to be a depenency rather then
a selected config") being queued in LinusW's tree, as a new
config entry was added for the msm8953 that also needs the
change.
Applies to LinusW's pinctrl devel tree.
Signed-off-by: John Stultz <john.stultz@linaro.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Andy Gross <agross@kernel.org>
Cc: Prasad Sodagudi <psodagud@codeaurora.org>
Cc: Vladimir Lypak <junak.pub@gmail.com>
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: linux-arm-msm@vger.kernel.org
Cc: linux-gpio@vger.kernel.org
Link: https://lore.kernel.org/r/20201110215619.86076-1-john.stultz@linaro.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* Fix HOSTSW_OWN offset and unhide SPI group of pins on Jasper Lake
* Fix debounce configuration on Baytrail when it's turned off
* Fix default bias setting on Merrifield
The following is an automated git shortlog grouped by driver:
baytrail:
- Avoid clearing debounce value when turning it off
jasperlake:
- Fix HOSTSW_OWN offset
- Unhide SPI group of pins
merrifield:
- Set default bias in case no particular value given
-----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEqaflIX74DDDzMJJtb7wzTHR8rCgFAl+yno0ACgkQb7wzTHR8
rChXdxAAw027fWAiA8fDZPri4ZWcvL4QFJB58phUBRayu8ARrOdF0V4xGW4EWKEL
HrMTsB0RFFL5hm0PhWz0vkcoaGGTfe0mJ7Gvbp+x1Kx17ELWQaUS7KOor3omzp48
hwdrU4np4F8GJ4qJb/sbatk22QDFA4sgtTjMrn2exir/3IVBFp3+1wybjn9Zdm/E
m+f3ah7PMpFKyUj+n4gUd2miCYie9FYySbu2FWwqegPdUOmd02j5EWTGOKqw+GmQ
XhNHV7nlMdeyxds5QNtSTGipvIq/+gYXji4FtO5O6DEM72k53hrDlPm0qQjNOdg6
Q3UlorVI5mJfWeaoTFgq9m2ccHM/fTTAEqo3sYmgXD7Ukwd1XTPZPG+od7WPpqDM
NufGv4MGcVIH/mK6kVCUC4gRIA6ahGkokQUCgf+YBH4VBYOh5XBzOlV555+BUGdM
Uj0ANNC3A+AnQiRjo0odVlVrqz+zfBeDLatI7NXoweg3r1L1d7EhwrK7dvCW8yEb
3fEIh0ZUILwEgHg3k++hKvaz7200ON58sRKNwuQJpv75V2GNbj8EVsK+rSoZRrZW
TASXBiXkzxFa3/KGeEpDtD+96goGE9nlcmA2NX21SCB37XbR1OB+zl6n4WRW4xBt
nRHH8GAbZ6j3NSGgNi80I7jZdjpXfjPtdTElJeGR/2L8v/RT3Y4=
=xymw
-----END PGP SIGNATURE-----
Merge tag 'intel-pinctrl-v5.10-3' of gitolite.kernel.org:pub/scm/linux/kernel/git/pinctrl/intel into fixes
intel-pinctrl for v5.10-3
* Fix HOSTSW_OWN offset and unhide SPI group of pins on Jasper Lake
* Fix debounce configuration on Baytrail when it's turned off
* Fix default bias setting on Merrifield
The following is an automated git shortlog grouped by driver:
baytrail:
- Avoid clearing debounce value when turning it off
jasperlake:
- Fix HOSTSW_OWN offset
- Unhide SPI group of pins
merrifield:
- Set default bias in case no particular value given
Since commit 4b563a0666 ("ARM: imx: Remove imx21 support") the imx21
SoC is no longer supported.
Get rid of its pinctrl driver too, which is now unused.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Acked-by: Shawn Guo <shawnguo@kernel.org>
Link: https://lore.kernel.org/r/20201110190210.29376-1-festevam@gmail.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
- Add remaining video-in (VIN) pin groups on R-Car H2 and RZ/G1H,
- Image size optimizations and code consolidations,
- Minor fixes and improvements.
-----BEGIN PGP SIGNATURE-----
iHUEABYIAB0WIQQ9qaHoIs/1I4cXmEiKwlD9ZEnxcAUCX66aYQAKCRCKwlD9ZEnx
cHHrAP9V86MzOAHZN0Uixr/onKQtmxdy0s4JLM4HLOh1oxo9VQD/R40pMVz//WWc
tmgfV3UMUq7RyhF11Wqe+d0eAegKogk=
=Qqks
-----END PGP SIGNATURE-----
Merge tag 'renesas-pinctrl-for-v5.11-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel
pinctrl: renesas: Updates for v5.11
- Add remaining video-in (VIN) pin groups on R-Car H2 and RZ/G1H,
- Image size optimizations and code consolidations,
- Minor fixes and improvements.
Baytrail pin control has a common register to set up debounce timeout.
When a pin configuration requested debounce to be disabled, the rest
of the pins may still want to have debounce enabled and thus rely on
the common timeout value. Avoid clearing debounce value when turning
it off for one pin while others may still use it.
Fixes: 658b476c74 ("pinctrl: baytrail: Add debounce configuration")
Depends-on: 04ff5a095d ("pinctrl: baytrail: Rectify debounce support")
Depends-on: 827e1579e1 ("pinctrl: baytrail: Rectify debounce support (part 2)")
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
When GPIO library asks pin control to set the bias, it doesn't pass
any value of it and argument is considered boolean (and this is true
for ACPI GpioIo() / GpioInt() resources, by the way). Thus, individual
drivers must behave well, when they got the resistance value of 1 Ohm,
i.e. transforming it to sane default.
In case of Intel Merrifield pin control hardware the 20 kOhm sounds plausible
because it gives a good trade off between weakness and minimization of leakage
current (will be only 50 uA with the above choice).
Fixes: 4e80c8f505 ("pinctrl: intel: Add Intel Merrifield pin controller support")
Depends-on: 2956b5d94a ("pinctrl / gpio: Introduce .set_config() callback for GPIO chips")
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
GPIOs that attempt to use interrupts get thwarted with a message like:
"pin 161 cannot be used as IRQ" (for instance with SD_CD). This is because
the HOSTSW_OWN offset is incorrect, so every GPIO looks like it's
owned by ACPI.
Fixes: e278dcb704 ("pinctrl: intel: Add Intel Jasper Lake pin controller support")
Cc: stable@vger.kernel.org
Signed-off-by: Evan Green <evgreen@chromium.org>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
If the group of pins is hidden in the pin list it affects
the register offset calculation despite fixed GPIO base.
Hence, the offsets of all pins after the hidden group
are broken. Instead we have to unhide the group and use a flag
to exclude it from GPIO number space.
Fixes: e278dcb704 ("pinctrl: intel: Add Intel Jasper Lake pin controller support")
Reported-by: Divagar Mohandass <divagar.mohandass@intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Baytrail pin control has a common register to set up debounce timeout.
When a pin configuration requested debounce to be disabled, the rest
of the pins may still want to have debounce enabled and thus rely on
the common timeout value. Avoid clearing debounce value when turning
it off for one pin while others may still use it.
Fixes: 658b476c74 ("pinctrl: baytrail: Add debounce configuration")
Depends-on: 04ff5a095d ("pinctrl: baytrail: Rectify debounce support")
Depends-on: 827e1579e1 ("pinctrl: baytrail: Rectify debounce support (part 2)")
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
The only usage of sh73a0_vccq_mc0_ops is to assign its address to the
ops field in the regulator_desc struct, which is a const pointer. Make
it const to allow the compiler to put it in read-only memory.
Signed-off-by: Rikard Falkeborn <rikard.falkeborn@gmail.com>
Link: https://lore.kernel.org/r/20201109221012.177478-1-rikard.falkeborn@gmail.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
On SuperH and ARM SH/R-Mobile SoCs, the pin control driver handles
GPIOs, too. To reduce code size when compiling a kernel supporting only
modern SoCs, most, but not all, of the GPIO functionality is protected
by checks for CONFIG_PINCTRL_SH_FUNC_GPIO.
Factor out the remaining parts when not needed:
1. sh_pfc_soc_info.{in,out}put describe GPIO pins that have input
resp. output capabilities (SuperH and SH/R-Mobile).
2. sh_pfc_soc_info.gpio_irq{,_size} describe the mapping from GPIO
pins to interrupt numbers (SH/R-Mobile).
3. sh_pfc_gpio_set_direction() configures GPIO direction, called from
the GPIO driver through pinctrl_gpio_direction_{in,out}put()
(SH/R-Mobile). Unfortunately this function cannot just be moved to
drivers/pinctrl/renesas/gpio.c, as it relies on knowledge of
sh_pfc_pinctrl, which is internal to
drivers/pinctrl/renesas/pinctrl.c.
While code size reduction is minimal, this does help in documenting
depencies.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20201028151637.1734130-9-geert+renesas@glider.be
Currently, the rcar_pinmux_[gs]et_bias() helpers handle only SoCs that
have separate LSI Pin Pull-Enable (PUEN) and Pull-Up/Down Control (PUD)
registers, like R-Car Gen3 and RZ/G2. Update the function to handle
SoCs that have only LSI Pin Pull-Up Control Register (PUPR), like R-Car
Gen1/Gen2 and RZ/G1.
Reduce code duplication by converting the R-Car M1A pin control driver
to use the common handler.
Note that this changes behavior in case the (invalid!) option
"bias-pull-down" is used in an R-Car M1A DTS: before, it was ignored
silently; after this change, it is considered the same as
"bias-pull-up".
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20201028151637.1734130-8-geert+renesas@glider.be
The handling of the LSI Pin Pull-Up Control Registers (PUPR) on R-Car
M1A uses register offsets instead of register physical addresses.
This is different from the handling on other R-Car parts.
Convert the bias handling from register offsets to physical addresses.
This increases uniformity, and prepares for consolidation of the bias
handling.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20201028151637.1734130-7-geert+renesas@glider.be
Shrink sh_pfc_pin_config from 8 to 2 bytes:
- The mux_set flag can be removed, as a non-zero mark value means the
same (zero = PINMUX_RESERVED is an invalid mark value),
- The gpio_enabled flag needs only a single bit,
- Mark values are small integers, and can easily fit in a 15-bit
bitfield.
This saves 6 bytes per pin when allocating the sh_pfc_pinctrl.configs
array, i.e. it reduces run-time memory consumption by ca. 1.5 KiB.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20201028151637.1734130-5-geert+renesas@glider.be
On arm64, pointer size and alignment is 64-bit, hence a 4-byte hole is
present in between the enum_id and name members of the sh_pfc_pin
structure. Get rid of this hole by sorting the structure's members by
decreasing size.
This saves up to 1.5 KiB per enabled SoC, and reduces the size of a
kernel including support for all R-Car Gen3 SoCs by more than 10 KiB.
This has no size impact on SH and arm32.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20201028151637.1734130-4-geert+renesas@glider.be
This driver supports both RZ/G1[MN] and R-Car M2-W/M2-N SoCs.
Optimize pinctrl image size for RZ/G1[MN], when support for R-Car
M2-W/M2-N (R8A779[13]) is not enabled.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20201019124258.4574-7-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This driver supports both RZ/G1H and R-Car H2 SoCs.
Optimize pinctrl image size for RZ/G1H, when support for R-Car H2
(R8A7790) is not enabled.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20201019124258.4574-6-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This driver supports both RZ/G2E and R-Car E3 SoCs.
Optimize pinctrl image size for RZ/G2E, when support for R-Car E3
(R8A77990) is not enabled.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20201019124258.4574-5-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This driver supports both RZ/G2N and R-Car M3-N SoCs.
Optimize pinctrl image size for RZ/G2N, when support for R-Car M3-N
(R8A77965) is not enabled.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20201019124258.4574-4-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This driver supports both RZ/G2M and R-Car M3-W/W+ SoCs.
Optimize pinctrl image size for RZ/G2M, when support for R-Car M3-W/W+
(R8A7796[01]) is not enabled.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20201019132805.5996-1-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This driver supports both RZ/G2H and R-Car H3 ES2 SoCs.
Optimize pinctrl image size for RZ/G2H, when support for R-Car H3 ES2
(R8A77951) is not enabled.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20201019124258.4574-2-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
When GPIO library asks pin control to set the bias, it doesn't pass
any value of it and argument is considered boolean (and this is true
for ACPI GpioIo() / GpioInt() resources, by the way). Thus, individual
drivers must behave well, when they got the resistance value of 1 Ohm,
i.e. transforming it to sane default.
In case of Intel Merrifield pin control hardware the 20 kOhm sounds plausible
because it gives a good trade off between weakness and minimization of leakage
current (will be only 50 uA with the above choice).
Fixes: 4e80c8f505 ("pinctrl: intel: Add Intel Merrifield pin controller support")
Depends-on: 2956b5d94a ("pinctrl / gpio: Introduce .set_config() callback for GPIO chips")
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
GPIOs that attempt to use interrupts get thwarted with a message like:
"pin 161 cannot be used as IRQ" (for instance with SD_CD). This is because
the HOSTSW_OWN offset is incorrect, so every GPIO looks like it's
owned by ACPI.
Fixes: e278dcb704 ("pinctrl: intel: Add Intel Jasper Lake pin controller support")
Cc: stable@vger.kernel.org
Signed-off-by: Evan Green <evgreen@chromium.org>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
If the group of pins is hidden in the pin list it affects
the register offset calculation despite fixed GPIO base.
Hence, the offsets of all pins after the hidden group
are broken. Instead we have to unhide the group and use a flag
to exclude it from GPIO number space.
Fixes: e278dcb704 ("pinctrl: intel: Add Intel Jasper Lake pin controller support")
Reported-by: Divagar Mohandass <divagar.mohandass@intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
It appears that pin configuration for GPIO chip hasn't been enabled yet
due to absence of ->set_config() callback.
Enable it here for Intel Lynxpoint PCH.
Depends-on: 2956b5d94a ("pinctrl / gpio: Introduce .set_config() callback for GPIO chips")
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
We have a specific constant to describe a disabled bias,
i.e. GPIWP_NONE. Use it explicitly instead of making
an assumption about its value.
While at it, move argument assignment to the switch-case
in lp_pin_config_get().
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Replace the two separate calls for setting the irq handler and data with a
single irq_set_chained_handler_and_data() call.
Signed-off-by: Martin Kaiser <martin@kaiser.cx>
Link: https://lore.kernel.org/r/20201108180144.28594-1-martin@kaiser.cx
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Commit be117ca322 ("pinctrl: qcom: Kconfig: Rework PINCTRL_MSM to be a
dependency rather then a selected config") moved the qcom pinctrl drivers
to have PINCTRL_MSM as dependency rather then a selected config, so do
this change for SDX55 pinctrl driver as well.
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20201111043610.177168-1-vkoul@kernel.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
We need a more granular distribution among funcion A
and function B for the LCD pins for the Samsung
GT-I9070. Provide some new pin groups so we can
configure this phone properly.
Link: https://lore.kernel.org/r/20201110232330.2242167-1-linus.walleij@linaro.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* Respect bias setting when comes from ACPI
The following is an automated git shortlog grouped by driver:
intel:
- Set default bias in case no particular value given
- Fix 2 kOhm bias which is 833 Ohm
-----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEqaflIX74DDDzMJJtb7wzTHR8rCgFAl+lkxIACgkQb7wzTHR8
rChnvA//WtUChge5HzlJu/6/Eim32S1N8HPaEsxEpNT3B/D8T3KFhpcbzTM+7tDC
3HLgqTa/r/VmCbJH1Su//VFLBRIndYjSZKgLl2c++YQe5bTxWR0HY+su2U5Fzf24
TwpeuhM8+7mWCvI4VeEOULZaZ+3OSfTbg9ccGZB7pD6GLonVSogs6eg4tdNeMDDs
Lv5GQLc8NrPJZyKqnc5S3GScyY9bemQG8gGjtDSOo8YPMGxPQl2Mcz5iEOlw6lzT
dGvB184X4XTD4L9RgYtEJmP9peEEG2xJuWOzxUI1EkitA7j9MwyNPjeQITv1UV5i
HWIN91cqBGPv/ic286mVAdP0lnAcYiOF/yVHDkW4zKDj1QC35wj26eRQcuqTfEZS
owqb0hEP2NlCqBGWHHOIsxCaTaPokO4pG0zsLjXNmw1z1wGfIJncRwNha0cfcQEE
UDUXNcBiDceh5xYz/0unj4TxMTFOfmIwTtn3CkOVJMiNMsKCJfXl0+KKLN0D/ebg
FtrXYfwK6f4clFBxD9wqLT7UwzYX6Bnn4fLA3Z+LPRKenpXDZ8guld//rn98mcAp
0hAEER1YceUnADEPwKftBxH3iO4SLQQQdoLFWYu4MGybbzSLi65EkwI16GWy5y94
EcQRFlGsdIMH7rSVV6934qI3CYq53intnjFNQh+Bk8omiteV9Us=
=Voi9
-----END PGP SIGNATURE-----
Merge tag 'intel-pinctrl-v5.10-2' of git://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/intel into fixes
intel-pinctrl for v5.10-2
* Respect bias setting when comes from ACPI
The following is an automated git shortlog grouped by driver:
intel:
- Set default bias in case no particular value given
- Fix 2 kOhm bias which is 833 Ohm
This patch adds support for Serval pinctrl, using the ocelot driver as
basis. It adds pinconfig support as well, as supported by the
platform.
gclement: Split from a larger patch adding support all platforms in
the same time.
Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Link: https://lore.kernel.org/r/20201106093118.965152-5-gregory.clement@bootlin.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This patch adds support for Luton pinctrl, using the ocelot driver as
basis. It adds pinconfig support as well, as supported by the
platform.
gclement: Split from a larger patch adding support all platforms in
the same time.
Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Link: https://lore.kernel.org/r/20201106093118.965152-4-gregory.clement@bootlin.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Tweaks to allow pinctrl-msm code to be loadable as a module.
This is needed in order to support having the qcom-scm driver,
which pinctrl-msm calls into, configured as a module.
This requires that we tweak Kconfigs selecting PINCTRL_MSM to
also depend on QCOM_SCM || QCOM_SCM=n so that we match the
module setting of QCOM_SCM.
Signed-off-by: John Stultz <john.stultz@linaro.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
Cc: Andy Gross <agross@kernel.org>
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Joerg Roedel <joro@8bytes.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Marc Zyngier <maz@kernel.org>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Vinod Koul <vkoul@kernel.org>
Cc: Kalle Valo <kvalo@codeaurora.org>
Cc: Maulik Shah <mkshah@codeaurora.org>
Cc: Lina Iyer <ilina@codeaurora.org>
Cc: Saravana Kannan <saravanak@google.com>
Cc: Todd Kjos <tkjos@google.com>
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Cc: linux-arm-msm@vger.kernel.org
Cc: iommu@lists.linux-foundation.org
Cc: linux-gpio@vger.kernel.org
Link: https://lore.kernel.org/r/20201106042710.55979-2-john.stultz@linaro.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This patch reworks PINCTRL_MSM to be a visible option, and
instead of having the various SoC specific drivers select
PINCTRL_MSM, this switches those configs to depend on
PINCTRL_MSM.
This is useful, as it will be needed in order to cleanly support
having the qcom-scm driver, which pinctrl-msm calls into,
configured as a module. Without this change, we would eventually
have to add dependency lines to every config that selects
PINCTRL_MSM, and that would becomes a maintenance headache.
We also add PINCTRL_MSM to the arm64 defconfig to avoid
surprises as otherwise PINCTRL_MSM/IPQ* options previously
enabled, will be off.
Signed-off-by: John Stultz <john.stultz@linaro.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
Cc: Andy Gross <agross@kernel.org>
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Joerg Roedel <joro@8bytes.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Marc Zyngier <maz@kernel.org>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Vinod Koul <vkoul@kernel.org>
Cc: Kalle Valo <kvalo@codeaurora.org>
Cc: Maulik Shah <mkshah@codeaurora.org>
Cc: Lina Iyer <ilina@codeaurora.org>
Cc: Saravana Kannan <saravanak@google.com>
Cc: Todd Kjos <tkjos@google.com>
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Cc: linux-arm-msm@vger.kernel.org
Cc: iommu@lists.linux-foundation.org
Cc: linux-gpio@vger.kernel.org
Link: https://lore.kernel.org/r/20201106042710.55979-1-john.stultz@linaro.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Print the status of debounce filter as follows,
$ cat /sys/kernel/debug/gpio
pin129 interrupt is disabled | interrupt is masked |
disable wakeup in S0i3 state | disable wakeup in S3 state |
disable wakeup in S4/S5 state| input is high | pull-up is disabled |
Pull-down is disabled | output is disabled |
debouncing filter disabled | 0x50000
pin130 interrupt is disabled | interrupt is masked |
disable wakeup in S0i3 state | disable wakeup in S3 state |
disable wakeup in S4/S5 state | input is high | pull-up is disabled |
Pull-down is disabled | output is disabled |
debouncing filter (high) enabled |
debouncing timeout is 124800 (us)| 0x503c8
Signed-off-by: Coiby Xu <coiby.xu@gmail.com>
Link: https://lore.kernel.org/r/20201105231912.69527-4-coiby.xu@gmail.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Add the "lcd-8bit" group to the "lcd" function.
As "lcd-24bit" is a superset of "lcd-8bit", in theory the former could
be modified to only contain the pins not already included in "lcd-8bit",
just like how it's done for the JZ4740 and JZ4725B platforms. However,
we can't do that without breaking Device Tree ABI, so in that case we
have no choice but to have two groups containing the same pins.
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Tested-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
Link: https://lore.kernel.org/r/20201101090104.5088-3-paul@crapouillou.net
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Abuse the pin function pointer to store the pin function value directly,
when all the pins of a group have the same function value. Now when the
pointer value is <= 3 (unsigned), the pointer value is used as the pin
function; otherwise it is used as a regular pointer.
This drastically reduces the number of pin function tables needed, and
drops .data usage by about 2 KiB. Additionally, the few pin function
tables that are still around now contain u8 instead of int, since the
largest number that will be stored is 3.
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Tested-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
Link: https://lore.kernel.org/r/20201101090104.5088-2-paul@crapouillou.net
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
mt7622 is reported by mediatek to have only 6 pwm channels
so drop pindefines for 7th channel
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
Acked-by: Sean Wang <sean.wang@kernel.org>
Link: https://lore.kernel.org/r/20201016204019.2606-4-linux@fw-web.de
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Specify the PDC mapping for SM8250, so that gpio interrupts are
propertly mapped to the wakeup IRQs of the PDC.
Fixes: 4e3ec9e407 ("pinctrl: qcom: Add sm8250 pinctrl driver.")
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20201028043642.1141723-1-bjorn.andersson@linaro.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
