Leave a comment explaining the constant value of 27Mhz used
in include/mach/timex.h for all DaVinci platforms. Many of
the platforms actually run at 24MHz timer frequency (Eg.
EVMs of DM355, DM365 and OMAP-L1).
The comment also serves as a porting alert.
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
Create static map for internal SRAM and populate SRAM base
and size in soc_info structure to allow SRAM allocation
functions from arch/arm/mach-davinci/sram.c to work.
On DA850 SRAM is used for suspend-to-RAM implementation
in places where DDR2 cannot be accessed as its clocks are
stopped.
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
On omap-l1 devices the PLL registers can be locked from
writes. Currently the cpufreq rate setting code unlocks
PLL0 before the write actually happens. With suspend
support getting added PLL1 registers need be be unlocked
as well.
To facilitate this, unlock both PLLs during the init time
itself.
This also obviates the need to unlock PLL registers for
each CPUFreq transtition.
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
When suspend is supported, both cpuidle and suspend code
need to work on DDR2 registers. Instead of mapping the
DDR2 registers twice, do it once outside of cpuidle
driver and let cpuidle driver get the virtual base address
of DDR2 registers.
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
psc.h contains register defines for PSC module which
need to be accessed in assembly code which helps the
DA850/OMAP-L138 SoC go to sleep. Shutting down DDR clock
using PSC is a part of the sleep procedure.
Also, the PLL related hardware definitions in clock.h are
needed in assembly code to bypass the DDR2 PLL.
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
The motivation behind the change is to use the same
definitions in the assembly code responsible for
suspending the SoC, a part of which is to clock gate
the DDR2 clock.
Note that the assembly code cannot invoke the C function
meant for this. The main reason being that stack in DDR2
cannot be accessed while DDR2 clock is being clock gated.
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
Move defintions of DDR2 controller registers to memory.h
from cpuidle.c. The motivation behind the change is to be
able to use these defintions in assembly code that puts
DDR2 in self-refresh and enables the SoC to enter suspend
state.
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
As suspend support is added, the code supporting
the suspend operation needs to bypass PLLs and
needs to access the same wait time values as the
PLL code in clock.c.
To facilitate this, move the PLL wait times to
clock.h where they can be accessed by suspend code.
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
OMAP-L138 adds a second SYSCFG region having useful functionality
like deep sleep, pull up/down control and SATA clock stop.
This patch makes provision for accessing registers from second
SYSCFG region in da8xx code.
Note that OMAP-L137 has a single SYSCFG region.
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
This patch adds following changes:-
1) add sub device configuration data for TVP5146 used by vpfe capture
2) registers platform devices for vpfe_capture, isif and vpss
3) defines hardware resources for the devices listed under 2)
4) defines clock aliase for isif driver
5) adding setup_pinmux() for isif
Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
* 'omap-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap-2.6: (25 commits)
OMAP2/3: DMTIMER: Clear pending interrupts when stopping a timer
PM debug: Fix warning when no CONFIG_DEBUG_FS
OMAP3: PM: DSS PM_WKEN to refill DMA
OMAP: timekeeping: time should not stop during suspend
OMAP3: PM: Force write last pad config register into save area
OMAP: omap3_pm_get_suspend_state() error ignored in pwrdm_suspend_get()
OMAP3: PM: Enable wake-up from McBSP2, 3 and 4 modules
OMAP3: PM debug: fix build error when !CONFIG_DEBUG_FS
OMAP3: PM: Removing redundant and potentially dangerous PRCM configration
OMAP3: Fixed ARM aux ctrl register save/restore
OMAP3: CPUidle: Fixed timer resolution
OMAP3: PM: Remove duplicate code blocks
OMAP3: PM: Disable interrupt controller AUTOIDLE before WFI
OMAP3: PM: Enable system control module autoidle
OMAP3: PM: Ack pending interrupts before entering suspend
omap: Enable GPMC clock in gpmc_init
OMAP1 clock: fix for "BUG: spinlock lockup on CPU#0"
OMAP4: clocks: Fix the clksel_rate struct DPLL divs
OMAP4: PRCM: Fix the base address for CHIRONSS reg defines
OMAP: dma_chan[lch_head].flag & OMAP_DMA_ACTIVE tested twice in omap_dma_unlink_lch()
...
This patch fixes power LED blinking and power-off on DNS-323 rev. B1.
GPIO pin 3 has to be set to 1 to stop power LED blinking and to allow the LED to be controlled via leds-gpio. This pin has to be also set to 1 for power-off to work.
To power-off the rev. B1 machine, pin 8 has to be set to 1 and then set to 0 to do actual power-off.
Tested on my DNS-323 rev. B1
Signed-off-by: Erik Benada <erikbenada@yahoo.ca>
Signed-off-by: Nicolas Pitre <nico@marvell.com>
OMAP GP timers keep running for a few cycles after they are stopped,
which can cause the timer to expire and generate an interrupt. The
pending interrupt will prevent e.g. OMAP from entering suspend, thus
we ack it manually. Only applicable on OMAP2/3/4.
Signed-off-by: Tero Kristo <tero.kristo@nokia.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Commit cfc38999f (backlight: Pass device through notify callback)
added a struct device argument to the notify callback, but didn't
update the user of it in mach-hmt.c
Signed-off-by: Peter Korsgaard <jacmet@sunsite.dk>
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
* master.kernel.org:/home/rmk/linux-2.6-arm:
ARM: 5888/1: arm: Update comments in cacheflush.h and remove unnecessary V6 and V7 comments
ARM: 5886/1: arm: Fix cpu_proc_fin() for proc-v7.S and make kexec work
ARM: 5885/1: arm: Flush TLB entries in setup_mm_for_reboot()
ARM: 5884/1: arm: Fix DCC console for v7
ARM: 5883/1: Revert "disable NX support for OABI-supporting kernels"
ARM: 5882/1: ARM: Fix uncompress code compile for different defines of flush(void)
ARM: fix badly placed mach/plat entries in Kconfig & Makefile
Fix following warning when CONFIG_DEBUG_FS wasn't selected:
arch/arm/mach-omap2/pm-debug.c:57: warning: 'pm_dbg_init' declared 'static' but never defined
Signed-off-by: Sergio Aguirre <saaguirre@ti.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
Currently, DSS does not wakeup when there is a DMA request. DSS wake
up event must be enabled so that the DMA request to refill the FIFO
will wake up the CORE domain.
Signed-off-by: Subramani Venkatesh <subramani.venkatesh@windriver.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
During suspend, the kernel timekeeping subsystem is shut down. Before
suspend and upon resume, it uses a weak function
read_persistent_clock() to determine the amount of time that elapsed
during suspend.
This function was not implemented on OMAP, so from the timekeeping
subsystem perspective (and thus userspace as well) it appeared that no
time elapsed during suspend.
This patch uses the 32k sync timer as a the persistent clock.
NOTE: This does *NOT* fully handle wrapping of the 32k sync timer, so
more than one wrapping of the 32k sync timer during suspend may
cause problems. Also note there are not interrupts when the 32k
sync timer wraps, so something else has to be done.
Reported-by: Jon Hunter <jon-hunter@ti.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
Due to OMAP3 erratas 1.157, 1.185 the save of the last pad register
(ETK_D14 and ETK_D15) can fail sometimes when there is simultaneous
OCP access to the SCM register area. Fixed by writing the last
register to the save area.
Also, optimized the delay loop for the HW save to include an udelay(1),
which limits the number of unnecessary HW accesses to SCM register area
during the save.
Signed-off-by: Tero Kristo <tero.kristo@nokia.com>
Acked-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Anand Gadiyar <gadiyar@ti.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
val is an u64 pointer, we need an int to check the error.
Signed-off-by: Roel Kluin <roel.kluin@gmail.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
Wake-up from McBSP ports are needed, especially when the THRESHOLD
dma mode is in use for audio playback.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@nokia.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
The PM debug code fails to build on when CONFIG_DEBUG_FS is not
enabled.
Build error log:
arch/arm/mach-omap2/built-in.o: In function `omap_sram_idle':
arch/arm/mach-omap2/pm34xx.c:449: undefined reference to `pm_dbg_regset_save'
arch/arm/mach-omap2/pm34xx.c:460: undefined reference to `pm_dbg_regset_save'
arch/arm/mach-omap2/built-in.o: In function `configure_vc':
arch/arm/mach-omap2/pm34xx.c:1237: undefined reference to `pm_dbg_regset_init'
arch/arm/mach-omap2/pm34xx.c:1238: undefined reference to `pm_dbg_regset_init'
make: *** [.tmp_vmlinux1] Error 1
This patch fixes the above errors.
Kernel booting is tested on omap zoom2 and zoom3 boards.
Signed-off-by: Manjunatha GK <manjugk@ti.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
As part of Core domain context restoration while coming out of off mode
there are some registers being restored which are not required to be restored.
ROM code will have restored them already. Overwriting some of them can have
potential side effect. Eg: CM_CLKEN_PLL register should not be written while dpll is locked.
Tested on OMAP 3430 SDP for suspend/resume and off mode with sleep_while_idle enabled.
Signed-off-by: Vishwanath BS <vishwanath.bs@ti.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
Current value is stored on SDRAM and it is written back during wakeup.
Previously a static value of 0x72 was written there.
Signed-off-by: Tero Kristo <tero.kristo@nokia.com>
Acked-by: Thara Gopinath <thara@ti.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
Previously used u32 as temporary data storage that wraps around at 4.294s.
Signed-off-by: Tero Kristo <tero.kristo@nokia.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
This patch removes code blocks that are repeated
in function prcm_setup_regs().
Signed-off-by: Sanjeev Premi <premi@ti.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
OMAP interrupt controller goes to unknown state when there is right
combination of l3,l4 sleep/wake-up transitions, l4 autoidle in
interrupt controller and some interrupt. When this happens, interrupts
are not delivered to ARM anymore and ARM will remain in WFI (wait for
interrupt) until interrupt controller is forced to wake-up
(i.e. lauterbach).
Signed-off-by: Tero Kristo <tero.kristo@nokia.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
Enable the auto-idle feature of the SCM block to save some additional
power.
Signed-off-by: Mika Westerberg <ext-mika.1.westerberg@nokia.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
Suspending drivers may still generate interrupts just before their suspend is
completed. Any pending interrupts here will prevent sleep.
Signed-off-by: Tero Kristo <tero.kristo@nokia.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
Don't assume that gpmc_l3_clk is on, enable it before touching
configuration registers.
Note that the current code assumes that this clock is always
enabled. We are already setting smart idle and L3 autogating
for GPMC clock in gpmc_init.
Signed-off-by: Olof Johansson <olof@lixom.net>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Commit 52650505fb caused clock initialization
to fail on OMAP1 with "BUG: spinlock lockup on CPU#0" -- this is because
omap1_select_table_rate() and omap1_round_to_table_rate() call clk_get_rate()
with the clockfw spinlock held. Fix by accessing the rate directly from
the internal clock framework functions.
Thanks to Tony Lindgren <tony@atomide.com> for reporting and testing the fix.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Tony Lindgren <tony@atomide.com>
For all DPLL's the valid dividers are same as the values
to be programmed in the register. 0 is an invalid value.
The changes are generated by updating the script which autogenerates
the file modifed in the patch.
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
The CHIRONSS has its own local PRCM module and the register defines
need to use the CHIRONSS base and not the PRM base.
The changes are generated by updating the script which autogenerates
the file modifed in the patch.
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
We need to set the omap_chip.oc carefully for the clocks to work.
To fix this, set the omap_chip.oc in omap3_check_features() based
on the CONTROL_IDCODE and silicon revision registers.
Also add handling for 34xx es3.1.2 as es3.1 for now.
Fixes booting on at least overo board.
Based on an earlier patch by Paul Walmsley <paul@pwsan.com>.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Make the omap_mux_read and write available for board code,
and rename omap_mux_set_board_signals into omap_mux_write_array.
Also add the related prototypes and comments into mux.h.
In some cases we want to change the signals dynamically,
mostly for power management.
Note that we cannot use the signal names as they are set
__init to save memory.
Signed-off-by: Tony Lindgren <tony@atomide.com>
Looks like cmdline muxing got broken at some point when we
decided to limit muxing to __init code. Currently omap_mux_entry
list is not yet initialized when we try to initialize cmdline
muxing.
Fix this by calling omap_mux_init_list() before calling
omap_mux_set_cmdline_signals().
Reported-by: Philip Balister <philip@balister.org>
Tested-by: Philip Balister <philip@balister.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
The first thing that omap2_init_clksel_parent() does is check for
a non-zero .clksel field in the struct clk. Therefore, it is
pointless calling this function on clocks where the clksel field
is unset.
Remove init calls to omap2_init_clksel_parent() on clocks without
a clksel field.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
In the current implementation the sysconfig value is read into
_sysc_cache once and an actual update to the sysconfig register
happens only if the new value paased is differnt from the one in _sysc_cache.
_sysc_cache is updated only if _HWMOD_SYSCONFIG_LOADED is not set.
This can lead to the follwing issue if off mode is enabled in modules
which employs "always-retore" mechanism of context save and restore.
a. The module sets the sysconfig register through omap_device_enable.
Here _sysc_cache is updated with the value written to the sysconfig
register and left.
b. The power domain containig the module enters off mode and the
module context is lost.
c. The module in use becomes active and calls omap_device_enable to
enable itself. Here a read of sysconfig register does not happen
as _HWMOD_SYSCONFIG_LOADED flag is set. The value to be written
to the sysconfig register will be same as the one written in step a.
Since _sysc_cache reflects the previous written value an update
of the sysconfig register does not happen.
This means in modules which employs "always-restore" mechanism
after off , the sysconfig regsiters will never get updated.
This patch introduces a flag SYSC_NO_CACHE which if set ensures that the
sysconfig register is always read into _sysc_cache before an update is
attempted.
This flags need to be set only by modules which does not do a context save
but re-initializes the registers every time the module is accessed. This
includes modules like i2c, smartreflex etc.
Signed-off-by: Thara Gopinath <thara@ti.com>
[paul@pwsan.com: tweaked to apply on a different head, added flag comment]
Signed-off-by: Paul Walmsley <paul@pwsan.com>
The comments in cacheflush.h should follow what's in
struct cpu_cache_fns. The comments for V6 and V7 are
unnecessary.
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
The comments in arm_machine_restart() suggest that cpu_proc_fin()
will clean and disable cache and turn off interrupts. This does
not seem to be implemented for proc-v7.S, implement it the same
way as for proc-v6.S.
This also makes kexec work for v7. Note that a related TLB and
branch traget flush patch is also needed to avoid kexec
"crc error".
Note that there are still some issues that seem to be related
to L2 cache being on and causing occasional uncompress "crc error"
with kexec. Anyways, this gets kexec mostly working on V7 for now.
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
We need to do that if we tinker with the MMU entries.
This fixes the occasional bug with kexec where the new
fails to uncompress with "crc error". Most likely at
least kexec on v6 and v7 need this fix.
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Without this patch arch/arm/compressed/head.S defaults to generic
DCC code that does not work for v7.
For more information on the v7 DCC, see Cortex-A8 TRM
"12.11.1 Debug communications channel".
To use it with post 2.6.33-rc1 or later, you need to have:
CONFIG_DEBUG_LL=y
ONFIG_DEBUG_ICEDCC=y
CONFIG_EARLY_PRINTK=y
Earlier kernels need commit 93fd03a8c6
backported.
Tested on omap3430.
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This reverts commit 14f0aa3593.
That commit was needed earlier because system call restarting for
OABI (compat) required an executable stack and thus had problems
with NX. Since ab72b00734 ("ARM: Fix signal restart issues
with NX and OABI compat") has reworked the code to not require an
executable stack anymore, we can re-enable NX support for kernels
with OABI (compat) support.
Signed-off-by: Rabin Vincent <rabin@rab.in>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
