Don't use a static for WM8974 PLL factors - we don't support more than
one device so it won't happen but no sense in leaving the race condition
hanging around. Also, pre_div is a single bit and it's a bit simpler if
we move the handling of the factor of 4 in the output into the
coefficient setup.
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
The DMA params for McASP with FIFO has been updated so that it works for
various FIFO levels. A member- 'fifo_level' has been added to the DMA
params data structure. The fifo_level can be adjusted by the tx[rx]_numevt
platform data. This is relevant only for DA8xx/OMAP-L1xx platforms. This
implementation has been tested for numevt values 1, 2, 4, 8.
Signed-off-by: Chaithrika U S <chaithrika@ti.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Add DAI format definition for PDM interfaces.
Signed-off-by: Misael Lopez Cruz <x0052729@ti.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
When running in TDM mode there can be more than 2 channels used. Datasheet has
figures for upto 8 channels so increase max_channels on all SSP interfaces to
this figure.
Signed-off-by: Graeme Gregory <dp@xora.org.uk>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
McASP write FIFO registers should be modified for playback and read FIFO
registers for capture. Check the PCM mode before manipulating the
FIFO registers. Currently, irrespective of playback/capture both the
FIFOs are enabled or disbaled. This resulted in errors in audio loopback
mode.
Signed-off-by: Chaithrika U S <chaithrika@ti.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
This patch removes references to cpu_dai->dma_data.
It makes struct davinci_pcm_dma_params part of
struct davinci_mcbsp_dev or struct davinci_audio_dev.
It removes the unused name variable from davinci_pcm_dma_params.
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
When both playback and capture stream were open
davinci_i2s_hw_params was setting parameters for
the wrong stream. The fix for davinci_i2s_hw_params
is sufficient, but it looks like a race still happens
in davici_pcm_open. This patch also makes the race smaller
but the next patch provides a better fix.
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: Cliff Cai <cliff.cai@analog.com>
Signed-off-by: Barry Song <barry.song@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Since the active field of the dai already tells us the stream activity,
the local counter variable is redundant and can be replaced.
Signed-off-by: Barry Song <barry.song@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
When MONOMIX is set to Stereo, Left PGA was not powered on but should be.
Add a mapping from Capture Left Mux to Capture Left Mixer to fix the issue.
Signed-off-by: Phil Vandry <vandry@TZoNE.ORG>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
1. delete redundant assignment to bus field in spi_driver structure
2. fix lost assignment to set_bias_level entry in ad1938 codec dai
3. change spi driver name of ad1836 from "ad1836-spi" to "ad1836"
Signed-off-by: Barry Song <barry.song@analog.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
New machine driver for WM8580 I2S i/f on SMDK64XX.
By default SoC-Slave is set and WM8580 is configured to use it's
PLLA to generate clocks from a 12MHz crystal attached to WM8580.
[Added dependency on BROKEN since the IISv4 interface hasn't been merged
yet, fixed the PLL API usage and removed the disabling of the PLL in the
hw_free function since that'll break simultaneous playback and record
-- broonie.]
Signed-off-by: Jassi <jassi.brar@samsung.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Instead of always returnig pointer to the 'audio-bus' clock,
check which clock is used to generate internal clocks and
then return it's pointer.
Signed-off-by: Jassi <jassi.brar@samsung.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
McASP register settings are not correct for DSP mode of operation.
There is a channel swap initally. This patch provides fixes to
the register values for proper working.
Tested on DA830/OMAP-L137 EVM, DM6467 EVM.
Signed-off-by: Chaithrika U S <chaithrika@ti.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
If the sound system hasn't been utilized yet and we suspend, then we
attempt to save/restore using state that doesn't exist. So use a global
handle instead to reconfigure properly.
Signed-off-by: Cliff Cai <cliff.cai@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Commit dc7d7b830e trimmed the platform_device parameter from all of the
suspend functions, but it also accidentally removed it from the resume
function in the Blackfin I2S driver. So restore it.
Signed-off-by: Barry Song <barry.song@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: Barry Song <barry.song@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Somewhere along the line, most of SND_BF5XX_MULTICHAN_SUPPORT handling was
merged, but two places were missed (the probe/resume functions). Restore
handling of this option so it gets initialized properly.
Signed-off-by: Cliff Cai <cliff.cai@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
CDCLK can either be an output generated by the CPU, intended for use
as the CODEC master clock, or an input (probably from the CODEC)
providing a master clock for the IIS block.
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
This patch enables tlv320aic3101 support on DM365 EVM and
it was tested on DM365 EVM rev c.
Note: this patch was created based on temp/asoc branch.
Signed-off-by: Miguel Aguilar <miguel.aguilar@ridgerun.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
1) Explicitly set LRCLK polarity for I2S Vs LSM/MSB modes.
2) Convert from numerical to bit-field values for BCLK selection.
3) Use proper error checking for return value from clk_get
Signed-off-by: Jassi <jassi.brar@samsung.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
s3c2412_snd_lrsync() maybe reached with IRQs disabled and if LRCLK
is dead due to improper initialization of CPU or CODEC, the system
gets stuck in the loop because jiffies may never get updated.
Implemented counter based wait mechanism for atleast the same
timeout period.
Signed-off-by: Jassi <jassi.brar@samsung.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
The patch adds an interface to set the relationship between audio
channel number and slot number. The interface should be really useful
because audio channel n doesn't always use slot n in all platforms. And
for some devices, the relationship even can change with sound mode
switch in 2.1,3.1,4.1,5.1,6.1,7.1 etc.
Signed-off-by: Barry Song <21cnbao@gmail.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Error handling code following a kzalloc should free the allocated data.
Error handling code following an ioremap should iounmap the allocated data.
The semantic match that finds the first problem is as follows:
(http://www.emn.fr/x-info/coccinelle/)
// <smpl>
@r exists@
local idexpression x;
statement S;
expression E;
identifier f,f1,l;
position p1,p2;
expression *ptr != NULL;
@@
x@p1 = \(kmalloc\|kzalloc\|kcalloc\)(...);
...
if (x == NULL) S
<... when != x
when != if (...) { <+...x...+> }
(
x->f1 = E
|
(x->f1 == NULL || ...)
|
f(...,x->f1,...)
)
...>
(
return \(0\|<+...x...+>\|ptr\);
|
return@p2 ...;
)
@script:python@
p1 << r.p1;
p2 << r.p2;
@@
print "* file: %s kmalloc %s return %s" % (p1[0].file,p1[0].line,p2[0].line)
// </smpl>
Signed-off-by: Julia Lawall <julia@diku.dk>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
The AK4671 is a stereo CODEC with a built-in Microphone-Amplifier,
Receiver-Amplifier and Headphone-Amplifier.
The datasheet for the ak4671 can find at the following url:
http://www.asahi-kasei.co.jp/akm/en/product/ak4671/ak4671_f01e.pdf
Signed-off-by: Joonyoung Shim <jy0922.shim@samsung.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Some chips with complex internal supply (particularly clocking)
arragements may have multiple options for some of the supply
connections. Since these don't affect user-visible audio routing
the expectation would be that they would be managed automatically
by one of the drivers.
Support these users by allowing routes to have a connected function
which is queried before the connectedness of the path is checked as
normal. Currently this is only done for supplies, other widgets
could be supported but are not currently since the expectation for
them is that audio routing will be under the control of userspace.
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
This patch fixes the following bugs:
- only reprogram bitdepth if it has changed since last call to hw_params.
- add locking inside ac97_read/write functions:
When reprogramming sample depth, the ac97 unit has to be disabled,
which should not be done in the middle of codec register accesses.
- retry timed-out codec register accesses.
- wait for status bits to set/clear when starting/stopping various
functional blocks; very important after reenabling AC97 unit else
sound may be distorted (e.g. high-pitch noise in 1kHz sine wave).
- clear fifos before/after starting/stopping RX/TX.
- longer timeouts waiting for PSC/AC97 ready after cold reset
with certain codecs this can take ridiculous amounts of time.
Run-tested on various Au1200 platforms with various codecs.
Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
It's the 8th enum of a zero indexed array. This is why I don't let
new drivers use these arrays of enums...
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Cc: stable@kernel.org
This patch is for the AK4671 codec driver using this format.
Signed-off-by: Joonyoung Shim <jy0922.shim@samsung.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
More and more devices feature PLLs and FLLs with the ability to select
between multiple input clocks. In order to better support these devices
a new argument, source, has been added to the set_pll() configuration
API. Using set_clkdiv() is often difficult due to the need to stop the
PLL/FLL before any reconfiguration can be done.
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Today's linux-next fails to build with
sound/arm/pxa2xx-ac97.c: In function 'pxa2xx_ac97_probe':
sound/arm/pxa2xx-ac97.c:211: error: 'pxa2xx_audio_ops_t' has no member named 'codec_data'
make[2]: *** [sound/arm/pxa2xx-ac97.o] Error 1
It looks like commit e2365bf313 has
introduced this; patch below.
Signed-off-by: Robert Schwebel <r.schwebel@pengutronix.de>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Avoids potential issues if we read back unexpected values during
a read/modify/write cycle.
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Bug was caught while trying to use WM8580 as I2S master on SMDK.
Symptoms were lesser LRCLK read by CRO(41.02 instead of 44.1 KHz) Solved
by referring to WM8580A manual and setting mask value correctly and
making the code to not touch 'reserved' bits of PLL4 register.
Signed-off-by: Jassi <jassi.brar@samsung.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
As discussed, the patch uses the original TDM order without rewriting.
For the match between TDM slot number and audio channel number, a new
API need be added.
Signed-off-by: Barry Song <21cnbao@gmail.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
The McBSP1 port in OMAP3 processors (I believe OMAP2 too but I don't have
specifications to check it) have additional CLKR and FSR pins for McBSP1
receiver. Reset default is that receiver is using bit clock and frame
sync signal from those pins but it is possible to configure to use
also CLKX and FSX pins as well. In fact, other McBSP ports are doing that
internally that transmitter and receiver share the CLKX and FSX.
Add functionaly that machine drivers can set the CLKR and FSR sources by
using the snd_soc_dai_set_sysclk.
Thanks to "Aggarwal, Anuj" <anuj.aggarwal@ti.com> for reporting the issue.
Signed-off-by: Jarkko Nikula <jhnikula@gmail.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Also, the codec setup data structure has to remain for successful
probe.
Signed-off-by: Chaithrika U S <chaithrika@ti.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
If the requested FLL configuration is the one we're currently running
in it's at best pointless to reconfigure the FLL.
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Now that we don't need the I2C address for the device the platform data
is redundant so allow it to be omitted.
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Tested-by: Chaithrika U S <chaithrika@ti.com>
No point in building them for S3C64xx, certainly no sense in running
into build issues there.
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
