Commit Graph

15307 Commits

Author SHA1 Message Date
Russell King
34471a9168 Merge branch 'ppi-irq-core-for-rmk' of git://github.com/mzyngier/arm-platforms into devel-stable 2011-10-23 14:42:30 +01:00
Marc Zyngier
28af690a28 ARM: gic, local timers: use the request_percpu_irq() interface
This patch remove the hardcoded link between local timers and PPIs,
and convert the PPI users (TWD, MCT and MSM timers) to the new
*_percpu_irq interface. Also some collateral cleanup
(local_timer_ack() is gone, and the interrupt handler is strictly
private to each driver).

PPIs are now useable for more than just the local timers.

Additional testing by David Brown (msm8250 and msm8660) and
Shawn Guo (imx6q).

Cc: David Brown <davidb@codeaurora.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Acked-by: David Brown <davidb@codeaurora.org>
Tested-by: David Brown <davidb@codeaurora.org>
Tested-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2011-10-23 13:32:33 +01:00
Marc Zyngier
292b293cee ARM: gic: consolidate PPI handling
PPI handling is a bit of an odd beast. It uses its own low level
handling code and is hardwired to the local timers (hence lacking
a registration interface).

Instead, switch the low handling to the normal SPI handling code.
PPIs are handled by the handle_percpu_devid_irq flow.

This also allows the removal of some duplicated code.

Cc: Kukjin Kim <kgene.kim@samsung.com>
Cc: David Brown <davidb@codeaurora.org>
Cc: Bryan Huntsman <bryanh@codeaurora.org>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Paul Mundt <lethal@linux-sh.org>
Cc: Magnus Damm <magnus.damm@gmail.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Acked-by: David Brown <davidb@codeaurora.org>
Tested-by: David Brown <davidb@codeaurora.org>
Tested-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2011-10-23 13:32:29 +01:00
Russell King
a06f916b7a ARM: smp: fix clipping of number of CPUs
Rather than clipping the number of CPUs using the compile-time NR_CPUS
constant, use the runtime nr_cpu_ids value instead.  This allows the
nr_cpus command line option to work as expected.

Cc: <stable@kernel.org>
Reported-by: Mark Salter <msalter@redhat.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-10-20 22:06:57 +01:00
Russell King
cefd3e71ef Merge branch 'mach_memory_h' of git://git.linaro.org/people/nico/linux into devel-stable 2011-10-18 13:40:54 +01:00
Jamie Iles
5a567d78c4 ARM: 7115/4: move __exception and friends to asm/exception.h
The definition of __exception_irq_entry for
CONFIG_FUNCTION_GRAPH_TRACER=y needs linux/ftrace.h, but this creates a
circular dependency with it's current home in asm/system.h. Create
asm/exception.h and update all current users.

v4:	- rebase to rmk/for-next
v3:	- remove redundant includes of linux/ftrace.h
v2:	- document the usage restricitions of __exception*

Cc: Zoltan Devai <zdevai@gmail.com>
Signed-off-by: Jamie Iles <jamie@jamieiles.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-10-17 09:02:44 +01:00
Shawn Guo
0af8aa0069 ARM: 7124/1: smp: Add a localtimer handler callable from C code
In order to be able to handle localtimer directly from C code instead of
assembly code, introduce handle_local_timer(), which is modeled after
handle_IRQ().

Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-10-17 09:02:44 +01:00
Shawn Guo
0b5a1b95dc ARM: 7123/1: smp: Add an IPI handler callable from C code
In order to be able to handle IPI directly from C code instead of
assembly code, introduce handle_IPI(), which is modeled after handle_IRQ().

Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-10-17 09:02:43 +01:00
Shawn Guo
26a527e69d ARM: 7100/1: smp_scu: remove __init annotation from scu_enable()
When Cortex-A9 MPCore resumes from Dormant or Shutdown modes,
SCU needs to be re-enabled.  This patch removes __init annotation
from function scu_enable(), so that platform resume procedure can
call it to re-enable SCU.

Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-10-17 09:02:43 +01:00
Will Deacon
267840f339 ARM: 7061/1: gic: convert logical CPU numbers into physical numbers
The GIC driver must convert logical CPU numbers passed in from Linux
into physical CPU numbers that are understood by the hardware.

This patch uses the new cpu_logical_map macro for performing the
conversion inside the GIC driver.

Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-10-17 09:02:43 +01:00
Will Deacon
d6257288c4 ARM: 7060/1: smp: populate logical CPU mapping during boot
To allow booting Linux on a CPU with physical ID != 0, we need to
provide a mapping from the logical CPU number to the physical CPU
number.

This patch adds such a mapping and populates it during boot.

Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-10-17 09:02:43 +01:00
Vincent Guittot
c9018aab8e ARM: 7011/1: Add ARM cpu topology definition
The affinity between ARM processors is defined in the MPIDR register.
We can identify which processors are in the same cluster,
and which ones have performance interdependency. We can define the
cpu topology of ARM platform, that is then used by sched_mc and sched_smt.

The default state of sched_mc and sched_smt config is disable.
When enabled, the behavior of the scheduler can be modified with
sched_mc_power_savings and sched_smt_power_savings sysfs interfaces.

Changes since v4 :
*  Remove unnecessary parentheses and blank lines

Changes since v3 :
* Update the format of printk message
* Remove blank line

Changes since v2 :
* Update the commit message and some comments

Changes since v1 :
* Update the commit message
* Add read_cpuid_mpidr in arch/arm/include/asm/cputype.h
* Modify header of arch/arm/kernel/topology.c
* Modify tests and manipulation of MPIDR's bitfields
* Modify the place and dependancy of the config
* Modify Noop functions

Signed-off-by: Vincent Guittot <vincent.guittot@linaro.org>
Reviewed-by: Amit Kucheria <amit.kucheria@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-10-17 09:02:43 +01:00
Nicolas Pitre
0cdc8b921d ARM: switch from NO_MACH_MEMORY_H to NEED_MACH_MEMORY_H
Given that we want the default to not have any <mach/memory.h> and given
that there are now fewer cases where it is still provided than the cases
where it is not at this point, this makes sense to invert the logic and
just identify the exception cases.

The word "need" instead of "have" was chosen to construct the config
symbol so not to suggest that having a mach/memory.h file is actually
a feature that one should aim for.

Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
2011-10-13 12:53:53 -04:00
Nicolas Pitre
48de58e34e ARM: mach-s5p64x0: remove mach/memory.h
Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
2011-10-13 12:49:52 -04:00
Nicolas Pitre
b4be3999d1 ARM: mach-s3c64xx: remove mach/memory.h
Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
2011-10-13 12:49:51 -04:00
Nicolas Pitre
c039bad00f ARM: plat-mxc: remove mach/memory.h
Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
2011-10-13 12:49:50 -04:00
Nicolas Pitre
17dea45adb ARM: mach-prima2: remove mach/memory.h
Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
2011-10-13 12:49:50 -04:00
Nicolas Pitre
f431eb6960 ARM: mach-zynq: remove mach/memory.h
Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
2011-10-13 12:49:49 -04:00
Nicolas Pitre
0e79671e13 ARM: mach-bcmring: remove mach/memory.h
Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
2011-10-13 12:49:48 -04:00
Nicolas Pitre
0020afb369 ARM: mach-davinci: remove mach/memory.h
Move some DDR2 related defines into a private <mach/ddr2.h> beforehand.

Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
2011-10-13 12:49:47 -04:00
Nicolas Pitre
f4220feb35 ARM: mach-pxa: remove mach/memory.h
Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
2011-10-13 12:49:47 -04:00
Nicolas Pitre
3bc465aab0 ARM: mach-ixp4xx: remove mach/memory.h
Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
2011-10-13 12:49:46 -04:00
Nicolas Pitre
2e5df8d28a ARM: mach-h720x: remove mach/memory.h
Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
2011-10-13 12:49:45 -04:00
Nicolas Pitre
e41fa86e55 ARM: mach-vt8500: remove mach/memory.h
Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
2011-10-13 12:49:44 -04:00
Nicolas Pitre
476eb37ad7 ARM: mach-s5pc100: remove mach/memory.h
Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
2011-10-13 12:49:43 -04:00
Nicolas Pitre
f8bc5ddf13 ARM: mach-tegra: remove mach/memory.h
Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
2011-10-13 12:49:43 -04:00
Nicolas Pitre
3044454779 ARM: plat-tcc: remove mach/memory.h
Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
2011-10-13 12:49:42 -04:00
Nicolas Pitre
9b15e4fe00 ARM: mach-mmp: remove mach/memory.h
Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
2011-10-13 12:49:41 -04:00
Nicolas Pitre
17108711c5 ARM: mach-cns3xxx: remove mach/memory.h
Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
2011-10-13 12:49:40 -04:00
Nicolas Pitre
6b1f1005f3 ARM: mach-nuc93x: remove mach/memory.h
Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
2011-10-13 12:49:40 -04:00
Nicolas Pitre
a109d811ba ARM: mach-mxs: remove mach/memory.h
Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
2011-10-13 12:49:39 -04:00
Nicolas Pitre
94cc0a7847 ARM: spear: remove mach/memory.h and plat/memory.h
Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
2011-10-13 12:49:38 -04:00
Nicolas Pitre
9d25544968 ARM: mach-msm: remove mach/memory.h
Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
2011-10-13 12:49:37 -04:00
Nicolas Pitre
d8c9e024e3 ARM: mach-gemini: remove mach/memory.h
Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
2011-10-13 12:49:37 -04:00
Nicolas Pitre
bf45bd7687 ARM: mach-lpc32xx: remove mach/memory.h
Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
2011-10-13 12:49:36 -04:00
Nicolas Pitre
ff4067e4cf ARM: mach-netx: remove mach/memory.h
Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
2011-10-13 12:49:35 -04:00
Nicolas Pitre
2f93c8885b ARM: mach-versatile: remove mach/memory.h
Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
2011-10-13 12:49:34 -04:00
Nicolas Pitre
6d3f8b40f4 ARM: mach-ux500: remove mach/memory.h
Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
2011-10-13 12:49:33 -04:00
Nicolas Pitre
6b0e7f69ad ARM: mach-nomadik: remove mach/memory.h
Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
2011-10-13 12:49:33 -04:00
Nicolas Pitre
489a1b5b89 ARM: mach-iop32x: remove mach/memory.h
Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
2011-10-13 12:49:32 -04:00
Nicolas Pitre
b890f6b59d ARM: mach-pnx4008: remove mach/memory.h
Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
2011-10-13 12:49:31 -04:00
Nicolas Pitre
f29781ac69 ARM: mach-w90x900: remove mach/memory.h
Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
2011-10-13 12:49:30 -04:00
Nicolas Pitre
34561b557f ARM: mach-vexpress: remove mach/memory.h
Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
2011-10-13 12:49:29 -04:00
Nicolas Pitre
e2c72ff9dc ARM: mach-mv78xx0: remove mach/memory.h
Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
2011-10-13 12:49:29 -04:00
Nicolas Pitre
8b5da2df27 ARM: mach-s3c2410: remove memory.h
This also removes the mach/s3c2400 version which was probably never used
due to the fact that we have this line in arch/arm/Makefile:

machine-$(CONFIG_ARCH_S3C2410)          := s3c2410 s3c2400 [...]

This is later used to construct the search path for:

The compiler would be looking into mach-s3c2410 and picking up this
version first.  Any config that was actually expecting the mach-s3c2400
version was therefore producing a broken kernel binary.  Not relying on
any of them anymore would fix that issue.

Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
2011-10-13 12:49:27 -04:00
Will Deacon
a26bce1220 ARM: 7127/1: hw_breakpoint: skip v7-specific reset on v6 cores
ARMv6 cores do not implement the DBGOSLAR register, so we don't need to
try and clear it on boot. Furthermore, the VCR is zeroed out of reset,
so we don't need to zero it explicitly when a CPU comes online.

Tested-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-10-08 10:05:34 +01:00
Nicolas Pitre
8cfc1ef96a ARM: mach-iop33x: remove mach/memory.h
Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
2011-09-26 10:12:04 -04:00
Nicolas Pitre
7743a08764 ARM: mach-omap2: remove mach/memory.h
Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
Acked-by: Tony Lindgren <tony@atomide.com>
2011-09-26 10:12:03 -04:00
Nicolas Pitre
ee581ae83f ARM: OMAP: move OMAP1 memory config from plat/memory.h to its mach/memory.h
Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
Acked-by: Tony Lindgren <tony@atomide.com>
2011-09-26 10:12:02 -04:00
Nicolas Pitre
8fce8b2080 ARM: mach-orion5x: remove mach/memory.h
Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
2011-09-26 10:12:01 -04:00