Commit Graph

1058818 Commits

Author SHA1 Message Date
Hector Martin
42c2366a9c dt-bindings: pci: apple,pcie: Add t6000 support
This new SoC is compatible with the existing driver, but the block
supports 4 downstream ports, so we need to adjust the binding to
allow that.

Reviewed-by: Mark Kettenis <kettenis@openbsd.org>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Hector Martin <marcan@marcan.st>
2021-12-12 10:33:05 +09:00
Hector Martin
b66652c751 dt-bindings: i2c: apple,i2c: Add apple,t6000-i2c compatible
This block is compatible with t8103, so just add the new per-SoC
compatible under apple,i2c.

Reviewed-by: Mark Kettenis <kettenis@openbsd.org>
Reviewed-by: Sven Peter <sven@svenpeter.dev>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Hector Martin <marcan@marcan.st>
2021-12-12 10:33:00 +09:00
Hector Martin
e15b8c8563 dt-bindings: arm: apple: Add t6000/t6001 MacBook Pro 14/16" compatibles
This adds the initial apple,t6000 platforms:

- apple,j314s - MacBook Pro (14-inch, M1 Pro, 2021)
- apple,j316s - MacBook Pro (16-inch, M1 Pro, 2021)

And the initial apple,t6001 platforms:

- apple,j314c - MacBook Pro (14-inch, M1 Max, 2021)
- apple,j316c - MacBook Pro (16-inch, M1 Max, 2021)

Reviewed-by: Mark Kettenis <kettenis@openbsd.org>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Hector Martin <marcan@marcan.st>
2021-12-12 10:32:50 +09:00
Hector Martin
34e5719e1c arm64: dts: apple: t8103: Add apple,min-state to DCP PMGR nodes
This is required for DCP to boot successfully; it seems if power gating
is allowed, they do not wake up properly.

Reviewed-by: Sven Peter <sven@svenpeter.dev>
Signed-off-by: Hector Martin <marcan@marcan.st>
2021-12-12 10:25:40 +09:00
Hector Martin
d824dade33 dt-bindings: power: apple,pmgr-pwrstate: Add apple,min-state prop
A few devices (DCP/DCPEXT) need to have the minimum power state for
auto-PM configured. Add a property that allows the DT to specify this
value.

Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Hector Martin <marcan@marcan.st>
2021-12-12 10:25:22 +09:00
Nicolas Frattaroli
ea1847c09c arm64: dts: rockchip: Add spi1 pins on Quartz64 A
The Quartz64 Model A has the SPI pins broken out on its pin
header. The actual pins being used though are not the m0
variant, but the m1 variant, which also lacks the cs1 pin.

This commit overrides pinctrl-0 accordingly for this board.

spi1 is intentionally left disabled, as anyone wishing to add
SPI devices needs to edit the dts anyway, and the pins are more
useful as GPIOs for the rest of the users.

Signed-off-by: Nicolas Frattaroli <frattaroli.nicolas@gmail.com>
Link: https://lore.kernel.org/r/20211127141910.12649-4-frattaroli.nicolas@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2021-12-11 11:59:12 +01:00
Nicolas Frattaroli
aaa552d845 arm64: dts: rockchip: Add spi nodes on rk356x
This adds the four spi nodes (spi0, spi1, spi2, spi3) to the
rk356x dtsi. These are from the downstream device tree, though
I have double-checked that their interrupts and DMA numbers are
correct. I have also tested spi1 with an SPI device.

Signed-off-by: Nicolas Frattaroli <frattaroli.nicolas@gmail.com>
Link: https://lore.kernel.org/r/20211127141910.12649-3-frattaroli.nicolas@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2021-12-11 11:59:11 +01:00
Sascha Hauer
2e4dbcf717 arm64: dts: rockchip: Change pwm pinctrl-name to "default" on rk356x
The pinctrl state "active" is neither documented nor used by the PWM
driver. Rename it to "default"

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Link: https://lore.kernel.org/r/20211208120312.3300390-1-s.hauer@pengutronix.de
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2021-12-11 11:47:47 +01:00
Thierry Reding
fa0fdb78cb ARM: dts: am335x: Use correct vendor prefix for Asahi Kasei Corp.
The old "ak" vendor prefix that was never officially accepted was still
being used in some device trees. Convert to the correct vendor prefix
(i.e. "asahi-kasei").

Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2021-12-09 10:06:42 +02:00
Geert Uytterhoeven
7ebe6e99f7 ARM: dts: motorola-mapphone: Drop second ti,wlcore compatible value
The TI wlcore DT bindings specify using a single compatible value for
each variant, and the Linux kernel driver matches against the first
compatible value since commit 078b30da3f ("wlcore: add wl1285
compatible") in v4.13.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2021-12-09 10:06:42 +02:00
Miquel Raynal
6fde719b19 ARM: dts: am437x-gp-evm: enable ADC1
ADC0 and ADC1 pins are available on external connector J22.

Enable ADC1 which was missing.

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2021-12-09 10:06:42 +02:00
Miquel Raynal
6c06a9f55b ARM: dts: am43xx: Describe the magnetic reader/ADC1 hardware module
This hardware module is close to the am33xx ADC module but instead of
featuring a touchscreen it has a magnetic reader capability.

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2021-12-09 10:06:42 +02:00
Miquel Raynal
d2e8a6c43b ARM: dts: am437x-cm-t43: Use a correctly spelled DT property
Back in 2014 a property got misspelled "ti,coordiante-readouts" instead
of "ti,coordinate-readouts".

The year after it got fixed but both are still supported, although this
is not a reason to continue using this old deprecated property.

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2021-12-09 10:06:42 +02:00
Drew Fustini
1e72c64eb7 ARM: dts: am335x-icev2: Add system-power-controller to RTC node
On the am335x-icev2 board [1], AM3359 PMIC_PWR_EN (ZCZ ball C6) is
connected to PWRHOLD (pin 1) on the TPS65910A3 PMIC. The addition of
system-power-controller to the rtc node will enable the capability of
the RTC driver to poweroff the board.

Based on commit 15c7be47fb7c ("ARM: dts: am335x: Add rtc node as
system-power-controller") by Keerthy in ti-linux-5.4.y branch [2].

[1] https://www.ti.com/tool/TMDSICE3359
[2] git://git.ti.com/ti-linux-kernel/ti-linux-kernel.git

Cc: Dave Gerlach <d-gerlach@ti.com>
Cc: Keerthy <j-keerthy@ti.com>
Link: https://lore.kernel.org/linux-omap/20211012191311.879838-1-dfustini@baylibre.com/
Suggested-by: Johan Hovold <johan@kernel.org>
Signed-off-by: Drew Fustini <dfustini@baylibre.com>
Reviewed-by: Johan Hovold <johan@kernel.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2021-12-09 10:06:41 +02:00
Drew Fustini
f3499b1329 ARM: dts: am335x-boneblack-common: move system-power-controller
Move the rtc node system-power-controller property from
am335x-boneblack-common.dtsi to am335x-bone-common.dtsi.

am335x-boneblack-common.dtsi is included by am335x-boneblack.dts,
am335x-boneblack-wireless.dts, am335x-sancloud-bbe.dts and
am335x-sancloud-bbe-lite.dts. All of these dts files also include
am335x-bone-common.dtsi and thus will retain the rtc node
system-power-controller property.

am335x-bone-common.dtsi is also included by am335x-bone.dts [1],
am335x-bonegreen.dts [2] and am335x-bonegreen-wireless.dts [3]. These
boards will now have the rtc node system-power-controller property too.
This is valid as they also have PMIC_POWR_EN (ZCZ C6) connected to
PWR_EN on the TPS65217B PMIC.

Based on commit 15c7be47fb7c ("ARM: dts: am335x: Add rtc node as
system-power-controller") by Keerthy in ti-linux-5.4.y branch [4].

[1] https://beagleboard.org/static/beaglebone/BEAGLEBONE_SCHEM_A3.pdf
[2] https://github.com/SeeedDocument/BeagleBone_Green/blob/master/resources/BEAGLEBONE_GREEN_V1.pdf
[3] https://github.com/SeeedDocument/BeagleBone_Green_Wireless/blob/master/resources/BeagleBone_Green%20Wireless_V1.0_SCH_20160314.pdf
[4] git://git.ti.com/ti-linux-kernel/ti-linux-kernel.git

Cc: Jason Kridner <jkridner@beagleboard.org>
Cc: Dave Gerlach <d-gerlach@ti.com>
Cc: Keerthy <j-keerthy@ti.com>
Link: https://lore.kernel.org/linux-omap/20211012191311.879838-1-dfustini@baylibre.com/
Suggested-by: Johan Hovold <johan@kernel.org>
Reviewed-by: Johan Hovold <johan@kernel.org>
Signed-off-by: Drew Fustini <dfustini@baylibre.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2021-12-09 10:06:41 +02:00
Dmitry Osipenko
36b88b2095 ARM: dts: elpida_ecb240abacn: Change Elpida compatible
Vendor prefix shouldn't start with capital letter. The Elpida Memory
compatible was never used in practice, hence just correct the compatible.

Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2021-12-09 09:11:10 +02:00
Oleksij Rempel
b3111fe15d ARM: dts: at91: add Microchip EVB-KSZ9477 board
Add KSZ9477 managed switch evaluation kit with SAMA5D36 MPU:
https://www.microchip.com/en-us/development-tool/evb-ksz9477

Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de>
Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Link: https://lore.kernel.org/r/20211111081045.711323-1-o.rempel@pengutronix.de
2021-12-08 14:05:16 +01:00
Mihai Sain
6d4518a086 ARM: dts: at91: sama5d2_xplained: remove PA11__SDMMC0_VDDSEL from pinctrl
I/O voltage for eMMC is always 3.3V because PA11__SDMMC0_VDDSEL is
tied with 10K resistor to GND. U13 switch S1 is always selected as
voltage rail of 3.3V for VCCQ power pin from MPU controller and eMMC flash.
Removing PA11 from pinctrl because it remains unused.

Signed-off-by: Mihai Sain <mihai.sain@microchip.com>
Reviewed-by: Eugen Hristev <eugen.hristev@microchip.com>
Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Link: https://lore.kernel.org/r/20211026132034.678655-1-eugen.hristev@microchip.com
2021-12-08 14:04:52 +01:00
Michal Vokáč
0de4ab81ab ARM: dts: imx6dl-yapp4: Add Y Soft IOTA Crux/Crux+ board
Add devicetrees for the new boards in the Y Soft IOTA family.
These boards are based on Orion but use Quad/QuadPlus SoC
instead of DualLite.

Signed-off-by: Michal Vokáč <michal.vokac@ysoft.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-12-08 20:31:54 +08:00
Joakim Zhang
44d0dfee53 arm64: dts: imx8mp: add mac address for EQOS
Add mac address in efuse, so that EQOS driver can parse it from nvmem
cell.

Signed-off-by: Joakim Zhang <qiangqing.zhang@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-12-08 20:25:24 +08:00
Joakim Zhang
baf55c1509 arm64: dts: imx8m: remove unused "nvmem_macaddr_swap" property for FEC
Remove unused "nvmem_macaddr_swap" property for FEC, there is no info in both
dt-binding and driver, so it's safe to remove it.

Reviewed-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Joakim Zhang <qiangqing.zhang@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-12-08 20:25:24 +08:00
Joakim Zhang
311ad460c4 arm64: dts: imx8mp-evk: disable CLKOUT clock for ENET PHY
According to commit 0a4355c2b7 ("net: phy: realtek: add dt property to
disable CLKOUT clock"), diable CLKOUT clock for FEC PHY to save power on
i.MX8MP EVK board.

Signed-off-by: Joakim Zhang <qiangqing.zhang@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-12-08 20:25:24 +08:00
Joakim Zhang
09e5ccdd86 arm64: dts: imx8m: configure FEC PHY VDDIO voltage
As commit 2f664823a4 ("net: phy: at803x: add device tree binding")
described, configure FEC PHY VDDIO voltage according to board design.

Signed-off-by: Joakim Zhang <qiangqing.zhang@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-12-08 20:25:24 +08:00
Joakim Zhang
20b6559ecf arm64: dts: imx8m: disable smart eee for FEC PHY
As commit 390b4cad81 ("net: phy: at803x: add support for configuring SmartEEE")
described, disable PHY smart eee by default.

Signed-off-by: Joakim Zhang <qiangqing.zhang@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-12-08 20:25:24 +08:00
Joakim Zhang
e0aa402b40 arm64: dts: imx8mp-evk: add hardware reset for EQOS PHY
As commit 798a1807ab ("arm64: dts: imx8mp-evk: Improve the Ethernet PHY
description") described, add hardware reset for EQOS PHY.

Signed-off-by: Joakim Zhang <qiangqing.zhang@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-12-08 20:25:24 +08:00
Joakim Zhang
6133d84228 arm64: dts: imx8mn-evk: add hardware reset for FEC PHY
Add hardware reset for FEC PHY.

Signed-off-by: Joakim Zhang <qiangqing.zhang@nxp.com>
Reviewed-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-12-08 20:25:24 +08:00
Hari Prasath
12f332d2dd ARM: dts: at91: update alternate function of signal PD20
The alternate function of PD20 is 4 as per the datasheet of
sama7g5 and not 5 as defined earlier.

Signed-off-by: Hari Prasath <Hari.PrasathGE@microchip.com>
Fixes: 7540629e2f ("ARM: dts: at91: add sama7g5 SoC DT and sama7g5-ek")
Cc: <stable@vger.kernel.org> # v5.15+
Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Link: https://lore.kernel.org/r/20211208063553.19807-1-Hari.PrasathGE@microchip.com
2021-12-08 12:12:20 +01:00
Yoshihiro Shimoda
08b8699eb3 arm64: dts: renesas: Add Renesas Spider boards support
Initial support for the Renesas Spider CPU and BreakOut boards.

Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Tested-by: Takehito Nakamura <takehito.nakamura.nx@renesas.com>
Link: https://lore.kernel.org/r/20211201073308.1003945-14-yoshihiro.shimoda.uh@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-12-07 16:55:20 +01:00
Yoshihiro Shimoda
c62331e822 arm64: dts: renesas: Add Renesas R8A779F0 SoC support
Add initial support for the Renesas R8A779F0 (R-Car S4-8) SoC.

Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/r/20211201073308.1003945-13-yoshihiro.shimoda.uh@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-12-07 16:55:10 +01:00
Geert Uytterhoeven
35ae0d00ab Renesas R-Car S4-8 DT Binding Definitions
Clock and Power Domain definitions for the Renesas R-Car S4-8 (R8A77FA0)
 SoC, shared by driver and DT source files.
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Merge tag 'renesas-r8a779f0-dt-binding-defs-tag' into renesas-arm-dt-for-v5.17

Renesas R-Car S4-8 DT Binding Definitions

Clock and Power Domain definitions for the Renesas R-Car S4-8 (R8A77FA0)
SoC, shared by driver and DT source files.
2021-12-07 16:52:36 +01:00
Yoshihiro Shimoda
81c1655823 dt-bindings: clock: Add r8a779f0 CPG Core Clock Definitions
Add all Clock Pulse Generator Core Clock Outputs for the Renesas
R-Car S4-8 (R8A779F0) SoC.

Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/r/20211201073308.1003945-4-yoshihiro.shimoda.uh@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-12-07 16:29:25 +01:00
Yoshihiro Shimoda
500daa0e6b dt-bindings: power: Add r8a779f0 SYSC power domain definitions
Add power domain indices for R-Car S4-8 (r8a779f0).

Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/r/20211201073308.1003945-3-yoshihiro.shimoda.uh@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-12-07 16:29:24 +01:00
Yoshihiro Shimoda
d01986bec3 dt-bindings: arm: renesas: Document Renesas Spider boards
Add device tree bindings documentation for Renesas R-Car S4-8
Spider CPU and BreakOut boards.

Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/r/20211201073308.1003945-2-yoshihiro.shimoda.uh@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-12-07 16:27:13 +01:00
Kieran Bingham
82ce79391d arm64: dts: renesas: Fix thermal bindings
The binding node names for the thermal zones are not successfully
validated by the dt-schemas.

Fix the validation by changing from sensor-thermalN or thermal-sensor-N
to sensorN-thermal.  Provide node labels of the form sensorN_thermal to
ensure consistency with the other platform implementations.

Signed-off-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Link: https://lore.kernel.org/r/20211104224033.3997504-1-kieran.bingham+renesas@ideasonboard.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-12-07 15:51:27 +01:00
Hector Martin
111659c2a5 arm64: dts: apple: t8103: Remove PCIe max-link-speed properties
The driver doesn't support these, they shouldn't be in the SoC include
anyway, and we're now configuring this in the bootloader instead. This
also solves the j274 1G/10G Ethernet variant discrepancy, since that
will now be configured properly based on the dynamic ADT property.

Acked-by: Marc Zyngier <maz@kernel.org>
Signed-off-by: Hector Martin <marcan@marcan.st>
2021-12-07 23:43:35 +09:00
Aswath Govindraju
2f474da98c arm64: dts: ti: k3-am642-evm/sk: Add support for main domain mcan nodes in EVM and disable them on SK
AM642 EVM has two CAN connecters brought out from the two MCAN instances in
the main domain through transceivers. Add device tree nodes for
transceivers and set the required properties in the mcan device tree nodes,
in EVM device tree file.

On AM642 SK there are no connectors brought out for CAN. Therefore, disable
the mcan device tree nodes in the SK device tree file.

Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Apurva Nandan <a-nandan@ti.com>
Link: https://lore.kernel.org/r/20211122134159.29936-7-a-govindraju@ti.com
2021-12-07 19:33:09 +05:30
Aswath Govindraju
9c4441ad3d arm64: dts: ti: k3-am64-main: Add support for MCAN
Add Support for two MCAN controllers present on the am64x SOC. Both support
classic CAN messages as well as CAN-FD.

Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Apurva Nandan <a-nandan@ti.com>
Link: https://lore.kernel.org/r/20211122134159.29936-6-a-govindraju@ti.com
2021-12-07 19:33:09 +05:30
Faiz Abbas
87d60c4663 arm64: dts: ti: k3-j721e-common-proc-board: Add support for mcu and main mcan nodes
Add four MCAN nodes present on the common processor board and set a
maximum data rate of 5 Mbps. Disable all other nodes as they
are not brought out on the common processor board.

Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Apurva Nandan <a-nandan@ti.com>
Link: https://lore.kernel.org/r/20211122134159.29936-5-a-govindraju@ti.com
2021-12-07 19:33:09 +05:30
Faiz Abbas
4688a4fcb7 arm64: dts: ti: k3-j721e: Add support for MCAN nodes
Add support for 14 MCAN controllers in main domain and 2 MCAN controllers
present in mcu domain. All the MCAN controllers support classic CAN
messages as well as CAN_FD messages.

Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Apurva Nandan <a-nandan@ti.com>
Link: https://lore.kernel.org/r/20211122134159.29936-4-a-govindraju@ti.com
2021-12-07 19:33:09 +05:30
Aswath Govindraju
f533bb82de arm64: dts: ti: am654-base-board/am65-iot2050-common: Disable mcan nodes
AM654 base board and iot platforms do not have mcan instances pinned out.
Therefore, disable all the mcan instances.

Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Apurva Nandan <a-nandan@ti.com>
Link: https://lore.kernel.org/r/20211122134159.29936-3-a-govindraju@ti.com
2021-12-07 19:33:09 +05:30
Faiz Abbas
c3e4ea557d arm64: dts: ti: k3-am65-mcu: Add Support for MCAN
Add Support for two MCAN controllers present on the am65x SOC. Both support
classic CAN messages as well as CAN-FD.

Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Apurva Nandan <a-nandan@ti.com>
Link: https://lore.kernel.org/r/20211122134159.29936-2-a-govindraju@ti.com
2021-12-07 19:33:09 +05:30
Mark Kettenis
bf2c05b619 arm64: dts: apple: t8103: Expose PCI node for the WiFi MAC address
Expose the PCI node corresponding to the WiFi device and give it
a 'local-mac-address' property. The bootloader will update it
(m1n1 already has the required feature).

Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
Acked-by: Marc Zyngier <maz@kernel.org>
Signed-off-by: Hector Martin <marcan@marcan.st>
2021-12-07 13:41:32 +09:00
Hector Martin
2ba22cfeda arm64: dts: apple: t8103: Add UART2
This UART is connected to the debug port of the WLAN module. It is
mostly useless, but makes for a good test case for runtime-pm without
having to unbind the console from the main system UART.

Reviewed-by: Mark Kettenis <kettenis@openbsd.org>
Signed-off-by: Hector Martin <marcan@marcan.st>
2021-12-07 13:41:32 +09:00
Hector Martin
106ba3b48a arm64: dts: apple: t8103: Add PMGR nodes
This adds the two PMGR nodes and all known power state subnodes. Since
there are a large number of them, let's put them in a separate file to
include.

Reviewed-by: Sven Peter <sven@svenpeter.dev>
Signed-off-by: Hector Martin <marcan@marcan.st>
2021-12-07 13:41:32 +09:00
Hector Martin
c83eeec79f dt-bindings: arm: apple: Add apple,pmgr binding
The PMGR block in Apple Silicon SoCs is responsible for SoC power
management. There are two PMGRs in T8103, with different register
layouts but compatible registers. In order to support this as well
as future SoC generations with backwards-compatible registers, we
declare these blocks as syscons and bind to individual registers
in child nodes. Each register controls one SoC device.

The respective apple compatibles are defined in case device-specific
quirks are necessary in the future, but currently these nodes are
expected to be bound by the generic syscon driver.

Reviewed-by: Mark Kettenis <kettenis@openbsd.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Hector Martin <marcan@marcan.st>
2021-12-07 13:04:10 +09:00
Hector Martin
e8117f85b9 dt-bindings: power: Add apple,pmgr-pwrstate binding
This syscon child node represents a single SoC device controlled by the
PMGR block. This layout allows us to declare all device power state
controls (power/clock gating and reset) in the device tree, including
dependencies, instead of hardcoding it into the driver. The register
layout is uniform.

Each pmgr-pwrstate node provides genpd and reset features, to be
consumed by downstream device nodes.

Future SoCs are expected to use backwards compatible registers, and the
"apple,pmgr-pwrstate" represents any such interfaces (possibly with
additional features gated by the more specific compatible), allowing
them to be bound without driver updates. If a backwards incompatible
change is introduced in future SoCs, it will require a new compatible,
such as "apple,pmgr-pwrstate-v2".

Reviewed-by: Mark Kettenis <kettenis@openbsd.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Hector Martin <marcan@marcan.st>
2021-12-07 13:04:08 +09:00
Hector Martin
bd4d13ed21 MAINTAINERS: Add PMGR power state files to ARM/APPLE MACHINE
This covers the PMGR power state driver and its DT bindings,
as well as any other future stuff in drivers/soc/apple.

Signed-off-by: Hector Martin <marcan@marcan.st>
2021-12-07 13:04:07 +09:00
Sven Peter
9e9652862a dt-bindings: watchdog: Add Apple Watchdog
Apple SoCs come with a simple embedded watchdog. This watchdog is also
required in order to reset the SoC.

Reviewed-by: Mark Kettenis <kettenis@openbsd.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Sven Peter <sven@svenpeter.dev>
Reviewed-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Hector Martin <marcan@marcan.st>
2021-12-07 13:04:02 +09:00
Jagan Teki
3ff0810ffc ARM: dts: stm32: Add Engicam i.Core STM32MP1 C.TOUCH 2.0 10.1" OF
Engicam C.TOUCH 2.0 is an EDIMM compliant general purpose Carrier
board.

Genaral features:
- Ethernet 10/100
- Wifi/BT
- USB Type A/OTG
- Audio Out
- CAN
- 10" LVDS Panel (SN65DSI84 DSI-LVDS bridge on SoM)

i.Core STM32MP1 is an EDIMM SoM based on STM32MP157A from Engicam.

10.1" OF is a capacitive touch 10.1" Open Frame panel solutions.

i.Core STM32MP1 needs to mount on top of C.TOUCH 2.0 carrier with
pluged 10.1" OF for creating complete i.Core STM32MP1 C.TOUCH 2.0
10.1" Open Frame board.

Add support for it.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2021-12-06 09:31:05 +01:00
Jagan Teki
854b020b16 dt-bindings: arm: stm32: Add Engicam i.Core STM32MP1 C.TOUCH 2.0 10.1" OF
i.Core STM32MP1 is an EDIMM SoM based on STM32MP157A from Engicam.

C.TOUCH 2.0 is a general purpose carrier board with capacitive
touch interface support.

10.1" OF is a capacitive touch 10.1" Open Frame panel solutions.

i.Core STM32MP1 needs to mount on top of C.TOUCH 2.0 carrier with
pluged 10.1" OF for creating complete i.Core STM32MP1 C.TOUCH 2.0
10.1" Open Frame board.

Add bindings for it.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2021-12-06 09:31:05 +01:00