This matters to any sort of device that is wired to one of the CPU
interrupt pins on an SMP system. Typically the scenario is most easily
triggered with the count/compare timer interrupt where the same interrupt
number and thus irq_desc is used on each processor.
CPU A CPU B
do_IRQ()
generic_handle_irq()
handle_level_irq()
spin_lock(desc_lock)
set IRQ_INPROGRESS
spin_unlock(desc_lock)
do_IRQ()
generic_handle_irq()
handle_level_irq()
spin_lock(desc_lock)
IRQ_INPROGRESS set => bail out
spin_lock(desc_lock)
clear IRQ_INPROGRESS
spin_unlock(desc_lock)
In case of the cp0 compare interrupt this means the interrupt will be
acked and not handled or re-armed on CPU b, so there won't be any timer
interrupt until the count register wraps around.
With kernels 2.6.20 ... 2.6.23 we usually were lucky that things were just
working right on VSMP because the count registers are synchronized on
bootup so it takes something that disables interrupts for a long time on
one processor to trigger this one.
For scenarios where an interrupt is multicasted or broadcasted over several
CPUs the existing code was safe and the fix will break it. There is no
way to know in the interrupt controller code because it is abstracted from
the platform code. I think we do not have such a setup currently, so this
should be ok.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
The GNU `config.guess' uses "linux-gnu" as the canonical system name.
Fix the list of compiler prefixes checked to spell it correctly.
Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Adds a JR.HB after halting a TC, to ensure that the TC has really halted.
only modifies the TCSTATUS register when the TC is safely halted.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
We have no guarantee by the generic time code that the timer is stopped
when the ->next_event method is called. Modifying the Timer Initial Count
register while the timer is enabled has UNPREDICTABLE effect according to
the BCM1250/BCM1125/BCM1125H User Manual. So stop the timer before
reprogramming.
This is a paranoia fix; no ill effects have been observed previously.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
For the old minimum of a single tick a value of zero would be programmed
into the init value register which in the BCM1250/BCM1125/BCM1125H User
Manual in the Timer Special Cases section is documented to have
UNPREDICTABLE effect.
Observable sympthoms of this bug were hangs of several seconds on the
console during bootup and later if both dyntick and highres timer options
were activated.
In theory contiguous mode of the timers is also affected but in an act of
hopeless lack of realism I'll assume nobody will ever configure a KERNEL
for HZ > 500kHz but if so I leave that to evolution to sort out.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
The range of MIPS_CPU IRQ and the range of LASAT IRQ overlap.
Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Shadow register support would not possibly have worked on multicore
systems. The support code for it was also depending not on MIPS R2 but
VSMP or SMTC kernels even though it makes perfect sense with UP kernels.
SR sets are a scarce resource and the expected usage pattern is that
users actually hardcode the register set numbers in their code. So fix
the allocator by ditching it. Move the remaining CPU probe bits into
the generic CPU probe.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
iounmap if pci clock is over 33MHz. Cosmetic because the iomap() in this
case is just a bit of address magic.
Signed-off-by: Roel Kluin <12o3l@tiscali.nl>
Acked-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
The recent switch of the Sibyte SOCs from the processor specific cache
managment code in c-sb1.c to c-r4k.c lost this old hack
[MIPS] Hack for SB1 cache issues
Removing flush_icache_page a while ago broke SB1 which was using an empty
flush_data_cache_page function. This glues things well enough so a more
efficient but also more intrusive solution can be found later.
Signed-Off-By: Thiemo Seufer <ths@networkno.de>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
in the hope it was no longer needed. As it turns it still is so resurrect
it until there is a better solution.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
The Jazz machines have to use the PIT timer for dyntick and highresolution
kernels. This may break because currently just like i386 used to do MIPS
uses two separate spinlocks in the actual PIT code and the PC speaker
code. So switch to do it the same that x86 currently does PIT locking.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Fix ISA irq acknowledge.
Make r4030 clockevent code look like other mips clockevent code.
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Register A20R clockevent.
Remove PIT timer setup because it doesn't work
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
arch/mips/au1000/pb1200/irqmap.c:101: warning: ignoring return value of 'request_irq', declared with attribute warn_unused_result
And while at it a few coding style cleanups.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* Do not include unnecessary headers.
* Do not mention time.README.
* Do not mention mips_timer_ack.
* Make clocksource_mips static. It is now dedicated to c0_timer.
* Initialize clocksource_mips.read statically.
* Remove null_hpt_read.
* Remove an argument of plat_timer_setup. It is just a placeholder.
Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
When GDB writes a breakpoint into address area of inferior process the
kernel needs to invalidate the modified memory in the inferior which
is done by calling flush_cache_page which in turns calls
r4k_flush_cache_page and local_r4k_flush_cache_page for VSMP or SMTC
kernel via r4k_on_each_cpu().
As the VSMP and SMTC SMP kernels for 34K are running on a single shared
caches it is possible to get away without interprocessor function calls.
This optimization is implemented in r4k_on_each_cpu, so
local_r4k_flush_cache_page is only ever called on the local CPU.
This is where the following code in local_r4k_flush_cache_page() strikes:
/*
* If ownes no valid ASID yet, cannot possibly have gotten
* this page into the cache.
*/
if (cpu_context(smp_processor_id(), mm) == 0)
return;
On VSMP and SMTC had a function of cpu_context() for each CPU(TC).
So in case another CPU than the CPU executing local_r4k_cache_flush_page
has not accessed the mm but one of the other CPUs has there may be data
to be flushed in the cache yet local_r4k_cache_flush_page will falsely
return leaving the I-cache inconsistent for the breakpoint.
While the issue was discovered with GDB it also exists in
local_r4k_flush_cache_range() and local_r4k_flush_cache().
Fixed by introducing a new function has_valid_asid which on MT kernels
returns true if a mm is active on any processor in the system.
This is relativly expensive since for memory acccesses in that loop
cache misses have to be assumed but it seems the most viable solution
for 2.6.23 and older -stable kernels.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Enable the onboard GenBus IDE interface in the default configuration.
Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Contrary to the belief of some, the R3000 and related processors did have
caches, both a data and an instruction cache. Here is an implementation
of r3k_flush_cache_page(), which is the processor-specific back-end for
flush_cache_range(), done according to the spec in
Documentation/cachetlb.txt.
While at it, remove an unused local function: get_phys_page(), do some
trivial formatting fixes and modernise debugging facilities.
Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
