The values that these symbols define are only assigned to the per-SoC
structure where the context is clear, so there's no need for the extra
symbolic name.
Acked-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
Rename objects of type atmel_pwm_data to contain chip name instead of
version number.
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
SAM9X60's PWM controller uses 32 bits counters thus it could generate
signals with higher period and duty cycles than the old ones. Prepare
the current driver to be able to work with old controllers (that uses
16 bits counters) and with the new SAM9X60's controller, by providing
counters information based on compatible string.
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
Add struct atmel_pwm_data to embed different per controller information.
It prepares adding support for another similar controller that needs
additional information. At this stage, embed a member of type struct
atmel_pwm_registers in it.
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
sama5d2 can use the same atmel_pwm_data as sama5d3.
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Acked-by: Rob Herring <robh@kernel.org>
Reviewed-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
The currently Atmel PWM controllers supported by this driver could
change period or duty factor without channel disable, for regular
channels (sama5d3 support this by using period or duty factor update
registers, sam9rl support this by writing channel update register and
select the corresponding update: period or duty factor). The chip
doesn't support run time changings of signal polarity. To take advantage
of atomic PWM framework and let controller works without glitches, in
this patch only the duty factor could be changed without disabling PWM
channel. For period and signal polarity the atomic PWM is simulated by
disabling + enabling the right PWM channel.
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Reviewed-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
All PWM devices have been marked as "might sleep" since v4.5, there is
no longer a need to differentiate on a per-chip basis.
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
When disabling a PWM channel, the PWM clock was being stopped
immediately after writing to PWM_DIS. As a result, the disabling
of the PWM channel did not complete properly, and the PWM output
might be left at the wrong level.
Fix this by waiting for the channel to be effectively disabled
(by checking the PWM_SR register) before disabling the clock.
Signed-off-by: Guillermo Rodriguez <guille.rodriguez@gmail.com>
Acked-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
Use the pwm_get_xxx() helpers instead of directly accessing the fields
in struct pwm_device. This will allow us to smoothly move to the atomic
update approach.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
Some PWM drivers are testing the PWMF_ENABLED flag. Create a helper
function to hide the logic behind enabled test. This will allow us to
smoothly move from the current approach to an atomic PWM update
approach.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
pwm-leds calls .config() and .disable() in a row. This exhibits that it
may happen that the channel gets disabled before CDTY has been updated
with CUPD. The issue gets quite worse with long periods. So, ensure that
at least one period has past before disabling the channel by polling
ISR.
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Tested-by: Gaël PORTAY <gael.portay@gmail.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
CUPD is not flushed before enabling the channel so it will update
CDTY/CPRD just after one period. So we always set CUPD, even when the
channel is not enabled.
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
The prescale value used for calculating the period was incremented
afterwards, thus the resulting prescale value is by one too high.
This resulted in a PWM frequency only half as high as requested.
This patch moves the 64 bit division out of the prescale loop to
correct the above issue and make the calculation more efficient.
Signed-off-by: Nikolaus Voss <n.voss@weinmann-emt.de>
Tested-by: Bo Shen <voice.shen@atmel.com>
Acked-by: Bo Shen <voice.shen@atmel.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
atmel_pwm_config() calls clk_get_rate() which might sleep, so we need to
set pwm_chip can_sleep flag.
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
From the datasheet, the actual duty cycle is:
(period - (1 / clk) * CDTY) / period
This actually correct the polarity of the PWM and solves the issue that
pwm-leds exhibits: when setting a duty cycle of 0 and then disabling a
channel, the level was wrong (1 when the polarity was normal and 0 when
the polarity was inversed).
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
When atmel_pwm_config() calculates and then sets the prescaler, it is
overwriting the channel's CMR register so we are losing the CPOL
configuration.
As atmel_pwm_config() is always called before enabling a channel,
inverting the polarity doesn't work.
Fix that by reading CMR first and only overwriting the prescaler bits.
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
When the PWM controller is registered successfully, the clock can not
unprepare, so fix it.
Signed-off-by: Bo Shen <voice.shen@atmel.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
Add a PWM framework driver for the PWM controller found on Atmel SoCs.
Signed-off-by: Bo Shen <voice.shen@atmel.com>
Acked-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
[thierry.reding: coding style and other minor cleanups]
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
