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10583 Commits
| Author | SHA1 | Message | Date | |
|---|---|---|---|---|
Satya Priya Kakitapalli
|
a4d89b11ac |
clk: qcom: clk-alpha-pll: Simplify the zonda_pll_adjust_l_val()
In zonda_pll_adjust_l_val() replace the divide operator with comparison
operator to fix below build error and smatch warning.
drivers/clk/qcom/clk-alpha-pll.o: In function `clk_zonda_pll_set_rate':
clk-alpha-pll.c:(.text+0x45dc): undefined reference to `__aeabi_uldivmod'
smatch warnings:
drivers/clk/qcom/clk-alpha-pll.c:2129 zonda_pll_adjust_l_val() warn: replace
divide condition '(remainder * 2) / prate' with '(remainder * 2) >= prate'
Fixes:
|
||
Johan Hovold
|
71c03a8cb2 |
clk: qcom: gcc-sc8280xp: don't use parking clk_ops for QUPs
A recent change started parking the RCG at an always on parent during registration, something which specifically breaks handover from an early serial console. Quoting Stephen Boyd who fixed this issue for SM8550 [1]: The QUPs aren't shared in a way that requires parking the RCG at an always on parent in case some other entity turns on the clk. The hardware is capable of setting a new frequency itself with the DFS mode, so parking is unnecessary. Furthermore, there aren't any GDSCs for these devices, so there isn't a possibility of the GDSC turning on the clks for housekeeping purposes. This wasn't a problem to mark these clks shared until we started parking shared RCGs at clk registration time in commit |
||
Xingyu Wu
|
538d5477b2 |
clk: starfive: jh7110-sys: Add notifier for PLL0 clock
Add notifier function for PLL0 clock. In the function, the cpu_root clock
should be operated by saving its current parent and setting a new safe
parent (osc clock) before setting the PLL0 clock rate. After setting PLL0
rate, it should be switched back to the original parent clock.
Fixes:
|
||
Neil Armstrong
|
aa2eb2c435 |
clk: qcom: gcc-sm8650: Don't use shared clk_ops for QUPs
The QUPs aren't shared in a way that requires parking the RCG at an always on parent in case some other entity turns on the clk. The hardware is capable of setting a new frequency itself with the DFS mode, so parking is unnecessary. Furthermore, there aren't any GDSCs for these devices, so there isn't a possibility of the GDSC turning on the clks for housekeeping purposes. Like for the SM8550 GCC QUP clocks at [1], do not use shared clk_ops for QUPs. [1] https://lore.kernel.org/all/20240827231237.1014813-3-swboyd@chromium.org/ Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20240829-topic-sm8650-upstream-fix-qup-clk-rcg-shared-v1-1-7ecdbc672187@linaro.org Signed-off-by: Stephen Boyd <sboyd@kernel.org> |
||
Stephen Boyd
|
7b6dfa1bbe |
clk: qcom: gcc-sm8550: Don't park the USB RCG at registration time
Amit Pundir reports that audio and USB-C host mode stops working if the gcc_usb30_prim_master_clk_src clk is registered and clk_rcg2_shared_init() parks it on XO. Skip parking this clk at registration time to fix those issues. Partially revert commit |
||
|
Stephen Boyd
|
d10eeb7516 |
clk: qcom: gcc-sm8550: Don't use parking clk_ops for QUPs
The QUPs aren't shared in a way that requires parking the RCG at an always on parent in case some other entity turns on the clk. The hardware is capable of setting a new frequency itself with the DFS mode, so parking is unnecessary. Furthermore, there aren't any GDSCs for these devices, so there isn't a possibility of the GDSC turning on the clks for housekeeping purposes. This wasn't a problem to mark these clks shared until we started parking shared RCGs at clk registration time in commit |
||
Bryan O'Donoghue
|
ca082333b4 |
clk: qcom: gcc-x1e80100: Don't use parking clk_ops for QUPs
Per Stephen Boyd's explanation in the link below, QUP RCG clocks do not need to be parked when switching frequency. A side-effect in parking to a lower frequency can be a momentary invalid clock driven on an in-use serial peripheral. This can cause "junk" to spewed out of a UART as a low-impact example. On the x1e80100-crd this serial port junk can be observed on linux-next. Apply a similar fix to the x1e80100 Global Clock controller to remediate. Link: https://lore.kernel.org/all/20240819233628.2074654-3-swboyd@chromium.org/ Fixes: |
||
Stephen Boyd
|
0f6eaf125e |
Qualcomm clock fixes for v6.11
This corrects several issues with the Alpha PLL clock driver. It updates IPQ9574 GCC driver to correctly use the EVO PLL registers for GPLL clocks. X1E USB GDSC flags are corrected to leave these in retention as the controllers are suspended. -----BEGIN PGP SIGNATURE----- iQJJBAABCAAzFiEEBd4DzF816k8JZtUlCx85Pw2ZrcUFAmbMmk8VHGFuZGVyc3Nv bkBrZXJuZWwub3JnAAoJEAsfOT8Nma3FOnsP/jQzNV2WnmVhZcaVEMCodelYVDVq A3IDvVXzmDtcnGMxyZ92By5wO+/ZvqmyhlokYWSNbOs1LIRzCjjHUAIIqsJjXeTK yG8FbIPPnN9KyQw/pOR92UbQHRnZdmyKG8kfs1WM4DVWbWUlRPoLD4sqYhkXTF1I 0d0zpNfM9bmAw5DM1RGAZMbL2z982+7QfKt6vqTfW+kc2Emk71mjB/HqNIGyta+U ty3FYj9RNBSlCVedcrSrqgpNz71vv4cKrBN25pQOGihTW7Ad46WeMbEQAqQbyARg bddMA73ZRKqxqZUsGbyjYeb5f8rXQpW8TNkZIVki+Wsp1qqAXMWrQ4jy/kpxd9oC /Wgnsilxeu+U+GUSRq/hdvHi+K2JPijT9+6tnOEhzAPDk19RGwkispZQJ+YsZrGm TRwuIubd+QwEhs7/B3pEGtXCmdLDvoNt+MQC1336Iz5Za9AglEv1bNvaabMr6vhr Infb9gItsPflQwyJD9DXIxD1j0jG8hh5efACLOuNUT9YBiSWg34HSRLWhKT5s3wR I40WrRP/UxziZOmOa5KTOUf+n0rLBMB4YRCoQ1hczuSbOEodgUeb5Ux9++SQ/VkA XDYKLx1mPMXHPlGzZ48B/knltqzwPmcOI41EbDC9uiG6qAaJGZbBIKH/WEBb5Fof YB//eGUSmcCpSFR0 =B0FJ -----END PGP SIGNATURE----- Merge tag 'qcom-clk-fixes-for-6.11' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into clk-fixes Pull Qualcomm clk driver fixes from Bjorn Andersson: This corrects several issues with the Alpha PLL clock driver. It updates IPQ9574 GCC driver to correctly use the EVO PLL registers for GPLL clocks. X1E USB GDSC flags are corrected to leave these in retention as the controllers are suspended. * tag 'qcom-clk-fixes-for-6.11' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: clk: qcom: ipq9574: Update the alpha PLL type for GPLLs clk: qcom: gcc-x1e80100: Fix USB 0 and 1 PHY GDSC pwrsts flags clk: qcom: clk-alpha-pll: Update set_rate for Zonda PLL clk: qcom: clk-alpha-pll: Fix zonda set_rate failure when PLL is disabled clk: qcom: clk-alpha-pll: Fix the trion pll postdiv set rate API clk: qcom: clk-alpha-pll: Fix the pll post div mask |
||
devi priya
|
6357efe3ab |
clk: qcom: ipq9574: Update the alpha PLL type for GPLLs
Update PLL offsets to DEFAULT_EVO to configure MDIO to 800MHz.
The incorrect clock frequency leads to an incorrect MDIO clock. This,
in turn, affects the MDIO hardware configurations as the divider is
calculated from the MDIO clock frequency. If the clock frequency is
not as expected, the MDIO register fails due to the generation of an
incorrect MDIO frequency.
This issue is critical as it results in incorrect MDIO configurations
and ultimately leads to the MDIO function not working. This results in
a complete feature failure affecting all Ethernet PHYs. Specifically,
Ethernet will not work on IPQ9574 due to this issue.
Currently, the clock frequency is set to CLK_ALPHA_PLL_TYPE_DEFAULT.
However, this setting does not yield the expected clock frequency.
To rectify this, we need to change this to CLK_ALPHA_PLL_TYPE_DEFAULT_EVO.
This modification ensures that the clock frequency aligns with our
expectations, thereby resolving the MDIO register failure and ensuring
the proper functioning of the Ethernet on IPQ9574.
Fixes:
|
||
Abel Vesa
|
f4c16a7cdb |
clk: qcom: gcc-x1e80100: Fix USB 0 and 1 PHY GDSC pwrsts flags
Allowing these GDSCs to collapse makes the QMP combo PHYs lose their
configuration on machine suspend. Currently, the QMP combo PHY driver
doesn't reinitialise the HW on resume. Under such conditions, the USB
SuperSpeed support is broken. To avoid this, mark the pwrsts flags with
RET_ON. This is in line with USB 2 PHY GDSC config.
Fixes:
|
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|
Satya Priya Kakitapalli
|
f4973130d2 |
clk: qcom: clk-alpha-pll: Update set_rate for Zonda PLL
The Zonda PLL has a 16 bit signed alpha and in the cases where the alpha
value is greater than 0.5, the L value needs to be adjusted accordingly.
Thus update the logic to handle the signed alpha val.
Fixes:
|
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|
Satya Priya Kakitapalli
|
85e8ee59df |
clk: qcom: clk-alpha-pll: Fix zonda set_rate failure when PLL is disabled
Currently, clk_zonda_pll_set_rate polls for the PLL to lock even if the
PLL is disabled. However, if the PLL is disabled then LOCK_DET will
never assert and we'll return an error. There is no reason to poll
LOCK_DET if the PLL is already disabled, so skip polling in this case.
Fixes:
|
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|
Satya Priya Kakitapalli
|
4ad1ed6ef2 |
clk: qcom: clk-alpha-pll: Fix the trion pll postdiv set rate API
Correct the pll postdiv shift used in clk_trion_pll_postdiv_set_rate
API. The shift value is not same for different types of plls and
should be taken from the pll's .post_div_shift member.
Fixes:
|
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|
Satya Priya Kakitapalli
|
2c4553e6c4 |
clk: qcom: clk-alpha-pll: Fix the pll post div mask
The PLL_POST_DIV_MASK should be 0 to (width - 1) bits. Fix it.
Fixes:
|
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Drew Fustini
|
39a3396558 |
clk: thead: fix dependency on clk_ignore_unused
Add the CLK_IGNORE_UNUSED flag to the vp-axi clock (CLK_VP_AXI) to avoid
depending on clk_ignore_unused in the cmdline. Without this fix, the
emmc-sdio clock (CLK_EMMC_SDIO) fails to work after vp-axi is disabled.
Signed-off-by: Drew Fustini <drew@pdp7.com>
Link: https://lore.kernel.org/r/20240731061439.3807172-1-drew@pdp7.com
Fixes:
|
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Linus Torvalds
|
bf80f1391a |
Devicetree fixes for 6.11, part 1
- Treewide conversion of of_property_for_each_u32() to drop internal
arguments making struct property opaque
- Add binding for Amlogic A4 SoC watchdog
- Fix constraints for AD7192 'single-channel' property
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Merge tag 'devicetree-fixes-for-6.11-1' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux
Pull more devicetree updates from Rob Herring:
"Most of this is a treewide change to of_property_for_each_u32() which
was small enough to do in one go before rc1 and avoids the need to
create of_property_for_each_u32_some_new_name().
- Treewide conversion of of_property_for_each_u32() to drop internal
arguments making struct property opaque
- Add binding for Amlogic A4 SoC watchdog
- Fix constraints for AD7192 'single-channel' property"
* tag 'devicetree-fixes-for-6.11-1' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux:
dt-bindings: iio: adc: ad7192: Fix 'single-channel' constraints
of: remove internal arguments from of_property_for_each_u32()
dt-bindings: watchdog: add support for Amlogic A4 SoCs
|
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|
Linus Torvalds
|
de5f4fbe7b |
A few clk driver fixes for the merge window to fix the build and boot on
some SoCs.
- Initialize struct clk_init_data in the TI da8xx-cfgchip driver so
that stack contents aren't used for things like clk flags leading to
unexpected behavior
- Don't leak stack contents in a debug print in the new Sophgo clk
driver
- Disable the new T-Head clk driver on 32-bit targets to fix the build
due to a division
- Fix Samsung Exynos4 fin_pll wreckage from the clkdev rework done last
cycle by using a struct clk_hw directly instead of a struct clk
consumer
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Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull clk fixes from Stephen Boyd:
"A few clk driver fixes for the merge window to fix the build and boot
on some SoCs.
- Initialize struct clk_init_data in the TI da8xx-cfgchip driver so
that stack contents aren't used for things like clk flags leading
to unexpected behavior
- Don't leak stack contents in a debug print in the new Sophgo clk
driver
- Disable the new T-Head clk driver on 32-bit targets to fix the
build due to a division
- Fix Samsung Exynos4 fin_pll wreckage from the clkdev rework done
last cycle by using a struct clk_hw directly instead of a struct
clk consumer"
* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux:
clk: samsung: fix getting Exynos4 fin_pll rate from external clocks
clk: T-Head: Disable on 32-bit Targets
clk: sophgo: clk-sg2042-pll: Fix uninitialized variable in debug output
clk: davinci: da8xx-cfgchip: Initialize clk_init_data before use
|
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Luca Ceresoli
|
9722c3b66e |
of: remove internal arguments from of_property_for_each_u32()
The of_property_for_each_u32() macro needs five parameters, two of which
are primarily meant as internal variables for the macro itself (in the
for() clause). Yet these two parameters are used by a few drivers, and this
can be considered misuse or at least bad practice.
Now that the kernel uses C11 to build, these two parameters can be avoided
by declaring them internally, thus changing this pattern:
struct property *prop;
const __be32 *p;
u32 val;
of_property_for_each_u32(np, "xyz", prop, p, val) { ... }
to this:
u32 val;
of_property_for_each_u32(np, "xyz", val) { ... }
However two variables cannot be declared in the for clause even with C11,
so declare one struct that contain the two variables we actually need. As
the variables inside this struct are not meant to be used by users of this
macro, give the struct instance the noticeable name "_it" so it is visible
during code reviews, helping to avoid new code to use it directly.
Most usages are trivially converted as they do not use those two
parameters, as expected. The non-trivial cases are:
- drivers/clk/clk.c, of_clk_get_parent_name(): easily doable anyway
- drivers/clk/clk-si5351.c, si5351_dt_parse(): this is more complex as the
checks had to be replicated in a different way, making code more verbose
and somewhat uglier, but I refrained from a full rework to keep as much
of the original code untouched having no hardware to test my changes
All the changes have been build tested. The few for which I have the
hardware have been runtime-tested too.
Reviewed-by: Andre Przywara <andre.przywara@arm.com> # drivers/clk/sunxi/clk-simple-gates.c, drivers/clk/sunxi/clk-sun8i-bus-gates.c
Acked-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> # drivers/gpio/gpio-brcmstb.c
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com> # drivers/irqchip/irq-atmel-aic-common.c
Acked-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> # drivers/iio/adc/ti_am335x_adc.c
Acked-by: Uwe Kleine-König <u.kleine-koenig@baylibre.com> # drivers/pwm/pwm-samsung.c
Acked-by: Richard Leitner <richard.leitner@linux.dev> # drivers/usb/misc/usb251xb.c
Acked-by: Mark Brown <broonie@kernel.org> # sound/soc/codecs/arizona.c
Reviewed-by: Richard Fitzgerald <rf@opensource.cirrus.com> # sound/soc/codecs/arizona.c
Acked-by: Michael Ellerman <mpe@ellerman.id.au> # arch/powerpc/sysdev/xive/spapr.c
Acked-by: Stephen Boyd <sboyd@kernel.org> # clk
Signed-off-by: Luca Ceresoli <luca.ceresoli@bootlin.com>
Acked-by: Lee Jones <lee@kernel.org>
Link: https://lore.kernel.org/r/20240724-of_property_for_each_u32-v3-1-bea82ce429e2@bootlin.com
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
|
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Krzysztof Kozlowski
|
f99b3feb3b |
clk: samsung: fix getting Exynos4 fin_pll rate from external clocks
Commit |
||
Palmer Dabbelt
|
0e91ac701c |
clk: T-Head: Disable on 32-bit Targets
This fails to build on 32-bit targets because of a missing __udivdi3. IIRC the right way to fix that is to avoid the division, but I just want a tree that builds and the only real T-Head platforms are 64-bit right now. Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com> Link: https://lore.kernel.org/r/20240719151027.16152-1-palmer@rivosinc.com Acked-by: Drew Fustini <drew@pdp7.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org> |
||
|
Linus Torvalds
|
a4f9285520 |
This a large collection of clk driver updates and a handful of new SoC
clk driver support. We have the usual Qualcomm clk drivers, along with
clk drivers for the Sophgo and T-Head vendors, all to support some new
SoCs.
Nothing in particular stands out to me in the updates. There's the
interconnect clk driver which exposes clks as interconnects, crossing
subsystems. There's a bunch of janitorial things that are improving
drivers in general like kmemdup_array() or fixing error paths. But
overall the updates look normal to fix the description data which is
usually the stuff that's wrong and/or untested.
I really wanted to land a bunch of KUnit clk code that I've been working
on whenever I get some free time but it turned into a pumpkin at the
last minute so I dropped those patches. I'll let it soak in linux-next
after the merge window closes. I have a suspicion that we're going to
need to totally rework the clk framework to fix structural issues like
locking, clk rate setting, and runtime PM usage. Having a bunch of unit
tests for that will help make sure that all keeps working.
Core:
- Skip gate basic type KUnit tests on s390 due to lack of MMIO emulation
New Drivers:
- AP sub-system clock controller in the T-Head TH1520
- Sophgo Sophon sg2042 clk driver
- Qualcomm SM7150 camera, display and video clk drivers
- Qualcomm QCM2290 GPU clk driver
- Qualcomm QCS8386/QCS8084 NSS clk driver
- Qualcomm SM8650 camera and video drivers
Updates:
- Add reset support to Airoha EN7581 clk driver
- Add MODULE_DESCRIPTIONs to various clk drivers
- Introduce helper logic to expose clock controllers as simple
interconnect providers
- Use the interconnect helper above on Qualcomm ipq9574
- Add CLK_SET_RATE_PARENT to the remaining USB pipe clocks on Qualcomm
X1Elite
- Improve error handling in Qualcomm kpss-xcc driver
- Mark Qualcomm SC8280XP LPASS clock controller regmap_config const
- Export more clocks for Rockchip rk3128 peripherals
- Convert Rockchip clk drivers to use kmemdup_array()
- Drop CLK_NR_CLKS from Rockchip rk3128 and rk3188 binding headers
- Make qcom_cc_really_probe() take a struct device to allow reuse in
non-platform-drivers
- Introduce prepare-only branch clock ops in the qcom clk driver to
support clocks on buses that take locks
- Describe parent/child relationship for Qualcomm SC7280 camera GDSCs
- Support Qualcomm Huayra 2290 alpha PLL
- Adjust the highest SDCC clock frequency on Qualcomm IPQ6018 to match
HS200 support
- Add missing PCIe PIPE clocks on Qualcomm IPQ9574
- Fix various configurations and properties in the Qualcomm SA8775P,
X1E80100 and SM7280 drivers
- Park Qualcomm SM8350 GPU RCGs on XO while disabled
- Remove unused CONFIG_QCOM_RPMCC Kconfig symbol
- exynos-clkout: Remove usage of of_device_id table as .of_match_table,
because the driver is instantiated as MFD cell, not as standalone platform
driver. Populated .of_match_table confused people few times to convert the
code to device_get_match_data(), which broke the driver
- Mark one Samsung UFS clock as critical, because having it off stops the
system from shutdown
- Use kmemdup_array() when applicable
- Remove unused 'struct gates_data' from old sunxi driver library
- Add GPADC clock and reset for Allwinner H616
- Minor Amlogic S4 clock fixes
- DT bindings Yaml conversion of the Amlogic AXG audio controller
- Amlogic C3 clock controllers support
- Amlogic clk flag added to skip init of already enabled PLLs and avoid relocking
- Amlogic A1 DT bindings updates for system pll support
- Add missing MODULE_DESCRIPTION where necessary
- Remove obsolete clock DT binding header files
- Add Battery Backup (VBATTB) and I2C clocks, resets, and power
domains on Renesas RZ/G3S
- Add audio clocks on Renesas R-Car V4M
- Add video capture (ISPCS, CSI-2, VIN) clocks on Renesas R-Car V4M
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Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull clk updates from Stephen Boyd:
"This a large collection of clk driver updates and a handful of new SoC
clk driver support.
We have the usual Qualcomm clk drivers, along with clk drivers for the
Sophgo and T-Head vendors, all to support some new SoCs.
Nothing in particular stands out to me in the updates. There's the
interconnect clk driver which exposes clks as interconnects, crossing
subsystems. There's a bunch of janitorial things that are improving
drivers in general like kmemdup_array() or fixing error paths. But
overall the updates look normal to fix the description data which is
usually the stuff that's wrong and/or untested.
Core:
- Skip gate basic type KUnit tests on s390 due to lack of MMIO
emulation
New Drivers:
- AP sub-system clock controller in the T-Head TH1520
- Sophgo Sophon sg2042 clk driver
- Qualcomm SM7150 camera, display and video clk drivers
- Qualcomm QCM2290 GPU clk driver
- Qualcomm QCS8386/QCS8084 NSS clk driver
- Qualcomm SM8650 camera and video drivers
Updates:
- Add reset support to Airoha EN7581 clk driver
- Add MODULE_DESCRIPTIONs to various clk drivers
- Introduce helper logic to expose clock controllers as simple
interconnect providers
- Use the interconnect helper above on Qualcomm ipq9574
- Add CLK_SET_RATE_PARENT to the remaining USB pipe clocks on
Qualcomm X1Elite
- Improve error handling in Qualcomm kpss-xcc driver
- Mark Qualcomm SC8280XP LPASS clock controller regmap_config const
- Export more clocks for Rockchip rk3128 peripherals
- Convert Rockchip clk drivers to use kmemdup_array()
- Drop CLK_NR_CLKS from Rockchip rk3128 and rk3188 binding headers
- Make qcom_cc_really_probe() take a struct device to allow reuse in
non-platform-drivers
- Introduce prepare-only branch clock ops in the qcom clk driver to
support clocks on buses that take locks
- Describe parent/child relationship for Qualcomm SC7280 camera GDSCs
- Support Qualcomm Huayra 2290 alpha PLL
- Adjust the highest SDCC clock frequency on Qualcomm IPQ6018 to
match HS200 support
- Add missing PCIe PIPE clocks on Qualcomm IPQ9574
- Fix various configurations and properties in the Qualcomm SA8775P,
X1E80100 and SM7280 drivers
- Park Qualcomm SM8350 GPU RCGs on XO while disabled
- Remove unused CONFIG_QCOM_RPMCC Kconfig symbol
- exynos-clkout: Remove usage of of_device_id table as
.of_match_table, because the driver is instantiated as MFD cell,
not as standalone platform driver. Populated .of_match_table
confused people few times to convert the code to
device_get_match_data(), which broke the driver
- Mark one Samsung UFS clock as critical, because having it off stops
the system from shutdown
- Use kmemdup_array() when applicable
- Remove unused 'struct gates_data' from old sunxi driver library
- Add GPADC clock and reset for Allwinner H616
- Minor Amlogic S4 clock fixes
- DT bindings Yaml conversion of the Amlogic AXG audio controller
- Amlogic C3 clock controllers support
- Amlogic clk flag added to skip init of already enabled PLLs and
avoid relocking
- Amlogic A1 DT bindings updates for system pll support
- Add missing MODULE_DESCRIPTION where necessary
- Remove obsolete clock DT binding header files
- Add Battery Backup (VBATTB) and I2C clocks, resets, and power
domains on Renesas RZ/G3S
- Add audio clocks on Renesas R-Car V4M
- Add video capture (ISPCS, CSI-2, VIN) clocks on Renesas R-Car V4M"
* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (135 commits)
clk: thead: Add support for T-Head TH1520 AP_SUBSYS clocks
dt-bindings: clock: Document T-Head TH1520 AP_SUBSYS controller
clk: sophgo: Avoid -Wsometimes-uninitialized in sg2042_clk_pll_set_rate()
clk/sophgo: Using BUG() instead of unreachable() in mmux_get_parent_id()
clk: mxs: Use clamp() in clk_ref_round_rate() and clk_ref_set_rate()
clk: sunxi-ng r40: Constify struct regmap_config
clk: en7523: fix rate divider for slic and spi clocks
clk: lpc32xx: Constify struct regmap_config
clk: xilinx: Constify struct regmap_config
clk: en7523: Remove PCIe reset open drain configuration for EN7581
clk: en7523: Remove pcie prepare/unpreare callbacks for EN7581 SoC
clk: en7523: Add reset-controller support for EN7581 SoC
dt-bindings: clock: airoha: Add reset support to EN7581 clock binding
dt-bindings: clock: mediatek: Document reset cells for MT8188 sys
clk: mediatek: mt8173-infracfg: Handle unallocated infracfg when module
dt-bindings: clock: mediatek: add syscon compatible for mt7622 pciesys
dt-bindings: clock: sprd,sc9860-clk: convert to YAML
dt-bindings: clock: qoriq-clock: convert to yaml format
clk: qcom: Park shared RCGs upon registration
clk: qcom: ipq9574: Use icc-clk for enabling NoC related clocks
...
|
||
Dan Carpenter
|
5a6a25ea5b |
clk: sophgo: clk-sg2042-pll: Fix uninitialized variable in debug output
If sg2042_get_pll_ctl_setting() fails then "value" isn't initialized and
it is printed in the debug output. Initialize it to zero.
Fixes:
|
||
Bastien Curutchet
|
a83b22754e |
clk: davinci: da8xx-cfgchip: Initialize clk_init_data before use
The flag attribute of the struct clk_init_data isn't initialized before
the devm_clk_hw_register() call. This can lead to unexpected behavior
during registration.
Initialize the entire clk_init_data to zero at declaration.
Cc: stable@vger.kernel.org
Fixes:
|
||
|
Linus Torvalds
|
e3950967f6 |
soc: dt updates for 6.11
The devicetree updates are fairly well spread out across platforms,
with Qualcomm making up about a third of the total.
There are three new SoCs in existing product families this:
- NXP i.MX95 is a variant of i.MX93, now with six Cortex-A55 cores
instead of just two as well as a GPU and more high-speed I/O
devices.
- Qualcomm QCS8550 is a variant of SM8550 for IOT devices
- Airoha EN7581 is a 10G-PON network chip and related to
the MT7981 Wireless router chip from its parent Mediatek.
In total there are 58 new machines, including four riscv
boards and eight for 32-bit arm.
The most exciting new addition is probably a pair of laptops
based on the Qualcomm x1e80100 (Snapdragon X1 Elite) chip,
the Asus Vivobook S15 and the Lenovo Yoga Slim7x.
Other noteworthy new additions are:
- A total of 20 Qualcomm based machines, mostly Android devices
from Samsung, Motorola and LG, as well as a wireless router
and some reference designs
- Six NXP i.MX based machines, mostly industrial boards along
with some reference designs
- Mediatek sees some interesting Filogic based routers
including the "OpenWRT One", a few new Chromebooks as
well as single-board computers.
- Four machines from Solidrun based on Marvell cn913x,
replacing the older Armada 8000 based counterparts
- The four Amlogic machines are all set top boxes or reference
designs for them
- The nine new Rockchips machines are mostly single-board
computers including some interesting ones based on the
rk3588 chip like the ROCK 5 ITX board and the CM3588
with its four NVMe slots
- The RISC-V boards are all single-board computers based on
Starfive JH7110, Microchip MPFS and Allwinner D1, which all
had similar boards already
There are also a lot of updates to already supported machines,
notably for the TI K3, Rockchips, Freescale and of course
Qualcomm platforms.
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Merge tag 'soc-dt-6.11' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull SoC dt updates from Arnd Bergmann:
"The devicetree updates are fairly well spread out across platforms,
with Qualcomm making up about a third of the total.
There are three new SoCs in existing product families this:
- NXP i.MX95 is a variant of i.MX93, now with six Cortex-A55 cores
instead of just two as well as a GPU and more high-speed I/O
devices.
- Qualcomm QCS8550 is a variant of SM8550 for IOT devices
- Airoha EN7581 is a 10G-PON network chip and related to the MT7981
Wireless router chip from its parent Mediatek.
In total there are 58 new machines, including four riscv boards and
eight for 32-bit arm.
The most exciting new addition is probably a pair of laptops based on
the Qualcomm x1e80100 (Snapdragon X1 Elite) chip, the Asus Vivobook
S15 and the Lenovo Yoga Slim7x.
Other noteworthy new additions are:
- A total of 20 Qualcomm based machines, mostly Android devices from
Samsung, Motorola and LG, as well as a wireless router and some
reference designs
- Six NXP i.MX based machines, mostly industrial boards along with
some reference designs
- Mediatek sees some interesting Filogic based routers including the
"OpenWRT One", a few new Chromebooks as well as single-board
computers.
- Four machines from Solidrun based on Marvell cn913x, replacing the
older Armada 8000 based counterparts
- The four Amlogic machines are all set top boxes or reference
designs for them
- The nine new Rockchips machines are mostly single-board computers
including some interesting ones based on the rk3588 chip like the
ROCK 5 ITX board and the CM3588 with its four NVMe slots
- The RISC-V boards are all single-board computers based on Starfive
JH7110, Microchip MPFS and Allwinner D1, which all had similar
boards already
There are also a lot of updates to already supported machines, notably
for the TI K3, Rockchips, Freescale and of course Qualcomm platforms"
* tag 'soc-dt-6.11' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (846 commits)
arm64: dts: allwinner: h616: add crypto engine node
riscv: dts: add clock generator for Sophgo SG2042 SoC
arm64: dts: rockchip: Add Xunlong Orange Pi 3B
dt-bindings: arm: rockchip: Add Xunlong Orange Pi 3B
arm64: dts: rockchip: Add Radxa ROCK 3B
dt-bindings: arm: rockchip: Add Radxa ROCK 3B
mailmap: Update Luca Weiss's email address
ARM: dts: ixp4xx: nslu2: beeper uses PWM
arm64: dts: rockchip: add ROCK 5 ITX board
dt-bindings: arm: rockchip: Add ROCK 5 ITX board
arm64: dts: rockchip: Add dma-names to uart1 on Pine64 rk3566 devices
arm64: dts: rockchip: Add avdd supplies to hdmi on rock64
arm64: dts: qcom: msm8916-lg-c50: add initial dts for LG Leon LTE
arm64: dts: qcom: msm8916-lg-m216: Add initial device tree
dt-bindings: arm: qcom: Add msm8916 based LG devices
ARM: dts: qcom: msm8960: correct memory base
arm64: dts: qcom: ipq9574: Add icc provider ability to gcc
dt-bindings: interconnect: Add Qualcomm IPQ9574 support
arm64: dts: qcom: sm8150: Add video clock controller node
arm64: dts: qcom: pm6150: Add vibrator
...
|
||
|
Stephen Boyd
|
589eb11498 |
Merge branches 'clk-qcom', 'clk-rockchip', 'clk-sophgo' and 'clk-thead' into clk-next
- Add support for the AP sub-system clock controller in the T-Head TH1520 * clk-qcom: (71 commits) clk: qcom: Park shared RCGs upon registration clk: qcom: ipq9574: Use icc-clk for enabling NoC related clocks clk: qcom: common: Add interconnect clocks support interconnect: icc-clk: Add devm_icc_clk_register interconnect: icc-clk: Specify master/slave ids dt-bindings: clock: qcom: Add AHB clock for SM8150 clk: qcom: gcc-x1e80100: Set parent rate for USB3 sec and tert PHY pipe clks dt-bindings: interconnect: Add Qualcomm IPQ9574 support clk: qcom: kpss-xcc: Return of_clk_add_hw_provider to transfer the error clk: qcom: lpasscc-sc8280xp: Constify struct regmap_config clk: qcom: gcc-x1e80100: Fix halt_check for all pipe clocks clk: qcom: gcc-ipq6018: update sdcc max clock frequency clk: qcom: camcc-sm8650: Add SM8650 camera clock controller driver dt-bindings: clock: qcom: Add SM8650 camera clock controller dt-bindings: clock: qcom: Update the order of SC8280XP camcc header clk: qcom: videocc-sm8550: Add SM8650 video clock controller clk: qcom: videocc-sm8550: Add support for videocc XO clk ares dt-bindings: clock: qcom: Add SM8650 video clock controller dt-bindings: clock: qcom: Update SM8450 videocc header file name clk: qcom: gpucc-sa8775p: Update wait_val fields for GPU GDSC's ... * clk-rockchip: dt-bindings: clock: rk3188-cru-common: remove CLK_NR_CLKS clk: rockchip: rk3188: Drop CLK_NR_CLKS usage clk: rockchip: Switch to use kmemdup_array() clk: rockchip: rk3128: Add HCLK_SFC dt-bindings: clock: rk3128: Add HCLK_SFC dt-bindings: clock: rk3128: Drop CLK_NR_CLKS clk: rockchip: rk3128: Drop CLK_NR_CLKS usage clk: rockchip: rk3128: Add hclk_vio_h2p to critical clocks clk: rockchip: rk3128: Export PCLK_MIPIPHY dt-bindings: clock: rk3128: Add PCLK_MIPIPHY * clk-sophgo: clk: sophgo: Avoid -Wsometimes-uninitialized in sg2042_clk_pll_set_rate() clk/sophgo: Using BUG() instead of unreachable() in mmux_get_parent_id() clk: sophgo: Add SG2042 clock driver dt-bindings: clock: sophgo: add clkgen for SG2042 dt-bindings: clock: sophgo: add RP gate clocks for SG2042 dt-bindings: clock: sophgo: add pll clocks for SG2042 * clk-thead: clk: thead: Add support for T-Head TH1520 AP_SUBSYS clocks dt-bindings: clock: Document T-Head TH1520 AP_SUBSYS controller |
||
|
Stephen Boyd
|
bc060e6bb7 |
Merge branches 'clk-renesas', 'clk-amlogic', 'clk-allwinner' and 'clk-samsung' into clk-next
* clk-renesas: clk: renesas: r9a08g045: Add clock, reset and power domain support for I2C clk: renesas: r8a779h0: Add Audio clocks clk: renesas: r9a08g045: Add clock, reset and power domain support for the VBATTB IP dt-bindings: clock: rcar-gen2: Remove obsolete header files dt-bindings: clock: r8a7779: Remove duplicate newline clk: renesas: Drop "Renesas" from individual driver descriptions clk: renesas: r8a779h0: Fix PLL2/PLL4 multipliers in comments clk: renesas: r8a779h0: Add VIN clocks dt-bindings: clock: renesas,rzg2l-cpg: Update description for #reset-cells clk: renesas: rcar-gen2: Use DEFINE_SPINLOCK() for static spinlock clk: renesas: cpg-lib: Use DEFINE_SPINLOCK() for global spinlock clk: renesas: r8a77970: Use common cpg_lock clk: renesas: r8a779h0: Add CSI-2 clocks clk: renesas: r8a779h0: Add ISPCS clocks * clk-amlogic: clk: meson: add missing MODULE_DESCRIPTION() macros dt-bindings: clock: meson: a1: peripherals: support sys_pll input dt-bindings: clock: meson: a1: pll: introduce new syspll bindings clk: meson: add 'NOINIT_ENABLED' flag to eliminate init for enabled PLL clk: meson: c3: add c3 clock peripherals controller driver clk: meson: c3: add support for the C3 SoC PLL clock dt-bindings: clock: add Amlogic C3 peripherals clock controller dt-bindings: clock: add Amlogic C3 SCMI clock controller support dt-bindings: clock: add Amlogic C3 PLL clock controller dt-bindings: clock: meson: Convert axg-audio-clkc to YAML format clk: meson: s4: fix pwm_j_div parent clock clk: meson: s4: fix fixed_pll_dco clock * clk-allwinner: clk: sunxi-ng r40: Constify struct regmap_config clk: sunxi-ng: h616: Add clock/reset for GPADC dt-bindings: clock: sun50i-h616-ccu: Add GPADC clocks clk: sunxi: Remove unused struct 'gates_data' clk: sunxi-ng: add missing MODULE_DESCRIPTION() macros * clk-samsung: clk: samsung: gs101: mark gout_hsi2_ufs_embd_i_clk_unipro as critical clk: samsung: Switch to use kmemdup_array() clk: samsung: exynos-clkout: Remove misleading of_match_table/MODULE_DEVICE_TABLE |
||
|
Stephen Boyd
|
160d7b9fb9 |
Merge branches 'clk-stm', 'clk-cleanup', 'clk-kunit' and 'clk-mediatek' into clk-next
- Add reset support to Airoha EN7581 clk driver - Add module description to mediatek clk drivers * clk-stm: clk: stm32mp25: add security clocks clk: stm32mp2: use of STM32 access controller * clk-cleanup: clk: mxs: Use clamp() in clk_ref_round_rate() and clk_ref_set_rate() clk: lpc32xx: Constify struct regmap_config clk: xilinx: Constify struct regmap_config dt-bindings: clock: sprd,sc9860-clk: convert to YAML dt-bindings: clock: qoriq-clock: convert to yaml format clk: vexpress-osc: add missing MODULE_DESCRIPTION() macro clk: sifive: prci: fix module autoloading dt-bindings: clock: milbeaut: Drop providers and consumers from example clk: sprd: add missing MODULE_DESCRIPTION() macro clk: sophgo: add missing MODULE_DESCRIPTION() macro * clk-kunit: clk: disable clk gate tests for s390 clk: test: add missing MODULE_DESCRIPTION() macros * clk-mediatek: clk: en7523: fix rate divider for slic and spi clocks clk: en7523: Remove PCIe reset open drain configuration for EN7581 clk: en7523: Remove pcie prepare/unpreare callbacks for EN7581 SoC clk: en7523: Add reset-controller support for EN7581 SoC dt-bindings: clock: airoha: Add reset support to EN7581 clock binding dt-bindings: clock: mediatek: Document reset cells for MT8188 sys clk: mediatek: mt8173-infracfg: Handle unallocated infracfg when module dt-bindings: clock: mediatek: add syscon compatible for mt7622 pciesys clk: mediatek: Add a module description where missing |
||
|
Linus Torvalds
|
d46ede3188 |
pmdomain core:
- Add support for HW-managed devices pmdomain providers: - amlogic: Add support for the A5 and the A4 power domains - arm: Enable system wakeups for the SCMI PM domain - qcom/clk: Add HW-mode callbacks to allow switching of GDSC mode pmdomain consumers: - qcom/media/venus: Enable support for switching GDSC HW-mode on V6 -----BEGIN PGP SIGNATURE----- iQJLBAABCgA1FiEEugLDXPmKSktSkQsV/iaEJXNYjCkFAmaU8RIXHHVsZi5oYW5z c29uQGxpbmFyby5vcmcACgkQ/iaEJXNYjCnrbhAAqWQWOxXxZ9QHYgmE8K+fc96h 9e67dF2WjvBbipGEj63ijCRei9pChyHaIWPLSN/pHusfxTHaLqC2RTRf7Os/4TCm vwaITTvrIBxTHkocHVKDNUaODo/Mdc6WyhY8DUo+SyoZTvzKxy4QsmHDPsicJ6Q6 SxN01JrvNAHlOIRwgEm1BSuiL1qCOwg6vjdq/9I+3TVbFCLD8a9dYB8duWYTkupR HJqCeTQrrkucVi7LtGPwFZD50KnxK5/wMmug2jjHZ1jhS+iDI6WRoPGgyhlDyDNf 269Gveog7ewxK8Ny+h38FAgHwXvf0XuW47Zq4Pth7GdUnJH1n5AYGc0HETaFa0Xo +DnAm6xbWggSiAfzD63LwhRuv44hCE2vq3Ab10DYYcWC863qOis4t31VAyFsNq4m wQejAFPlZMQGUMjJMLRM9jPSYGakasvRjXwcVuv9DjFnku69lzroib8Z2eP6FR/t Q7DHVuq1lXbaVk4T4qV/yqgSjSOhEF5F/w1s+dYGygxfdY9Y5YH9dC8WBGtoqAUl K9w9UsA9qfVLvlLESRzHFF2oJaIdoqsTwcxykdq3WNaW+G2sGDf89rCpPvFvMLsj 43MWaxWs4dxS0okfr/hsGhBiCzIegqNbhxsrVdtn6BM/1qLnax7PjT2AEhP0oWL7 J4jvKcldHF4vNK5Kwlk= =ZIDp -----END PGP SIGNATURE----- Merge tag 'pmdomain-v6.11' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/linux-pm Pull pmdomain updates from Ulf Hansson: "pmdomain core: - Add support for HW-managed devices pmdomain providers: - amlogic: Add support for the A5 and the A4 power domains - arm: Enable system wakeups for the SCMI PM domain - qcom/clk: Add HW-mode callbacks to allow switching of GDSC mode pmdomain consumers: - qcom/media/venus: Enable support for switching GDSC HW-mode on V6" * tag 'pmdomain-v6.11' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/linux-pm: pmdomain: amlogic: Constify struct meson_secure_pwrc_domain_desc venus: pm_helpers: Use dev_pm_genpd_set_hwmode to switch GDSC mode on V6 clk: qcom: videocc: Use HW_CTRL_TRIGGER for SM8250, SC7280 vcodec GDSC's clk: qcom: gdsc: Add set and get hwmode callbacks to switch GDSC mode PM: domains: Add the domain HW-managed mode to the summary PM: domains: Allow devices attached to genpd to be managed by HW pmdomain: amlogic: Add support for A5 power domains controller dt-bindings: power: add Amlogic A5 power domains pmdomain: amlogic: add missing MODULE_DESCRIPTION() macros pmdomain: arm: scmi_pm_domain: set flag GENPD_FLAG_ACTIVE_WAKEUP pmdomain: renesas: rmobile-sysc: Use for_each_child_of_node_scoped() pmdomain: core: Use genpd_is_irq_safe() helper pmdomain: amlogic: Add support for A4 power domains controller dt-bindings: power: add Amlogic A4 power domains |
||
Drew Fustini
|
ae81b69fd2 |
clk: thead: Add support for T-Head TH1520 AP_SUBSYS clocks
Add support for the AP sub-system clock controller in the T-Head TH1520. This include CPU, DPU, GMAC and TEE PLLs. Link: https://openbeagle.org/beaglev-ahead/beaglev-ahead/-/blob/main/docs/TH1520%20System%20User%20Manual.pdf Co-developed-by: Yangtao Li <frank.li@vivo.com> Signed-off-by: Yangtao Li <frank.li@vivo.com> Co-developed-by: Jisheng Zhang <jszhang@kernel.org> Signed-off-by: Jisheng Zhang <jszhang@kernel.org> Link: https://git.beagleboard.org/beaglev-ahead/beaglev-ahead/-/tree/main/docs Signed-off-by: Drew Fustini <dfustini@tenstorrent.com> Link: https://lore.kernel.org/r/20240711-th1520-clk-v3-2-6ff17bb318fb@tenstorrent.com Signed-off-by: Stephen Boyd <sboyd@kernel.org> |
||
Nathan Chancellor
|
00c7ded680 |
clk: sophgo: Avoid -Wsometimes-uninitialized in sg2042_clk_pll_set_rate()
Clang warns (or errors with CONFIG_WERROR=y):
drivers/clk/sophgo/clk-sg2042-pll.c:396:6: error: variable 'ret' is used uninitialized whenever 'if' condition is true [-Werror,-Wsometimes-uninitialized]
396 | if (sg2042_pll_enable(pll, 0)) {
| ^~~~~~~~~~~~~~~~~~~~~~~~~
drivers/clk/sophgo/clk-sg2042-pll.c:418:9: note: uninitialized use occurs here
418 | return ret;
| ^~~
drivers/clk/sophgo/clk-sg2042-pll.c:396:2: note: remove the 'if' if its condition is always false
396 | if (sg2042_pll_enable(pll, 0)) {
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
397 | pr_warn("Can't disable pll(%s), status error\n", pll->hw.init->name);
| ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
398 | goto out;
| ~~~~~~~~~
399 | }
| ~
drivers/clk/sophgo/clk-sg2042-pll.c:393:9: note: initialize the variable 'ret' to silence this warning
393 | int ret;
| ^
| = 0
1 error generated.
sg2042_pll_enable() only ever returns zero, so this situation cannot
happen, but clang does not perform interprocedural analysis, so it
cannot know this to avoid the warning. Make it clearer to the compiler
by making sg2042_pll_enable() void and eliminate the error handling in
sg2042_clk_pll_set_rate(), which clears up the warning, as ret will
always be initialized.
Fixes:
|
||
Li Qiang
|
1f7a04a0e6 |
clk/sophgo: Using BUG() instead of unreachable() in mmux_get_parent_id()
In general it's a good idea to avoid using bare unreachable() because it
introduces undefined behavior in compiled code. but it caused a compilation warning,
Using BUG() instead of unreachable() to resolve compilation warnings.
Fixes the following warnings:
drivers/clk/sophgo/clk-cv18xx-ip.o: warning: objtool: mmux_round_rate() falls through to next function bypass_div_round_rate()
Fixes:
|
||
Thorsten Blum
|
12b02b6359 |
clk: mxs: Use clamp() in clk_ref_round_rate() and clk_ref_set_rate()
Use clamp() instead of duplicating its implementation. Signed-off-by: Thorsten Blum <thorsten.blum@toblux.com> Link: https://lore.kernel.org/r/20240710143309.706135-2-thorsten.blum@toblux.com Signed-off-by: Stephen Boyd <sboyd@kernel.org> |
||
Javier Carrasco
|
38bded8154 |
clk: sunxi-ng r40: Constify struct regmap_config
`sun8i_r40_ccu_regmap_config` is not modified and can be declared as const to move its data to a read-only section. Signed-off-by: Javier Carrasco <javier.carrasco.cruz@gmail.com> Link: https://lore.kernel.org/r/20240703-clk-const-regmap-v1-9-7d15a0671d6f@gmail.com Reviewed-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org> |
||
|
Stephen Boyd
|
691a018040 |
A few more Qualcomm clk updates for v6.11
This introduces helper logic to expose clock controllers as simple interconnect providers, and used this on ipq9574 to add the the system's interconnect providers. CLK_SET_RATE_PARENT is added to the remaining USB pipe clocks on X1Elite. Error handling is improved in kpss-xcc, and lastly the SC8280XP LPASS clock controller regmap_config is declared const. -----BEGIN PGP SIGNATURE----- iQJJBAABCAAzFiEEBd4DzF816k8JZtUlCx85Pw2ZrcUFAmaNkZcVHGFuZGVyc3Nv bkBrZXJuZWwub3JnAAoJEAsfOT8Nma3FuasQALZ431btBHhZ9HqmBsVgQ24yqU1A 3b+YQ/9v+ESInbdujxRt5v0KDjWJyNGFHYQKnHO/rxx7YbZsD6QW/qxFGnh7+h2Z BFbi1+QWokmXXPUXJMybA2nF1rMcTczu8Pqpu5W/Jl+0mtssO9jSXzZnvuxs9DEH 5SkDpyE3W4oUDiNG7e2dny7/g9qLefMNivWPqqaqx6yUtlP/lwJm+W3vBdTCpYLW bbovj5uA6h2jTVzIkk4YRi8DDubzs3i9RGKizzhXUh5LkOm/cDmXN3LVf4aHOfF1 TKhQcL0nouGdHqRltbo3+TyDQnFApSLHCXs1tG9NjoW0xVj409fGrUS2ViPmlXBH q7UR7fDdl86bCjP8Oz92Vh/y4IYHPVHm3xIIet6y1ETEv5KW8D8pra/c4NNrw/RW HT+MtFd+5jf+lVZfG7xQWZYYMjyL1hwI8tEE0uCsKB4nYvWvRaj7EUFna403BeE1 YJAZbnAxfYpJl9s3UoBPJgjxmIMrt9R8NUCaOmbUxBw80nQTvp0DeGvp9Fc0pJTT Z+JCbGSl/ghy2bKkeU+Cwy4L7KJGNC51QGhYRSRi01IxPM3kPnfA7utRj6O6pdhe HN+S670tw7NISsZyQ4fNm5t8yZlnhXuSoxtNFSLTnLiUhdngpYc+kYCep5t+zcWi 13dAX2Q9vaat5x4l =IynE -----END PGP SIGNATURE----- Merge tag 'qcom-clk-for-6.11-2' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into clk-qcom Pull more qcom clk driver updates from Bjorn Andersson: - Introduces helper logic to expose clock controllers as simple interconnect providers - Use the interconnect helper above on Qualcomm ipq9574 - Add CLK_SET_RATE_PARENT to the remaining USB pipe clocks on Qualcomm X1Elite. - Improve error handling in Qualcomm kpss-xcc driver - Mark Qualcomm SC8280XP LPASS clock controller regmap_config const * tag 'qcom-clk-for-6.11-2' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: clk: qcom: ipq9574: Use icc-clk for enabling NoC related clocks clk: qcom: common: Add interconnect clocks support interconnect: icc-clk: Add devm_icc_clk_register interconnect: icc-clk: Specify master/slave ids dt-bindings: clock: qcom: Add AHB clock for SM8150 clk: qcom: gcc-x1e80100: Set parent rate for USB3 sec and tert PHY pipe clks dt-bindings: interconnect: Add Qualcomm IPQ9574 support clk: qcom: kpss-xcc: Return of_clk_add_hw_provider to transfer the error clk: qcom: lpasscc-sc8280xp: Constify struct regmap_config |
||
Jagadeesh Kona
|
4c2aecac62 |
clk: qcom: videocc: Use HW_CTRL_TRIGGER for SM8250, SC7280 vcodec GDSC's
For Venus V6 variant SoCs(sm8250, sc7280), the venus driver uses the newly introduced dev_pm_genpd_set_hwmode() API to switch the vcodec GDSC to HW/SW control modes at runtime. Hence use HW_CTRL_TRIGGER flag for vcodec GDSC's on sm8250, sc7280 to register the set_hwmode_dev & get_hwmode_dev callbacks for vcodec GDSC and allow the GDSC mode to be changed using dev_pm_genpd_set_hwmode() API. Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Reviewed-by: Taniya Das <quic_tdas@quicinc.com> Acked-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20240624044809.17751-5-quic_jkona@quicinc.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> |
||
|
Jagadeesh Kona
|
f7ccdaad61 |
clk: qcom: gdsc: Add set and get hwmode callbacks to switch GDSC mode
Some GDSC client drivers require the GDSC mode to be switched dynamically to HW mode at runtime to gain the power benefits. Typically such client drivers require the GDSC to be brought up in SW mode initially to enable the required dependent clocks and configure the hardware to proper state. Once initial hardware set up is done, they switch the GDSC to HW mode to save power. At the end of usecase, they switch the GDSC back to SW mode and disable the GDSC. Introduce HW_CTRL_TRIGGER flag to register the set_hwmode_dev and get_hwmode_dev callbacks for GDSC's whose respective client drivers require the GDSC mode to be switched dynamically at runtime using dev_pm_genpd_set_hwmode() API. Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Reviewed-by: Taniya Das <quic_tdas@quicinc.com> Reviewed-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20240624044809.17751-4-quic_jkona@quicinc.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> |
||
Lorenzo Bianconi
|
58c53d4314 |
clk: en7523: fix rate divider for slic and spi clocks
Introduce div_offset field in en_clk_desc struct in order to fix rate
divider estimation in en7523_get_div routine for slic and spi fixed
rate clocks.
Moreover, fix base_shift for crypto clock.
Fixes:
|
||
|
Javier Carrasco
|
7b34303d9d |
clk: lpc32xx: Constify struct regmap_config
`lpc32xx_scb_regmap_config` is not modified and can be declared as const to move its data to a read-only section. Signed-off-by: Javier Carrasco <javier.carrasco.cruz@gmail.com> Link: https://lore.kernel.org/r/20240703-clk-const-regmap-v1-7-7d15a0671d6f@gmail.com Signed-off-by: Stephen Boyd <sboyd@kernel.org> |
||
|
Javier Carrasco
|
db8061ef91 |
clk: xilinx: Constify struct regmap_config
`vcu_settings_regmap_config` is not modified and can be declared as const to move its data to a read-only section. Signed-off-by: Javier Carrasco <javier.carrasco.cruz@gmail.com> Link: https://lore.kernel.org/r/20240703-clk-const-regmap-v1-10-7d15a0671d6f@gmail.com Signed-off-by: Stephen Boyd <sboyd@kernel.org> |
||
|
Lorenzo Bianconi
|
bf288bd25d |
clk: en7523: Remove PCIe reset open drain configuration for EN7581
PCIe reset open drain configuration will be managed by pinctrl driver. Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org> Link: https://lore.kernel.org/r/43276af5f08a554b4ab2e52e8d437fff5c06a732.1719485847.git.lorenzo@kernel.org Signed-off-by: Stephen Boyd <sboyd@kernel.org> |
||
|
Lorenzo Bianconi
|
db7a4a11e8 |
clk: en7523: Remove pcie prepare/unpreare callbacks for EN7581 SoC
Get rid of prepare and unpreare callbacks for PCIe clock since they can be modeled as a reset line cosumed by the PCIe driver (pcie-mediatek-gen3) Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Tested-by: Zhengping Zhang <zhengping.zhang@airoha.com> Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org> Link: https://lore.kernel.org/r/16df149975514d3030499c48fc1c64f090093595.1719485847.git.lorenzo@kernel.org Signed-off-by: Stephen Boyd <sboyd@kernel.org> |
||
|
Lorenzo Bianconi
|
e0d8ea4ed5 |
clk: en7523: Add reset-controller support for EN7581 SoC
Introduce reset API support to EN7581 clock driver. Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Tested-by: Zhengping Zhang <zhengping.zhang@airoha.com> Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org> Link: https://lore.kernel.org/r/4f735d17e549ea53769bf5a3f50406debb879a44.1719485847.git.lorenzo@kernel.org Signed-off-by: Stephen Boyd <sboyd@kernel.org> |
||
Alper Nebi Yasak
|
7f294d10eb |
clk: mediatek: mt8173-infracfg: Handle unallocated infracfg when module
The MT8173 infracfg clock driver does initialization in two steps, via a CLK_OF_DECLARE_DRIVER declaration. However its early init function doesn't get to run when it's built as a module, presumably since it's not loaded by the time it would have been called by of_clk_init(). This causes its second-step probe() to return -ENOMEM when trying to register clocks, as the necessary clock_data struct isn't initialized by the first step. MT2701 and MT6797 clock drivers also use this mechanism, but they try to allocate the necessary clock_data structure if missing in the second step. Mimic that for the MT8173 infracfg clock as well to make it work as a module. Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com> Link: https://lore.kernel.org/r/20240612201211.91683-1-alpernebiyasak@gmail.com Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org> |
||
|
Stephen Boyd
|
01a0a6cc8c |
clk: qcom: Park shared RCGs upon registration
There's two problems with shared RCGs. The first problem is that they incorrectly report the parent after commit |
||
Varadarajan Narayanan
|
23711cabe1 |
clk: qcom: ipq9574: Use icc-clk for enabling NoC related clocks
Use the icc-clk framework to enable few clocks to be able to create paths and use the peripherals connected on those NoCs. Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240430064214.2030013-6-quic_varada@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org> |
||
|
Varadarajan Narayanan
|
8737ec830e |
clk: qcom: common: Add interconnect clocks support
Unlike MSM platforms that manage NoC related clocks and scaling from RPM, IPQ SoCs dont involve RPM in managing NoC related clocks and there is no NoC scaling. However, there is a requirement to enable some NoC interface clocks for accessing the peripheral controllers present on these NoCs. Though exposing these as normal clocks would work, having a minimalistic interconnect driver to handle these clocks would make it consistent with other Qualcomm platforms resulting in common code paths. This is similar to msm8996-cbf's usage of icc-clk framework. Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com> Link: https://lore.kernel.org/r/20240430064214.2030013-5-quic_varada@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org> |
||
|
Varadarajan Narayanan
|
f45b94ffc5 |
interconnect: icc-clk: Specify master/slave ids
Presently, icc-clk driver autogenerates the master and slave ids. However, devices with multiple nodes on the interconnect could have other constraints and may not match with the auto generated node ids. Hence, modify the driver to use the master/slave ids provided by the caller instead of auto generating. Also, update clk-cbf-8996 accordingly. Acked-by: Georgi Djakov <djakov@kernel.org> Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com> Link: https://lore.kernel.org/r/20240430064214.2030013-2-quic_varada@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org> |
||
|
Abel Vesa
|
14539c8897 |
clk: qcom: gcc-x1e80100: Set parent rate for USB3 sec and tert PHY pipe clks
Allow the USB3 second and third GCC PHY pipe clocks to propagate the
rate to the pipe clocks provided by the QMP combo PHYs. The first
instance is already doing that.
Fixes:
|
||
Arnd Bergmann
|
2d61b9303c |
Qualcomm Arm64 DeviceTree updates for v6.11
This introduces 11 new boards, namely: * ASUS Vivobook S 15 * Lenovo Smart Tab M10 DTS * Motorola Moto E 2015 LTE (surnia) * Motorola Moto G 2015 (osprey) * Motorola Moto G4 Play (harpia) * Qualcomm AIM300 AIoT development board * Qualcomm SM8650 Hardware Development Kit (HDK) * SHIFTphone 8 * Samsung Galaxy Z Fold5 * Schneider HMIBSC board DTS * TP-Link Archer AX55 v1 Of particular interest here is the Asus Vivobook, the first supported X1 Elite consumer laptop. For IPQ6018 an SDHCI controller is added and on IPQ9574 an MDIO bus is described. The improvements to MSM8916-based devices continues, with sound and mdoem support added to Acer Iconia Talk S and GPLUS FL8005A, the latter also gaining BMS support. Samsung Galaxy devices gains PMIC and charger definitions, NFC support and MUIC. Accelerometer and magnetometer support is added to the Samsung Galaxy Grand Prime devices. On MSM8976 definitions for IOMMU, the display subsystem, wifi subsystem, and Adreno GPU are added. On MSM8996 UFS core clock frequencies are specified, FastRPC nodes are added for the audio DSP, glink-edges are described where available, the display subsystem reset is added. Venus is introduced on MSM8998 and the "No MSA Ready" quirk is added to allow ath10k to come up. GPU support is added to QCM2290 and enabled on the RB1 development board. The I2C controller used for communicating with the LT9611UXC HDMI bridge is temporarily replaced with i2c-gpio while issues with the builtin controller is diagnosed. The same is done for RB2, on the QRB4210 platform. On RB2 TCPM max current draw is corrected and the vreg_l9a regulator is marked as always on to match expectations. On the QDU1000 platform, USB is added, secure QFPROM is introduced to allow LLCC to access OTP data. USB is enabled on the two IDP boards. SA8775p gains PCIe endpoint definitions, LLCCC support, IMEM and PIL info regions. Nodes are marked as dma-coherent as needed, a dedicated carveout for shared memory bridge allocations is introduced. The SA8775P ride device is split in the two versions r2 and r3. The SC7180 Trogdor clamshell/detachable fragments are refactored for convenience, and pwmleds are disabled where unused. On SC7280 the APR nodes for interfacing with the audio services in audio DSP firmware are introduced. The Qualcomm SMMU TBUs are described, to enable improved debug support. QoS clocks are added to interconnects, as needed in order to operate the QoS settings on some buses. SuperSpeed in park is disabled for the primary DWC3 instance to address host controller issues under load. The PM8008 (camera PMIC) is introduced in Fairphone 5, regulators are named for better output, and firmware name for IPA is adjusted to the preferred file format. The HDMI bridge on Rb3gen2 is described, rtc, gpi-dma and qup nodes are enabled. The Type-C port manager found in PM7250b is enabled, for targets not using pmic-glink firmware for Type-C management. SC8180X gets a number of smaller corrections, and some cleanups - related to both functional issues and DeviceTree validation. The PSHOLD node is marked reserved, after reports that this causes issues during shutdown. Description of the USB signals are updated to match the signal path. The PM8008 camera PMIC is added to Lenovo ThinkPad X13s. The PM660 PMIC is extended with charger and rradc definitions, and the SDM670 gains a SMEM region definition. On SDM845 the Qualcomm SMMU TBU nodes are described, to enable improved debug output during faults etc. The UFS PHY is associated with its GDSC, and the DisplayPort controller is wired up to the QMP PHY. The Lenovo Yoga C630 Embedded Controller is introduced, adding battery and Type-C port management and altmode support. The C630 also gains WiFI calibration variant information, to cause selection of the right data. The missing IPA firmware path is corrected. For the SDX75 platform, AOSS, IPCC, SDHCI, TCSR, modem SMP2P, I2C and SPI nodes are introduced. SD-card support is added to the IDP board. CPUfreq support is introduced for the SM4450 platform. Missing reset is added to the SDHC controller of SM6115. The UFS PHY is associated with its GDSC, so is the PHY on SM6350. On Fairphone 4, the camera pmic (PM8008) is introduced, regulators are named for more informative debug output, and USB role switching is enabled. On the Fairphone 3, vibrator support is added and enabled. On SM8250, the USB signal paths are properly described in the OF graph, the UFS PHY gains its required power-domains description. Thanks to the introduction of PCI power sequence support, the QRB5165 RB5 WiFi chip can now be powered up, so this is added. Touchscreen interrupt flags are corrected accross a number of Sony Xperia devices, to remove the unexpected traces from downstream. On SM8450 an OPP-table is introduced for the PCIe controllers, to specify the bandwidth and performance state requirements for the different genrations and link widths. For this the PCIe controllers also gains interconnect path definitions. The LLCC register layout is corrected, and the UFS PHY is associated with its GDSC. On the SM8550 development boards speaker port mapping is added. WiFi support is finally enabled on the QRD board. The new AIM300 development platform/board is introduced. For SM8650 video and camera clock controller are introduced. SCM node gains details necessary to trigger USB ramdump (download mode) upon a system crash. WiFi support and speaker port mapping is added to the QRD and the newly introduced HDK. On the MTP the USB Type-C connector is describe to be routed to the PHY. In addition to the base HDK, a Display Card overlay is also introduced. For X1 Elite bwmon, fastrpc and GPU support, tsens, and the missing PCIe 6a instance are added. Thermal zones are described. Pmic-glink is introduced for both CRD and QCP devices, and remaining PMICs are described. Audio support is also added to the QCP. An explicit, larger, chunk of CMA memory is added to the various devices, in order to compensate for the lack of IOMMU for PCIe. Across a wide range of platforms, the thermal zone polling delays are removed as supplies are interrupt driven anyways. Also thermal related is the introduction of GPU thermal throttling, across many SoCs. The old SMSM implementation is finally transitioned to using the mailbox-based description and implementation for invoking interrupts on remote processors. As such interrupt-triggering is converted to use this mechanism on related platforms. The usb-role-switch property is removed for all USB instances hard coded to either host or peripheral across a range of boards. -----BEGIN PGP SIGNATURE----- iQJJBAABCAAzFiEEBd4DzF816k8JZtUlCx85Pw2ZrcUFAmaJfz0VHGFuZGVyc3Nv bkBrZXJuZWwub3JnAAoJEAsfOT8Nma3FxOMQALOlJsncvYy+WBZ+ganw3VTY43x+ CYtmM+cvy/oEEmqLLKWO63XyPtiDuhwjjmjO9H7019Zhi7dB2odXfr8PH4Wz315G /nW99uEoR1kgdHtMwMhBv+gMSf00c6D5X3fbFxVbt2lqlaB9blZeqbA/PsAcC2Dr FId/ji6/cMdEmC1qbWtvBMSc9Cku7WNt/90qe9q5KuwKbRVF/FKPj+lfBxGnrjQ8 vaKHmqVOYSV+cfuWqA/HrIe3WUds9eXv/F+O2nx22BTqEiBmlOxVR63LwQGFV9D+ fOpRaIR30TxBk+DK/i4jnNu7UEA9lPf//0RDiKeyySAffLfQWBpURGcRUrF6X+yz 7qdi8Ep/L1v7M+FKdPdCDooVxM91JHErPB65+/T/gLbI2Oe7MZED+hY/3UcTY8cr SkSH+3VeZk8M4DDFuVdgXcTBk1d/d1zqaKKokm9IkIqdAspDYJNvlOHMfgg1bsQe Ny9epqR+RR5wFulJ0W0YWGibOYkcubduAytvtad1lawmSTCmMI8SZb8K9n1l2RI3 vYEgaSfOo0SHprgZlpULc+LqPF9n9W2RrME8iFIqpfsZ9ovFccr3QgNbHdtVZyoN t0DhAUk5UKEM4iQ4vf/7+T2WjFA2LMAg1Bznv8X4L69BVkAH/VwRudbwQe429Yqm psehVa9nc/+upil7 =Hsda -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEiK/NIGsWEZVxh/FrYKtH/8kJUicFAmaL+k8ACgkQYKtH/8kJ UiffeBAAlBRO7Pp8MCFco+63SXZQTGJ0UXmmrkWLiXW6iCGDuUrllCLuygOGZx8O FVQ9dBQ5AXQbOy++LTYvHIzWt3pCJSIlnbhiv9Na04IgBFnZ3Uy+e+Iikq25o51M gC2lIvLfwDaTVe8KMvLdNoTUN7jWFv6dZerNo35K6mLxf5nwU6bucljM2Vn0naSK 6G4HMXA+ByvCMgSVOp4/5Qd3+XadH8604W+48n6aRM9YtLhTgV2bRRNY23y8hiAI IItgCMjzS30mbd6yrnXJOix0IoNhe9IxNKoKh8P0+G0CvAzH8s7KcVAlU+tiTsnR 0vMKYcYPK6PW8T4umHSvTTEG3HR+uvC5vyWAnCKvlx2OElD80JoVp/IWvmy4n9Fv U3hltgntDkn8raupGgQ9oeM6EoVR6fq5UtzuaZgkElWyuSigVK9jOsG8hrqf1gdo w7I6APX4c1D8ArEvCbBUmff0hy4LqnScwz+7evFwZORMDYiYxhy2ybRZVYGknozA miEkVGZr+MHLCszF8kzetHOFhhddqvTWx6IEh/5SMPTkqnGfaOTc667rJ/hfHt8/ 8AYw3dfpKrXsf3KxeNVlVpJDNexZU3yHK2glNEpr0yvXAuYYXfmXhhNo2DHNDzyg VHd6J24UoWMpQisszsfFPBtBsianBTzsPhfCfmprg8um2f0MaKY= =2vUa -----END PGP SIGNATURE----- Merge tag 'qcom-arm64-for-6.11' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/dt Qualcomm Arm64 DeviceTree updates for v6.11 This introduces 11 new boards, namely: * ASUS Vivobook S 15 * Lenovo Smart Tab M10 DTS * Motorola Moto E 2015 LTE (surnia) * Motorola Moto G 2015 (osprey) * Motorola Moto G4 Play (harpia) * Qualcomm AIM300 AIoT development board * Qualcomm SM8650 Hardware Development Kit (HDK) * SHIFTphone 8 * Samsung Galaxy Z Fold5 * Schneider HMIBSC board DTS * TP-Link Archer AX55 v1 Of particular interest here is the Asus Vivobook, the first supported X1 Elite consumer laptop. For IPQ6018 an SDHCI controller is added and on IPQ9574 an MDIO bus is described. The improvements to MSM8916-based devices continues, with sound and mdoem support added to Acer Iconia Talk S and GPLUS FL8005A, the latter also gaining BMS support. Samsung Galaxy devices gains PMIC and charger definitions, NFC support and MUIC. Accelerometer and magnetometer support is added to the Samsung Galaxy Grand Prime devices. On MSM8976 definitions for IOMMU, the display subsystem, wifi subsystem, and Adreno GPU are added. On MSM8996 UFS core clock frequencies are specified, FastRPC nodes are added for the audio DSP, glink-edges are described where available, the display subsystem reset is added. Venus is introduced on MSM8998 and the "No MSA Ready" quirk is added to allow ath10k to come up. GPU support is added to QCM2290 and enabled on the RB1 development board. The I2C controller used for communicating with the LT9611UXC HDMI bridge is temporarily replaced with i2c-gpio while issues with the builtin controller is diagnosed. The same is done for RB2, on the QRB4210 platform. On RB2 TCPM max current draw is corrected and the vreg_l9a regulator is marked as always on to match expectations. On the QDU1000 platform, USB is added, secure QFPROM is introduced to allow LLCC to access OTP data. USB is enabled on the two IDP boards. SA8775p gains PCIe endpoint definitions, LLCCC support, IMEM and PIL info regions. Nodes are marked as dma-coherent as needed, a dedicated carveout for shared memory bridge allocations is introduced. The SA8775P ride device is split in the two versions r2 and r3. The SC7180 Trogdor clamshell/detachable fragments are refactored for convenience, and pwmleds are disabled where unused. On SC7280 the APR nodes for interfacing with the audio services in audio DSP firmware are introduced. The Qualcomm SMMU TBUs are described, to enable improved debug support. QoS clocks are added to interconnects, as needed in order to operate the QoS settings on some buses. SuperSpeed in park is disabled for the primary DWC3 instance to address host controller issues under load. The PM8008 (camera PMIC) is introduced in Fairphone 5, regulators are named for better output, and firmware name for IPA is adjusted to the preferred file format. The HDMI bridge on Rb3gen2 is described, rtc, gpi-dma and qup nodes are enabled. The Type-C port manager found in PM7250b is enabled, for targets not using pmic-glink firmware for Type-C management. SC8180X gets a number of smaller corrections, and some cleanups - related to both functional issues and DeviceTree validation. The PSHOLD node is marked reserved, after reports that this causes issues during shutdown. Description of the USB signals are updated to match the signal path. The PM8008 camera PMIC is added to Lenovo ThinkPad X13s. The PM660 PMIC is extended with charger and rradc definitions, and the SDM670 gains a SMEM region definition. On SDM845 the Qualcomm SMMU TBU nodes are described, to enable improved debug output during faults etc. The UFS PHY is associated with its GDSC, and the DisplayPort controller is wired up to the QMP PHY. The Lenovo Yoga C630 Embedded Controller is introduced, adding battery and Type-C port management and altmode support. The C630 also gains WiFI calibration variant information, to cause selection of the right data. The missing IPA firmware path is corrected. For the SDX75 platform, AOSS, IPCC, SDHCI, TCSR, modem SMP2P, I2C and SPI nodes are introduced. SD-card support is added to the IDP board. CPUfreq support is introduced for the SM4450 platform. Missing reset is added to the SDHC controller of SM6115. The UFS PHY is associated with its GDSC, so is the PHY on SM6350. On Fairphone 4, the camera pmic (PM8008) is introduced, regulators are named for more informative debug output, and USB role switching is enabled. On the Fairphone 3, vibrator support is added and enabled. On SM8250, the USB signal paths are properly described in the OF graph, the UFS PHY gains its required power-domains description. Thanks to the introduction of PCI power sequence support, the QRB5165 RB5 WiFi chip can now be powered up, so this is added. Touchscreen interrupt flags are corrected accross a number of Sony Xperia devices, to remove the unexpected traces from downstream. On SM8450 an OPP-table is introduced for the PCIe controllers, to specify the bandwidth and performance state requirements for the different genrations and link widths. For this the PCIe controllers also gains interconnect path definitions. The LLCC register layout is corrected, and the UFS PHY is associated with its GDSC. On the SM8550 development boards speaker port mapping is added. WiFi support is finally enabled on the QRD board. The new AIM300 development platform/board is introduced. For SM8650 video and camera clock controller are introduced. SCM node gains details necessary to trigger USB ramdump (download mode) upon a system crash. WiFi support and speaker port mapping is added to the QRD and the newly introduced HDK. On the MTP the USB Type-C connector is describe to be routed to the PHY. In addition to the base HDK, a Display Card overlay is also introduced. For X1 Elite bwmon, fastrpc and GPU support, tsens, and the missing PCIe 6a instance are added. Thermal zones are described. Pmic-glink is introduced for both CRD and QCP devices, and remaining PMICs are described. Audio support is also added to the QCP. An explicit, larger, chunk of CMA memory is added to the various devices, in order to compensate for the lack of IOMMU for PCIe. Across a wide range of platforms, the thermal zone polling delays are removed as supplies are interrupt driven anyways. Also thermal related is the introduction of GPU thermal throttling, across many SoCs. The old SMSM implementation is finally transitioned to using the mailbox-based description and implementation for invoking interrupts on remote processors. As such interrupt-triggering is converted to use this mechanism on related platforms. The usb-role-switch property is removed for all USB instances hard coded to either host or peripheral across a range of boards. * tag 'qcom-arm64-for-6.11' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (279 commits) dt-bindings: arm: qcom: Document samsung,ms013g arm64: dts: qcom: Add device tree for ASUS Vivobook S 15 dt-bindings: arm: qcom: Add ASUS Vivobook S 15 arm64: dts: qcom: qrb4210-rb2: Correct max current draw for VBUS arm64: dts: qcom: msm8998: add venus node arm64: dts: qcom: sa8775p-ride-r3: add new board file arm64: dts: qcom: move common parts for sa8775p-ride variants into a .dtsi dt-bindings: arm: qcom: add sa8775p-ride Rev 3 arm64: dts: qcom: sm8550-qrd: add port mapping to speakers arm64: dts: qcom: sm8550-mtp: add port mapping to speakers arm64: dts: qcom: sm8550-hdk: add port mapping to speakers arm64: dts: qcom: sm8650-qrd: add port mapping to speakers arm64: dts: qcom: sm8650-mtp: add port mapping to speakers arm64: dts: qcom: sm8650-hdk: add port mapping to speakers arm64: dts: qcom: sm7225-fairphone-fp4: Name the regulators arm64: dts: qcom: pm8916: correct thermal zone name arm64: dts: qcom: x1e80100: Add gpu support arm64: dts: qcom: x1e80100: Fix USB HS PHY 0.8V supply arm64: dts: qcom: qcs6490-rb3gen2: enable hdmi bridge arm64: dts: qcom: sm6115: add resets for sdhc_1 ... Link: https://lore.kernel.org/r/20240706173140.18887-1-andersson@kernel.org Signed-off-by: Arnd Bergmann <arnd@arndb.de> |
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Linus Torvalds
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5a4bd506dd |
A set of clk fixes for the Qualcomm, Mediatek, and Allwinner drivers:
- Fix the Qualcomm Stromer Plus PLL set_rate() clk_op to explicitly set
the alpha enable bit and not set bits that don't exist
- Mark Qualcomm IPQ9574 crypto clks as voted to avoid stuck clk
warnings
- Fix the parent of some PLLs on Qualcomm sm6530 so their rate is
correct
- Fix the min/max rate clamping logic in the Allwinner driver that got
broken in v6.9
- Limit runtime PM enabling in the Mediatek driver to only
mt8183-mfgcfg so that system wide resume doesn't break on other
Mediatek SoCs
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Merge tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull clk fixes from Stephen Boyd:
"A set of clk fixes for the Qualcomm, Mediatek, and Allwinner drivers:
- Fix the Qualcomm Stromer Plus PLL set_rate() clk_op to explicitly
set the alpha enable bit and not set bits that don't exist
- Mark Qualcomm IPQ9574 crypto clks as voted to avoid stuck clk
warnings
- Fix the parent of some PLLs on Qualcomm sm6530 so their rate is
correct
- Fix the min/max rate clamping logic in the Allwinner driver that
got broken in v6.9
- Limit runtime PM enabling in the Mediatek driver to only
mt8183-mfgcfg so that system wide resume doesn't break on other
Mediatek SoCs"
* tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux:
clk: mediatek: mt8183: Only enable runtime PM on mt8183-mfgcfg
clk: sunxi-ng: common: Don't call hw_to_ccu_common on hw without common
clk: qcom: gcc-ipq9574: Add BRANCH_HALT_VOTED flag
clk: qcom: apss-ipq-pll: remove 'config_ctl_hi_val' from Stromer pll configs
clk: qcom: clk-alpha-pll: set ALPHA_EN bit for Stromer Plus PLLs
clk: qcom: gcc-sm6350: Fix gpll6* & gpll7 parents
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