Input: tegra-kbc - use reset framework

Tegra's clock driver now provides an implementation of the common
reset API (include/linux/reset.h). Use this instead of the old Tegra-
specific API; that will soon be removed.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Dmitry Torokhov <dmitry.torokhov@gmail.com>
Reviewed-by: Thierry Reding <treding@nvidia.com>
This commit is contained in:
Stephen Warren 2013-11-06 16:48:16 -07:00
parent c2b329f561
commit fe6b0dfaba

View File

@ -31,7 +31,7 @@
#include <linux/clk.h> #include <linux/clk.h>
#include <linux/slab.h> #include <linux/slab.h>
#include <linux/input/matrix_keypad.h> #include <linux/input/matrix_keypad.h>
#include <linux/clk/tegra.h> #include <linux/reset.h>
#include <linux/err.h> #include <linux/err.h>
#define KBC_MAX_KPENT 8 #define KBC_MAX_KPENT 8
@ -116,6 +116,7 @@ struct tegra_kbc {
u32 wakeup_key; u32 wakeup_key;
struct timer_list timer; struct timer_list timer;
struct clk *clk; struct clk *clk;
struct reset_control *rst;
const struct tegra_kbc_hw_support *hw_support; const struct tegra_kbc_hw_support *hw_support;
int max_keys; int max_keys;
int num_rows_and_columns; int num_rows_and_columns;
@ -373,9 +374,9 @@ static int tegra_kbc_start(struct tegra_kbc *kbc)
clk_prepare_enable(kbc->clk); clk_prepare_enable(kbc->clk);
/* Reset the KBC controller to clear all previous status.*/ /* Reset the KBC controller to clear all previous status.*/
tegra_periph_reset_assert(kbc->clk); reset_control_assert(kbc->rst);
udelay(100); udelay(100);
tegra_periph_reset_deassert(kbc->clk); reset_control_assert(kbc->rst);
udelay(100); udelay(100);
tegra_kbc_config_pins(kbc); tegra_kbc_config_pins(kbc);
@ -663,6 +664,12 @@ static int tegra_kbc_probe(struct platform_device *pdev)
return PTR_ERR(kbc->clk); return PTR_ERR(kbc->clk);
} }
kbc->rst = devm_reset_control_get(&pdev->dev, "kbc");
if (IS_ERR(kbc->rst)) {
dev_err(&pdev->dev, "failed to get keyboard reset\n");
return PTR_ERR(kbc->rst);
}
/* /*
* The time delay between two consecutive reads of the FIFO is * The time delay between two consecutive reads of the FIFO is
* the sum of the repeat time and the time taken for scanning * the sum of the repeat time and the time taken for scanning