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Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-next into net-accept-more

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* git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-next: (1557 commits)
  net: qede: use extack in qede_parse_actions()
  net: qede: propagate extack through qede_flow_spec_validate()
  net: qede: use faked extack in qede_flow_spec_to_rule()
  net: qede: use extack in qede_parse_flow_attr()
  net: qede: add extack in qede_add_tc_flower_fltr()
  net: qede: use extack in qede_flow_parse_udp_v4()
  net: qede: use extack in qede_flow_parse_udp_v6()
  net: qede: use extack in qede_flow_parse_tcp_v4()
  net: qede: use extack in qede_flow_parse_tcp_v6()
  net: qede: use extack in qede_flow_parse_v4_common()
  net: qede: use extack in qede_flow_parse_v6_common()
  net: qede: use extack in qede_set_v4_tuple_to_profile()
  net: qede: use extack in qede_set_v6_tuple_to_profile()
  net: qede: use extack in qede_flow_parse_ports()
  net: usb: smsc95xx: stop lying about skb->truesize
  net: dsa: microchip: Fix spellig mistake "configur" -> "configure"
  af_unix: Add dead flag to struct scm_fp_list.
  net: ethernet: adi: adin1110: Replace linux/gpio.h by proper one
  octeontx2-pf: Reuse Transmit queue/Send queue index of HTB class
  gve: Use ethtool_sprintf/puts() to fill stats strings
  ...
This commit is contained in:
Jens Axboe 2024-05-11 08:25:55 -06:00
commit fe6532b44a
1760 changed files with 78392 additions and 33266 deletions
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109
Documentation/bpf/standardization/instruction-set.rst
View File

@ -5,7 +5,11 @@
BPF Instruction Set Architecture (ISA)
======================================
This document specifies the BPF instruction set architecture (ISA).
eBPF (which is no longer an acronym for anything), also commonly
referred to as BPF, is a technology with origins in the Linux kernel
that can run untrusted programs in a privileged context such as an
operating system kernel. This document specifies the BPF instruction
set architecture (ISA).
Documentation conventions
=========================
@ -43,7 +47,7 @@ a type's signedness (`S`) and bit width (`N`), respectively.
===== =========
For example, `u32` is a type whose valid values are all the 32-bit unsigned
numbers and `s16` is a types whose valid values are all the 16-bit signed
numbers and `s16` is a type whose valid values are all the 16-bit signed
numbers.
Functions
@ -108,7 +112,7 @@ conformance group means it must support all instructions in that conformance
group.
The use of named conformance groups enables interoperability between a runtime
that executes instructions, and tools as such compilers that generate
that executes instructions, and tools such as compilers that generate
instructions for the runtime. Thus, capability discovery in terms of
conformance groups might be done manually by users or automatically by tools.
@ -181,10 +185,13 @@ A basic instruction is encoded as follows::
(`64-bit immediate instructions`_ reuse this field for other purposes)
**dst_reg**
destination register number (0-10)
destination register number (0-10), unless otherwise specified
(future instructions might reuse this field for other purposes)
**offset**
signed integer offset used with pointer arithmetic
signed integer offset used with pointer arithmetic, except where
otherwise specified (some arithmetic instructions reuse this field
for other purposes)
**imm**
signed integer immediate value
@ -228,10 +235,12 @@ This is depicted in the following figure::
operation to perform, encoded as explained above
**regs**
The source and destination register numbers, encoded as explained above
The source and destination register numbers (unless otherwise
specified), encoded as explained above
**offset**
signed integer offset used with pointer arithmetic
signed integer offset used with pointer arithmetic, unless
otherwise specified
**imm**
signed integer immediate value
@ -342,8 +351,8 @@ where '(u32)' indicates that the upper 32 bits are zeroed.
dst = dst ^ imm
Note that most instructions have instruction offset of 0. Only three instructions
(``SDIV``, ``SMOD``, ``MOVSX``) have a non-zero offset.
Note that most arithmetic instructions have 'offset' set to 0. Only three instructions
(``SDIV``, ``SMOD``, ``MOVSX``) have a non-zero 'offset'.
Division, multiplication, and modulo operations for ``ALU`` are part
of the "divmul32" conformance group, and division, multiplication, and
@ -365,15 +374,15 @@ Note that there are varying definitions of the signed modulo operation
when the dividend or divisor are negative, where implementations often
vary by language such that Python, Ruby, etc. differ from C, Go, Java,
etc. This specification requires that signed modulo use truncated division
(where -13 % 3 == -1) as implemented in C, Go, etc.:
(where -13 % 3 == -1) as implemented in C, Go, etc.::
a % n = a - n * trunc(a / n)
The ``MOVSX`` instruction does a move operation with sign extension.
``{MOVSX, X, ALU}`` :term:`sign extends<Sign Extend>` 8-bit and 16-bit operands into 32
bit operands, and zeroes the remaining upper 32 bits.
``{MOVSX, X, ALU}`` :term:`sign extends<Sign Extend>` 8-bit and 16-bit operands into
32-bit operands, and zeroes the remaining upper 32 bits.
``{MOVSX, X, ALU64}`` :term:`sign extends<Sign Extend>` 8-bit, 16-bit, and 32-bit
operands into 64 bit operands. Unlike other arithmetic instructions,
operands into 64-bit operands. Unlike other arithmetic instructions,
``MOVSX`` is only defined for register source operands (``X``).
The ``NEG`` instruction is only defined when the source bit is clear
@ -411,19 +420,19 @@ conformance group.
Examples:
``{END, TO_LE, ALU}`` with imm = 16/32/64 means::
``{END, TO_LE, ALU}`` with 'imm' = 16/32/64 means::
dst = htole16(dst)
dst = htole32(dst)
dst = htole64(dst)
``{END, TO_BE, ALU}`` with imm = 16/32/64 means::
``{END, TO_BE, ALU}`` with 'imm' = 16/32/64 means::
dst = htobe16(dst)
dst = htobe32(dst)
dst = htobe64(dst)
``{END, TO_LE, ALU64}`` with imm = 16/32/64 means::
``{END, TO_LE, ALU64}`` with 'imm' = 16/32/64 means::
dst = bswap16(dst)
dst = bswap32(dst)
@ -438,27 +447,33 @@ otherwise identical operations, and indicates the base64 conformance
group unless otherwise specified.
The 'code' field encodes the operation as below:
======== ===== ======= =============================== ===================================================
code value src_reg description notes
======== ===== ======= =============================== ===================================================
JA 0x0 0x0 PC += offset {JA, K, JMP} only
JA 0x0 0x0 PC += imm {JA, K, JMP32} only
======== ===== ======= ================================= ===================================================
code value src_reg description notes
======== ===== ======= ================================= ===================================================
JA 0x0 0x0 PC += offset {JA, K, JMP} only
JA 0x0 0x0 PC += imm {JA, K, JMP32} only
JEQ 0x1 any PC += offset if dst == src
JGT 0x2 any PC += offset if dst > src unsigned
JGE 0x3 any PC += offset if dst >= src unsigned
JGT 0x2 any PC += offset if dst > src unsigned
JGE 0x3 any PC += offset if dst >= src unsigned
JSET 0x4 any PC += offset if dst & src
JNE 0x5 any PC += offset if dst != src
JSGT 0x6 any PC += offset if dst > src signed
JSGE 0x7 any PC += offset if dst >= src signed
CALL 0x8 0x0 call helper function by address {CALL, K, JMP} only, see `Helper functions`_
CALL 0x8 0x1 call PC += imm {CALL, K, JMP} only, see `Program-local functions`_
CALL 0x8 0x2 call helper function by BTF ID {CALL, K, JMP} only, see `Helper functions`_
EXIT 0x9 0x0 return {CALL, K, JMP} only
JLT 0xa any PC += offset if dst < src unsigned
JLE 0xb any PC += offset if dst <= src unsigned
JSLT 0xc any PC += offset if dst < src signed
JSLE 0xd any PC += offset if dst <= src signed
======== ===== ======= =============================== ===================================================
JSGT 0x6 any PC += offset if dst > src signed
JSGE 0x7 any PC += offset if dst >= src signed
CALL 0x8 0x0 call helper function by static ID {CALL, K, JMP} only, see `Helper functions`_
CALL 0x8 0x1 call PC += imm {CALL, K, JMP} only, see `Program-local functions`_
CALL 0x8 0x2 call helper function by BTF ID {CALL, K, JMP} only, see `Helper functions`_
EXIT 0x9 0x0 return {CALL, K, JMP} only
JLT 0xa any PC += offset if dst < src unsigned
JLE 0xb any PC += offset if dst <= src unsigned
JSLT 0xc any PC += offset if dst < src signed
JSLE 0xd any PC += offset if dst <= src signed
======== ===== ======= ================================= ===================================================
where 'PC' denotes the program counter, and the offset to increment by
is in units of 64-bit instructions relative to the instruction following
the jump instruction. Thus 'PC += 1' skips execution of the next
instruction if it's a basic instruction or results in undefined behavior
if the next instruction is a 128-bit wide instruction.
The BPF program needs to store the return value into register R0 before doing an
``EXIT``.
@ -475,7 +490,7 @@ where 's>=' indicates a signed '>=' comparison.
gotol +imm
where 'imm' means the branch offset comes from insn 'imm' field.
where 'imm' means the branch offset comes from the 'imm' field.
Note that there are two flavors of ``JA`` instructions. The
``JMP`` class permits a 16-bit jump offset specified by the 'offset'
@ -493,26 +508,26 @@ Helper functions
Helper functions are a concept whereby BPF programs can call into a
set of function calls exposed by the underlying platform.
Historically, each helper function was identified by an address
encoded in the imm field. The available helper functions may differ
for each program type, but address values are unique across all program types.
Historically, each helper function was identified by a static ID
encoded in the 'imm' field. The available helper functions may differ
for each program type, but static IDs are unique across all program types.
Platforms that support the BPF Type Format (BTF) support identifying
a helper function by a BTF ID encoded in the imm field, where the BTF ID
a helper function by a BTF ID encoded in the 'imm' field, where the BTF ID
identifies the helper name and type.
Program-local functions
~~~~~~~~~~~~~~~~~~~~~~~
Program-local functions are functions exposed by the same BPF program as the
caller, and are referenced by offset from the call instruction, similar to
``JA``. The offset is encoded in the imm field of the call instruction.
A ``EXIT`` within the program-local function will return to the caller.
``JA``. The offset is encoded in the 'imm' field of the call instruction.
An ``EXIT`` within the program-local function will return to the caller.
Load and store instructions
===========================
For load and store instructions (``LD``, ``LDX``, ``ST``, and ``STX``), the
8-bit 'opcode' field is divided as::
8-bit 'opcode' field is divided as follows::
+-+-+-+-+-+-+-+-+
|mode |sz |class|
@ -580,7 +595,7 @@ instructions that transfer data between a register and memory.
dst = *(signed size *) (src + offset)
Where size is one of: ``B``, ``H``, or ``W``, and
Where '<size>' is one of: ``B``, ``H``, or ``W``, and
'signed size' is one of: s8, s16, or s32.
Atomic operations
@ -662,11 +677,11 @@ src_reg pseudocode imm type dst type
======= ========================================= =========== ==============
0x0 dst = (next_imm << 32) | imm integer integer
0x1 dst = map_by_fd(imm) map fd map
0x2 dst = map_val(map_by_fd(imm)) + next_imm map fd data pointer
0x3 dst = var_addr(imm) variable id data pointer
0x4 dst = code_addr(imm) integer code pointer
0x2 dst = map_val(map_by_fd(imm)) + next_imm map fd data address
0x3 dst = var_addr(imm) variable id data address
0x4 dst = code_addr(imm) integer code address
0x5 dst = map_by_idx(imm) map index map
0x6 dst = map_val(map_by_idx(imm)) + next_imm map index data pointer
0x6 dst = map_val(map_by_idx(imm)) + next_imm map index data address
======= ========================================= =========== ==============
where

2
Documentation/conf.py
View File

@ -75,6 +75,8 @@ if major >= 3:
"__rcu",
"__user",
"__force",
"__counted_by_le",
"__counted_by_be",
# include/linux/compiler_attributes.h:
"__alias",

56
Documentation/devicetree/bindings/net/airoha,en8811h.yaml Normal file
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@ -0,0 +1,56 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/airoha,en8811h.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Airoha EN8811H PHY
maintainers:
- Eric Woudstra <ericwouds@gmail.com>
description:
The Airoha EN8811H PHY has the ability to reverse polarity
on the lines to and/or from the MAC. It is reversed by
the booleans in the devicetree node of the phy.
allOf:
- $ref: ethernet-phy.yaml#
properties:
compatible:
enum:
- ethernet-phy-id03a2.a411
reg:
maxItems: 1
airoha,pnswap-rx:
type: boolean
description:
Reverse rx polarity of the SERDES. This is the receiving
side of the lines from the MAC towards the EN881H.
airoha,pnswap-tx:
type: boolean
description:
Reverse tx polarity of SERDES. This is the transmitting
side of the lines from EN8811H towards the MAC.
required:
- reg
unevaluatedProperties: false
examples:
- |
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethernet-phy@1 {
compatible = "ethernet-phy-id03a2.a411";
reg = <1>;
airoha,pnswap-rx;
};
};

4
Documentation/devicetree/bindings/net/nxp,dwmac-imx.yaml
View File

@ -66,6 +66,10 @@ properties:
Should be phandle/offset pair. The phandle to the syscon node which
encompases the GPR register, and the offset of the GPR register.
nvmem-cells: true
nvmem-cell-names: true
snps,rmii_refclk_ext:
$ref: /schemas/types.yaml#/definitions/flag
description:

169
Documentation/devicetree/bindings/net/pse-pd/microchip,pd692x0.yaml Normal file
View File

@ -0,0 +1,169 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/pse-pd/microchip,pd692x0.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Microchip PD692x0 Power Sourcing Equipment controller
maintainers:
- Kory Maincent <kory.maincent@bootlin.com>
allOf:
- $ref: pse-controller.yaml#
properties:
compatible:
enum:
- microchip,pd69200
- microchip,pd69210
- microchip,pd69220
reg:
maxItems: 1
managers:
type: object
description:
List of the PD69208T4/PD69204T4/PD69208M PSE managers. Each manager
have 4 or 8 physical ports according to the chip version. No need to
specify the SPI chip select as it is automatically detected by the
PD692x0 PSE controller. The PSE managers have to be described from
the lowest chip select to the greatest one, which is the detection
behavior of the PD692x0 PSE controller. The PD692x0 support up to
12 PSE managers which can expose up to 96 physical ports. All
physical ports available on a manager have to be described in the
incremental order even if they are not used.
properties:
"#address-cells":
const: 1
"#size-cells":
const: 0
required:
- "#address-cells"
- "#size-cells"
patternProperties:
"^manager@0[0-9a-b]$":
type: object
description:
PD69208T4/PD69204T4/PD69208M PSE manager exposing 4 or 8 physical
ports.
properties:
reg:
description:
Incremental index of the PSE manager starting from 0, ranging
from lowest to highest chip select, up to 11.
maxItems: 1
"#address-cells":
const: 1
"#size-cells":
const: 0
patternProperties:
'^port@[0-7]$':
type: object
required:
- reg
additionalProperties: false
required:
- reg
- "#address-cells"
- "#size-cells"
required:
- compatible
- reg
- pse-pis
unevaluatedProperties: false
examples:
- |
i2c {
#address-cells = <1>;
#size-cells = <0>;
ethernet-pse@3c {
compatible = "microchip,pd69200";
reg = <0x3c>;
managers {
#address-cells = <1>;
#size-cells = <0>;
manager@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
phys0: port@0 {
reg = <0>;
};
phys1: port@1 {
reg = <1>;
};
phys2: port@2 {
reg = <2>;
};
phys3: port@3 {
reg = <3>;
};
};
manager@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
phys4: port@0 {
reg = <0>;
};
phys5: port@1 {
reg = <1>;
};
phys6: port@2 {
reg = <2>;
};
phys7: port@3 {
reg = <3>;
};
};
};
pse-pis {
#address-cells = <1>;
#size-cells = <0>;
pse_pi0: pse-pi@0 {
reg = <0>;
#pse-cells = <0>;
pairset-names = "alternative-a", "alternative-b";
pairsets = <&phys0>, <&phys1>;
polarity-supported = "MDI", "S";
vpwr-supply = <&vpwr1>;
};
pse_pi1: pse-pi@1 {
reg = <1>;
#pse-cells = <0>;
pairset-names = "alternative-a";
pairsets = <&phys2>;
polarity-supported = "MDI";
vpwr-supply = <&vpwr2>;
};
};
};
};

101
Documentation/devicetree/bindings/net/pse-pd/pse-controller.yaml
View File

@ -13,6 +13,7 @@ description: Binding for the Power Sourcing Equipment (PSE) as defined in the
maintainers:
- Oleksij Rempel <o.rempel@pengutronix.de>
- Kory Maincent <kory.maincent@bootlin.com>
properties:
$nodename:
@ -22,11 +23,105 @@ properties:
description:
Used to uniquely identify a PSE instance within an IC. Will be
0 on PSE nodes with only a single output and at least 1 on nodes
controlling several outputs.
controlling several outputs which are not described in the pse-pis
subnode. This property is deprecated, please use pse-pis instead.
enum: [0, 1]
required:
- "#pse-cells"
pse-pis:
type: object
description:
Overview of the PSE PIs provided by the controller.
properties:
"#address-cells":
const: 1
"#size-cells":
const: 0
required:
- "#address-cells"
- "#size-cells"
patternProperties:
"^pse-pi@[0-9a-f]+$":
type: object
description:
PSE PI for power delivery via pairsets, compliant with IEEE
802.3-2022, Section 145.2.4. Each pairset comprises a positive and
a negative VPSE pair, adhering to the pinout configurations
detailed in the standard.
See Documentation/networking/pse-pd/pse-pi.rst for details.
properties:
reg:
description:
Address describing the PSE PI index.
maxItems: 1
"#pse-cells":
const: 0
pairset-names:
$ref: /schemas/types.yaml#/definitions/string-array
description:
Names of the pairsets as per IEEE 802.3-2022, Section 145.2.4.
Each name should correspond to a phandle in the 'pairset'
property pointing to the power supply for that pairset.
minItems: 1
maxItems: 2
items:
enum:
- alternative-a
- alternative-b
pairsets:
$ref: /schemas/types.yaml#/definitions/phandle-array
description:
List of phandles, each pointing to the power supply for the
corresponding pairset named in 'pairset-names'. This property
aligns with IEEE 802.3-2022, Section 33.2.3 and 145.2.4.
PSE Pinout Alternatives (as per IEEE 802.3-2022 Table 145\u20133)
|-----------|---------------|---------------|---------------|---------------|
| Conductor | Alternative A | Alternative A | Alternative B | Alternative B |
| | (MDI-X) | (MDI) | (X) | (S) |
|-----------|---------------|---------------|---------------|---------------|
| 1 | Negative VPSE | Positive VPSE | - | - |
| 2 | Negative VPSE | Positive VPSE | - | - |
| 3 | Positive VPSE | Negative VPSE | - | - |
| 4 | - | - | Negative VPSE | Positive VPSE |
| 5 | - | - | Negative VPSE | Positive VPSE |
| 6 | Positive VPSE | Negative VPSE | - | - |
| 7 | - | - | Positive VPSE | Negative VPSE |
| 8 | - | - | Positive VPSE | Negative VPSE |
minItems: 1
maxItems: 2
polarity-supported:
$ref: /schemas/types.yaml#/definitions/string-array
description:
Polarity configuration supported by the PSE PI pairsets.
minItems: 1
maxItems: 4
items:
enum:
- MDI-X
- MDI
- X
- S
vpwr-supply:
description: Regulator power supply for the PSE PI.
required:
- reg
- "#pse-cells"
oneOf:
- required:
- "#pse-cells"
- required:
- pse-pis
additionalProperties: true

95
Documentation/devicetree/bindings/net/pse-pd/ti,tps23881.yaml Normal file
View File

@ -0,0 +1,95 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/pse-pd/ti,tps23881.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: TI TPS23881 Power Sourcing Equipment controller
maintainers:
- Kory Maincent <kory.maincent@bootlin.com>
allOf:
- $ref: pse-controller.yaml#
properties:
compatible:
enum:
- ti,tps23881
reg:
maxItems: 1
'#pse-cells':
const: 1
channels:
description: each set of 8 ports can be assigned to one physical
channels or two for PoE4. This parameter describes the configuration
of the ports conversion matrix that establishes relationship between
the logical ports and the physical channels.
type: object
patternProperties:
'^channel@[0-7]$':
type: object
required:
- reg
unevaluatedProperties: false
required:
- compatible
- reg
examples:
- |
i2c {
#address-cells = <1>;
#size-cells = <0>;
ethernet-pse@20 {
compatible = "ti,tps23881";
reg = <0x20>;
channels {
#address-cells = <1>;
#size-cells = <0>;
phys0: channel@0 {
reg = <0>;
};
phys1: channel@1 {
reg = <1>;
};
phys2: channel@2 {
reg = <2>;
};
};
pse-pis {
#address-cells = <1>;
#size-cells = <0>;
pse_pi0: pse-pi@0 {
reg = <0>;
#pse-cells = <0>;
pairset-names = "alternative-a", "alternative-b";
pairsets = <&phys0>, <&phys1>;
polarity-supported = "MDI", "S";
vpwr-supply = <&vpwr1>;
};
pse_pi1: pse-pi@1 {
reg = <1>;
#pse-cells = <0>;
pairset-names = "alternative-a";
pairsets = <&phys2>;
polarity-supported = "MDI";
vpwr-supply = <&vpwr2>;
};
};
};
};

2
Documentation/devicetree/bindings/net/qcom,ipq4019-mdio.yaml
View File

@ -20,6 +20,7 @@ properties:
- enum:
- qcom,ipq6018-mdio
- qcom,ipq8074-mdio
- qcom,ipq9574-mdio
- const: qcom,ipq4019-mdio
"#address-cells":
@ -76,6 +77,7 @@ allOf:
- qcom,ipq5018-mdio
- qcom,ipq6018-mdio
- qcom,ipq8074-mdio
- qcom,ipq9574-mdio
then:
required:
- clocks

12
Documentation/devicetree/bindings/net/renesas,etheravb.yaml
View File

@ -88,10 +88,16 @@ properties:
'#address-cells':
description: Number of address cells for the MDIO bus.
const: 1
deprecated: true
'#size-cells':
description: Number of size cells on the MDIO bus.
const: 0
deprecated: true
mdio:
$ref: /schemas/net/mdio.yaml#
unevaluatedProperties: false
renesas,no-ether-link:
type: boolean
@ -110,9 +116,13 @@ properties:
tx-internal-delay-ps:
enum: [0, 2000]
# In older bindings there where no mdio child-node to describe the MDIO bus
# and the PHY. To not fail older bindings accept any node with an address. New
# users should describe the PHY inside the mdio child-node.
patternProperties:
"@[0-9a-f]$":
type: object
deprecated: true
required:
- compatible
@ -123,8 +133,6 @@ required:
- resets
- phy-mode
- phy-handle
- '#address-cells'
- '#size-cells'
allOf:
- $ref: ethernet-controller.yaml#

33
Documentation/devicetree/bindings/net/renesas,ethertsn.yaml
View File

@ -71,16 +71,8 @@ properties:
enum: [0, 2000]
default: 0
'#address-cells':
const: 1
'#size-cells':
const: 0
patternProperties:
"^ethernet-phy@[0-9a-f]$":
type: object
$ref: ethernet-phy.yaml#
mdio:
$ref: /schemas/net/mdio.yaml#
unevaluatedProperties: false
required:
@ -94,8 +86,7 @@ required:
- resets
- phy-mode
- phy-handle
- '#address-cells'
- '#size-cells'
- mdio
additionalProperties: false
@ -122,14 +113,18 @@ examples:
tx-internal-delay-ps = <2000>;
phy-handle = <&phy3>;
#address-cells = <1>;
#size-cells = <0>;
mdio {
#address-cells = <1>;
#size-cells = <0>;
phy3: ethernet-phy@3 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0>;
interrupt-parent = <&gpio4>;
interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
reset-gpios = <&gpio1 23 GPIO_ACTIVE_LOW>;
reset-post-delay-us = <4000>;
phy3: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0>;
interrupt-parent = <&gpio4>;
interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
};
};
};

4
Documentation/devicetree/bindings/net/rockchip-dwmac.yaml
View File

@ -137,8 +137,6 @@ examples:
assigned-clock-parents = <&ext_gmac>;
rockchip,grf = <&grf>;
phy-mode = "rgmii";
phy-mode = "rgmii-id";
clock_in_out = "input";
tx_delay = <0x30>;
rx_delay = <0x10>;
};

20
Documentation/devicetree/bindings/net/snps,dwmac.yaml
View File

@ -242,7 +242,8 @@ properties:
type: boolean
description: Multicast & Broadcast Packets
snps,priority:
$ref: /schemas/types.yaml#/definitions/uint32
$ref: /schemas/types.yaml#/definitions/uint32-array
maxItems: 1
description: Bitmask of the tagged frames priorities assigned to the queue
allOf:
- if:
@ -327,9 +328,6 @@ properties:
snps,tx-sched-dwrr:
type: boolean
description: Deficit Weighted Round Robin
snps,tx-sched-sp:
type: boolean
description: Strict priority
allOf:
- if:
required:
@ -338,7 +336,6 @@ properties:
properties:
snps,tx-sched-wfq: false
snps,tx-sched-dwrr: false
snps,tx-sched-sp: false
- if:
required:
- snps,tx-sched-wfq
@ -346,7 +343,6 @@ properties:
properties:
snps,tx-sched-wrr: false
snps,tx-sched-dwrr: false
snps,tx-sched-sp: false
- if:
required:
- snps,tx-sched-dwrr
@ -354,15 +350,6 @@ properties:
properties:
snps,tx-sched-wrr: false
snps,tx-sched-wfq: false
snps,tx-sched-sp: false
- if:
required:
- snps,tx-sched-sp
then:
properties:
snps,tx-sched-wrr: false
snps,tx-sched-wfq: false
snps,tx-sched-dwrr: false
patternProperties:
"^queue[0-9]$":
description: Each subnode represents a queue.
@ -393,7 +380,8 @@ properties:
$ref: /schemas/types.yaml#/definitions/uint32
description: max read outstanding req. limit
snps,priority:
$ref: /schemas/types.yaml#/definitions/uint32
$ref: /schemas/types.yaml#/definitions/uint32-array
maxItems: 1
description:
Bitmask of the tagged frames priorities assigned to the queue.
When a PFC frame is received with priorities matching the bitmask,

26
Documentation/devicetree/bindings/net/starfive,jh7110-dwmac.yaml
View File

@ -30,6 +30,10 @@ properties:
- items:
- const: starfive,jh7110-dwmac
- const: snps,dwmac-5.20
- items:
- const: starfive,jh8100-dwmac
- const: starfive,jh7110-dwmac
- const: snps,dwmac-5.20
reg:
maxItems: 1
@ -116,11 +120,25 @@ allOf:
minItems: 3
maxItems: 3
resets:
minItems: 2
if:
properties:
compatible:
contains:
const: starfive,jh8100-dwmac
then:
properties:
resets:
maxItems: 1
reset-names:
minItems: 2
reset-names:
const: stmmaceth
else:
properties:
resets:
minItems: 2
reset-names:
minItems: 2
unevaluatedProperties: false

7
Documentation/devicetree/bindings/net/stm32-dwmac.yaml
View File

@ -82,6 +82,13 @@ properties:
Should be phandle/offset pair. The phandle to the syscon node which
encompases the glue register, and the offset of the control register
st,ext-phyclk:
description:
set this property in RMII mode when you have PHY without crystal 50MHz and want to
select RCC clock instead of ETH_REF_CLK. OR in RGMII mode when you want to select
RCC clock instead of ETH_CLK125.
type: boolean
st,eth-clk-sel:
description:
set this property in RGMII PHY when you want to select RCC clock instead of ETH_CLK125.

35
Documentation/devicetree/bindings/net/ti,icssg-prueth.yaml
View File

@ -13,14 +13,12 @@ description:
Ethernet based on the Programmable Real-Time Unit and Industrial
Communication Subsystem.
allOf:
- $ref: /schemas/remoteproc/ti,pru-consumer.yaml#
properties:
compatible:
enum:
- ti,am642-icssg-prueth # for AM64x SoC family
- ti,am654-icssg-prueth # for AM65x SoC family
- ti,am642-icssg-prueth # for AM64x SoC family
- ti,am654-icssg-prueth # for AM65x SoC family
- ti,am654-sr1-icssg-prueth # for AM65x SoC family, SR1.0
sram:
$ref: /schemas/types.yaml#/definitions/phandle
@ -28,9 +26,11 @@ properties:
phandle to MSMC SRAM node
dmas:
maxItems: 10
minItems: 10
maxItems: 12
dma-names:
minItems: 10
items:
- const: tx0-0
- const: tx0-1
@ -42,6 +42,8 @@ properties:
- const: tx1-3
- const: rx0
- const: rx1
- const: rxmgm0
- const: rxmgm1
ti,mii-g-rt:
$ref: /schemas/types.yaml#/definitions/phandle
@ -132,6 +134,27 @@ required:
- interrupts
- interrupt-names
allOf:
- $ref: /schemas/remoteproc/ti,pru-consumer.yaml#
- if:
properties:
compatible:
contains:
const: ti,am654-sr1-icssg-prueth
then:
properties:
dmas:
minItems: 12
dma-names:
minItems: 12
else:
properties:
dmas:
maxItems: 10
dma-names:
maxItems: 10
unevaluatedProperties: false
examples:

1
Documentation/devicetree/bindings/net/wireless/brcm,bcm4329-fmac.yaml
View File

@ -44,6 +44,7 @@ properties:
- brcm,bcm4366-fmac
- cypress,cyw4373-fmac
- cypress,cyw43012-fmac
- infineon,cyw43439-fmac
- const: brcm,bcm4329-fmac
- enum:
- brcm,bcm4329-fmac

6
Documentation/devicetree/bindings/net/wireless/qcom,ath10k.yaml
View File

@ -73,6 +73,12 @@ properties:
- sky85703-11
- sky85803
firmware-name:
maxItems: 1
description:
If present, a board or platform specific string used to lookup firmware
files for the device.
wifi-firmware:
type: object
additionalProperties: false

3
Documentation/devicetree/bindings/net/wireless/qcom,ath11k.yaml
View File

@ -59,6 +59,8 @@ properties:
minItems: 1
maxItems: 2
ieee80211-freq-limit: true
wifi-firmware:
type: object
description: |
@ -88,6 +90,7 @@ required:
additionalProperties: false
allOf:
- $ref: ieee80211.yaml#
- if:
properties:
compatible:

2
Documentation/mm/page_frags.rst
View File

@ -25,7 +25,7 @@ to be disabled when executing the fragment allocation.
The network stack uses two separate caches per CPU to handle fragment
allocation. The netdev_alloc_cache is used by callers making use of the
netdev_alloc_frag and __netdev_alloc_skb calls. The napi_alloc_cache is
used by callers of the __napi_alloc_frag and __napi_alloc_skb calls. The
used by callers of the __napi_alloc_frag and napi_alloc_skb calls. The
main difference between these two calls is the context in which they may be
called. The "netdev" prefixed functions are usable in any context as these
functions will disable interrupts, while the "napi" prefixed functions are

2
Documentation/netlink/genetlink-c.yaml
View File

@ -158,7 +158,7 @@ properties:
type: &attr-type
enum: [ unused, pad, flag, binary,
uint, sint, u8, u16, u32, u64, s32, s64,
string, nest, array-nest, nest-type-value ]
string, nest, indexed-array, nest-type-value ]
doc:
description: Documentation of the attribute.
type: string

2
Documentation/netlink/genetlink-legacy.yaml
View File

@ -201,7 +201,7 @@ properties:
description: The netlink attribute type
enum: [ unused, pad, flag, binary, bitfield32,
uint, sint, u8, u16, u32, u64, s32, s64,
string, nest, array-nest, nest-type-value ]
string, nest, indexed-array, nest-type-value ]
doc:
description: Documentation of the attribute.
type: string

2
Documentation/netlink/genetlink.yaml
View File

@ -124,7 +124,7 @@ properties:
type: &attr-type
enum: [ unused, pad, flag, binary,
uint, sint, u8, u16, u32, u64, s32, s64,
string, nest, array-nest, nest-type-value ]
string, nest, indexed-array, nest-type-value ]
doc:
description: Documentation of the attribute.
type: string

2
Documentation/netlink/netlink-raw.yaml
View File

@ -222,7 +222,7 @@ properties:
description: The netlink attribute type
enum: [ unused, pad, flag, binary, bitfield32,
u8, u16, u32, u64, s8, s16, s32, s64,
string, nest, array-nest, nest-type-value,
string, nest, indexed-array, nest-type-value,
sub-message ]
doc:
description: Documentation of the attribute.

55
Documentation/netlink/specs/ethtool.yaml
View File

@ -16,6 +16,10 @@ definitions:
name: stringset
type: enum
entries: []
-
name: header-flags
type: flags
entries: [ compact-bitsets, omit-reply, stats ]
attribute-sets:
-
@ -30,6 +34,7 @@ attribute-sets:
-
name: flags
type: u32
enum: header-flags
-
name: bitset-bit
@ -559,6 +564,18 @@ attribute-sets:
-
name: tx-lpi-timer
type: u32
-
name: ts-stat
attributes:
-
name: tx-pkts
type: uint
-
name: tx-lost
type: uint
-
name: tx-err
type: uint
-
name: tsinfo
attributes:
@ -581,6 +598,10 @@ attribute-sets:
-
name: phc-index
type: u32
-
name: stats
type: nest
nested-attributes: ts-stat
-
name: cable-result
attributes:
@ -878,17 +899,29 @@ attribute-sets:
type: nest
nested-attributes: header
-
name: admin-state
name: podl-pse-admin-state
type: u32
name-prefix: ethtool-a-podl-pse-
name-prefix: ethtool-a-
-
name: admin-control
name: podl-pse-admin-control
type: u32
name-prefix: ethtool-a-podl-pse-
name-prefix: ethtool-a-
-
name: pw-d-status
name: podl-pse-pw-d-status
type: u32
name-prefix: ethtool-a-podl-pse-
name-prefix: ethtool-a-
-
name: c33-pse-admin-state
type: u32
name-prefix: ethtool-a-
-
name: c33-pse-admin-control
type: u32
name-prefix: ethtool-a-
-
name: c33-pse-pw-d-status
type: u32
name-prefix: ethtool-a-
-
name: rss
attributes:
@ -1388,6 +1421,7 @@ operations:
- tx-types
- rx-filters
- phc-index
- stats
dump: *tsinfo-get-op
-
name: cable-test-act
@ -1571,9 +1605,12 @@ operations:
reply:
attributes: &pse
- header
- admin-state
- admin-control
- pw-d-status
- podl-pse-admin-state
- podl-pse-admin-control
- podl-pse-pw-d-status
- c33-pse-admin-state
- c33-pse-admin-control
- c33-pse-pw-d-status
dump: *pse-get-op
-
name: pse-set

105
Documentation/netlink/specs/netdev.yaml
View File

@ -335,6 +335,110 @@ attribute-sets:
Allocation failure may, or may not result in a packet drop, depending
on driver implementation and whether system recovers quickly.
type: uint
-
name: rx-hw-drops
doc: |
Number of all packets which entered the device, but never left it,
including but not limited to: packets dropped due to lack of buffer
space, processing errors, explicit or implicit policies and packet
filters.
type: uint
-
name: rx-hw-drop-overruns
doc: |
Number of packets dropped due to transient lack of resources, such as
buffer space, host descriptors etc.
type: uint
-
name: rx-csum-unnecessary
doc: Number of packets that were marked as CHECKSUM_UNNECESSARY.
type: uint
-
name: rx-csum-none
doc: Number of packets that were not checksummed by device.
type: uint
-
name: rx-csum-bad
doc: |
Number of packets with bad checksum. The packets are not discarded,
but still delivered to the stack.
type: uint
-
name: rx-hw-gro-packets
doc: |
Number of packets that were coalesced from smaller packets by the device.
Counts only packets coalesced with the HW-GRO netdevice feature,
LRO-coalesced packets are not counted.
type: uint
-
name: rx-hw-gro-bytes
doc: See `rx-hw-gro-packets`.
type: uint
-
name: rx-hw-gro-wire-packets
doc: |
Number of packets that were coalesced to bigger packetss with the HW-GRO
netdevice feature. LRO-coalesced packets are not counted.
type: uint
-
name: rx-hw-gro-wire-bytes
doc: See `rx-hw-gro-wire-packets`.
type: uint
-
name: rx-hw-drop-ratelimits
doc: |
Number of the packets dropped by the device due to the received
packets bitrate exceeding the device rate limit.
type: uint
-
name: tx-hw-drops
doc: |
Number of packets that arrived at the device but never left it,
encompassing packets dropped for reasons such as processing errors, as
well as those affected by explicitly defined policies and packet
filtering criteria.
type: uint
-
name: tx-hw-drop-errors
doc: Number of packets dropped because they were invalid or malformed.
type: uint
-
name: tx-csum-none
doc: |
Number of packets that did not require the device to calculate the
checksum.
type: uint
-
name: tx-needs-csum
doc: |
Number of packets that required the device to calculate the checksum.
type: uint
-
name: tx-hw-gso-packets
doc: |
Number of packets that necessitated segmentation into smaller packets
by the device.
type: uint
-
name: tx-hw-gso-bytes
doc: See `tx-hw-gso-packets`.
type: uint
-
name: tx-hw-gso-wire-packets
doc: |
Number of wire-sized packets generated by processing
`tx-hw-gso-packets`
type: uint
-
name: tx-hw-gso-wire-bytes
doc: See `tx-hw-gso-wire-packets`.
type: uint
-
name: tx-hw-drop-ratelimits
doc: |
Number of the packets dropped by the device due to the transmit
packets bitrate exceeding the device rate limit.
type: uint
operations:
list:
@ -486,6 +590,7 @@ operations:
dump:
request:
attributes:
- ifindex
- scope
reply:
attributes:

1264
Documentation/netlink/specs/nftables.yaml Normal file
View File

File diff suppressed because it is too large Load Diff

6
Documentation/netlink/specs/nlctrl.yaml
View File

@ -65,11 +65,13 @@ attribute-sets:
type: u32
-
name: ops
type: array-nest
type: indexed-array
sub-type: nest
nested-attributes: op-attrs
-
name: mcast-groups
type: array-nest
type: indexed-array
sub-type: nest
nested-attributes: mcast-group-attrs
-
name: policy

483
Documentation/netlink/specs/rt_link.yaml
View File

@ -50,7 +50,16 @@ definitions:
name: dormant
-
name: echo
-
name: vlan-protocols
type: enum
entries:
-
name: 8021q
value: 33024
-
name: 8021ad
value: 34984
-
name: rtgenmsg
type: struct
@ -729,7 +738,171 @@ definitions:
-
name: filter-mask
type: u32
-
name: ifla-vlan-flags
type: struct
members:
-
name: flags
type: u32
enum: vlan-flags
enum-as-flags: true
-
name: mask
type: u32
display-hint: hex
-
name: vlan-flags
type: flags
entries:
- reorder-hdr
- gvrp
- loose-binding
- mvrp
- bridge-binding
-
name: ifla-vlan-qos-mapping
type: struct
members:
-
name: from
type: u32
-
name: to
type: u32
-
name: ifla-vf-mac
type: struct
members:
-
name: vf
type: u32
-
name: mac
type: binary
len: 32
-
name: ifla-vf-vlan
type: struct
members:
-
name: vf
type: u32
-
name: vlan
type: u32
-
name: qos
type: u32
-
name: ifla-vf-tx-rate
type: struct
members:
-
name: vf
type: u32
-
name: rate
type: u32
-
name: ifla-vf-spoofchk
type: struct
members:
-
name: vf
type: u32
-
name: setting
type: u32
-
name: ifla-vf-link-state
type: struct
members:
-
name: vf
type: u32
-
name: link-state
type: u32
enum: ifla-vf-link-state-enum
-
name: ifla-vf-link-state-enum
type: enum
entries:
- auto
- enable
- disable
-
name: ifla-vf-rate
type: struct
members:
-
name: vf
type: u32
-
name: min-tx-rate
type: u32
-
name: max-tx-rate
type: u32
-
name: ifla-vf-rss-query-en
type: struct
members:
-
name: vf
type: u32
-
name: setting
type: u32
-
name: ifla-vf-trust
type: struct
members:
-
name: vf
type: u32
-
name: setting
type: u32
-
name: ifla-vf-guid
type: struct
members:
-
name: vf
type: u32
-
name: guid
type: u64
-
name: ifla-vf-vlan-info
type: struct
members:
-
name: vf
type: u32
-
name: vlan
type: u32
-
name: qos
type: u32
-
name: vlan-proto
type: u32
-
name: rtext-filter
type: flags
entries:
- vf
- brvlan
- brvlan-compressed
- skip-stats
- mrp
- cfm-config
- cfm-status
- mst
attribute-sets:
-
@ -807,7 +980,7 @@ attribute-sets:
-
name: vfinfo-list
type: nest
nested-attributes: vfinfo-attrs
nested-attributes: vfinfo-list-attrs
-
name: stats64
type: binary
@ -833,6 +1006,8 @@ attribute-sets:
-
name: ext-mask
type: u32
enum: rtext-filter
enum-as-flags: true
-
name: promiscuity
type: u32
@ -964,9 +1139,107 @@ attribute-sets:
type: nest
value: 45
nested-attributes: mctp-attrs
-
name: vfinfo-list-attrs
attributes:
-
name: info
type: nest
nested-attributes: vfinfo-attrs
multi-attr: true
-
name: vfinfo-attrs
attributes: []
attributes:
-
name: mac
type: binary
struct: ifla-vf-mac
-
name: vlan
type: binary
struct: ifla-vf-vlan
-
name: tx-rate
type: binary
struct: ifla-vf-tx-rate
-
name: spoofchk
type: binary
struct: ifla-vf-spoofchk
-
name: link-state
type: binary
struct: ifla-vf-link-state
-
name: rate
type: binary
struct: ifla-vf-rate
-
name: rss-query-en
type: binary
struct: ifla-vf-rss-query-en
-
name: stats
type: nest
nested-attributes: vf-stats-attrs
-
name: trust
type: binary
struct: ifla-vf-trust
-
name: ib-node-guid
type: binary
struct: ifla-vf-guid
-
name: ib-port-guid
type: binary
struct: ifla-vf-guid
-
name: vlan-list
type: nest
nested-attributes: vf-vlan-attrs
-
name: broadcast
type: binary
-
name: vf-stats-attrs
attributes:
-
name: rx-packets
type: u64
value: 0
-
name: tx-packets
type: u64
-
name: rx-bytes
type: u64
-
name: tx-bytes
type: u64
-
name: broadcast
type: u64
-
name: multicast
type: u64
-
name: pad
type: pad
-
name: rx-dropped
type: u64
-
name: tx-dropped
type: u64
-
name: vf-vlan-attrs
attributes:
-
name: info
type: binary
struct: ifla-vf-vlan-info
multi-attr: true
-
name: vf-ports-attrs
attributes: []
@ -995,6 +1268,165 @@ attribute-sets:
type: sub-message
sub-message: linkinfo-member-data-msg
selector: slave-kind
-
name: linkinfo-bond-attrs
name-prefix: ifla-bond-
attributes:
-
name: mode
type: u8
-
name: active-slave
type: u32
-
name: miimon
type: u32
-
name: updelay
type: u32
-
name: downdelay
type: u32
-
name: use-carrier
type: u8
-
name: arp-interval
type: u32
-
name: arp-ip-target
type: indexed-array
sub-type: u32
byte-order: big-endian
display-hint: ipv4
-
name: arp-validate
type: u32
-
name: arp-all-targets
type: u32
-
name: primary
type: u32
-
name: primary-reselect
type: u8
-
name: fail-over-mac
type: u8
-
name: xmit-hash-policy
type: u8
-
name: resend-igmp
type: u32
-
name: num-peer-notif
type: u8
-
name: all-slaves-active
type: u8
-
name: min-links
type: u32
-
name: lp-interval
type: u32
-
name: packets-per-slave
type: u32
-
name: ad-lacp-rate
type: u8
-
name: ad-select
type: u8
-
name: ad-info
type: nest
nested-attributes: bond-ad-info-attrs
-
name: ad-actor-sys-prio
type: u16
-
name: ad-user-port-key
type: u16
-
name: ad-actor-system
type: binary
display-hint: mac
-
name: tlb-dynamic-lb
type: u8
-
name: peer-notif-delay
type: u32
-
name: ad-lacp-active
type: u8
-
name: missed-max
type: u8
-
name: ns-ip6-target
type: indexed-array
sub-type: binary
display-hint: ipv6
-
name: coupled-control
type: u8
-
name: bond-ad-info-attrs
name-prefix: ifla-bond-ad-info-
attributes:
-
name: aggregator
type: u16
-
name: num-ports
type: u16
-
name: actor-key
type: u16
-
name: partner-key
type: u16
-
name: partner-mac
type: binary
display-hint: mac
-
name: bond-slave-attrs
name-prefix: ifla-bond-slave-
attributes:
-
name: state
type: u8
-
name: mii-status
type: u8
-
name: link-failure-count
type: u32
-
name: perm-hwaddr
type: binary
display-hint: mac
-
name: queue-id
type: u16
-
name: ad-aggregator-id
type: u16
-
name: ad-actor-oper-port-state
type: u8
-
name: ad-partner-oper-port-state
type: u16
-
name: prio
type: u32
-
name: linkinfo-bridge-attrs
name-prefix: ifla-br-
@ -1513,6 +1945,39 @@ attribute-sets:
-
name: num-disabled-queues
type: u32
-
name: linkinfo-vlan-attrs
name-prefix: ifla-vlan-
attributes:
-
name: id
type: u16
-
name: flag
type: binary
struct: ifla-vlan-flags
-
name: egress-qos
type: nest
nested-attributes: ifla-vlan-qos
-
name: ingress-qos
type: nest
nested-attributes: ifla-vlan-qos
-
name: protocol
type: u16
enum: vlan-protocols
byte-order: big-endian
-
name: ifla-vlan-qos
name-prefix: ifla-vlan-qos
attributes:
-
name: mapping
type: binary
multi-attr: true
struct: ifla-vlan-qos-mapping
-
name: linkinfo-vrf-attrs
name-prefix: ifla-vrf-
@ -1623,7 +2088,8 @@ attribute-sets:
type: binary
-
name: hw-s-info
type: array-nest
type: indexed-array
sub-type: nest
nested-attributes: hw-s-info-one
-
name: l3-stats
@ -1648,6 +2114,9 @@ sub-messages:
-
name: linkinfo-data-msg
formats:
-
value: bond
attribute-set: linkinfo-bond-attrs
-
value: bridge
attribute-set: linkinfo-bridge-attrs
@ -1672,6 +2141,9 @@ sub-messages:
-
value: tun
attribute-set: linkinfo-tun-attrs
-
value: vlan
attribute-set: linkinfo-vlan-attrs
-
value: vrf
attribute-set: linkinfo-vrf-attrs
@ -1683,6 +2155,7 @@ sub-messages:
attribute-set: linkinfo-brport-attrs
-
value: bond
attribute-set: bond-slave-attrs
operations:
enum-model: directional

72
Documentation/netlink/specs/tc.yaml
View File

@ -1099,6 +1099,19 @@ definitions:
-
name: offmask
type: s32
-
name: tc-u32-mark
type: struct
members:
-
name: val
type: u32
-
name: mask
type: u32
-
name: success
type: u32
-
name: tc-u32-sel
type: struct
@ -1774,6 +1787,44 @@ attribute-sets:
-
name: key-ex
type: binary
-
name: tc-act-police-attrs
attributes:
-
name: tbf
type: binary
struct: tc-police
-
name: rate
type: binary # TODO
-
name: peakrate
type: binary # TODO
-
name: avrate
type: u32
-
name: result
type: u32
-
name: tm
type: binary
struct: tcf-t
-
name: pad
type: pad
-
name: rate64
type: u64
-
name: peakrate64
type: u64
-
name: pktrate64
type: u64
-
name: pktburst64
type: u64
-
name: tc-act-simple-attrs
attributes:
@ -1937,7 +1988,8 @@ attribute-sets:
nested-attributes: tc-ematch-attrs
-
name: act
type: array-nest
type: indexed-array
sub-type: nest
nested-attributes: tc-act-attrs
-
name: police
@ -2077,7 +2129,8 @@ attribute-sets:
type: u32
-
name: tin-stats
type: array-nest
type: indexed-array
sub-type: nest
nested-attributes: tc-cake-tin-stats-attrs
-
name: deficit
@ -2297,7 +2350,8 @@ attribute-sets:
type: string
-
name: act
type: array-nest
type: indexed-array
sub-type: nest
nested-attributes: tc-act-attrs
-
name: key-eth-dst
@ -2798,7 +2852,8 @@ attribute-sets:
type: string
-
name: act
type: array-nest
type: indexed-array
sub-type: nest
nested-attributes: tc-act-attrs
-
name: mask
@ -2951,7 +3006,8 @@ attribute-sets:
type: u32
-
name: act
type: array-nest
type: indexed-array
sub-type: nest
nested-attributes: tc-act-attrs
-
name: flags
@ -3324,7 +3380,8 @@ attribute-sets:
nested-attributes: tc-police-attrs
-
name: act
type: array-nest
type: indexed-array
sub-type: nest
nested-attributes: tc-act-attrs
-
name: tc-taprio-attrs
@ -3542,7 +3599,8 @@ attribute-sets:
nested-attributes: tc-police-attrs
-
name: act
type: array-nest
type: indexed-array
sub-type: nest
nested-attributes: tc-act-attrs
-
name: indev

204
Documentation/netlink/specs/team.yaml Normal file
View File

@ -0,0 +1,204 @@
# SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause)
name: team
protocol: genetlink-legacy
doc: |
Network team device driver.
c-family-name: team-genl-name
c-version-name: team-genl-version
kernel-policy: global
uapi-header: linux/if_team.h
definitions:
-
name: string-max-len
type: const
value: 32
-
name: genl-change-event-mc-grp-name
type: const
value: change_event
attribute-sets:
-
name: team
doc:
The team nested layout of get/set msg looks like
[TEAM_ATTR_LIST_OPTION]
[TEAM_ATTR_ITEM_OPTION]
[TEAM_ATTR_OPTION_*], ...
[TEAM_ATTR_ITEM_OPTION]
[TEAM_ATTR_OPTION_*], ...
...
[TEAM_ATTR_LIST_PORT]
[TEAM_ATTR_ITEM_PORT]
[TEAM_ATTR_PORT_*], ...
[TEAM_ATTR_ITEM_PORT]
[TEAM_ATTR_PORT_*], ...
...
name-prefix: team-attr-
attributes:
-
name: unspec
type: unused
value: 0
-
name: team-ifindex
type: u32
-
name: list-option
type: nest
nested-attributes: item-option
-
name: list-port
type: nest
nested-attributes: item-port
-
name: item-option
name-prefix: team-attr-item-
attr-cnt-name: __team-attr-item-option-max
attr-max-name: team-attr-item-option-max
attributes:
-
name: option-unspec
type: unused
value: 0
-
name: option
type: nest
nested-attributes: attr-option
-
name: attr-option
name-prefix: team-attr-option-
attributes:
-
name: unspec
type: unused
value: 0
-
name: name
type: string
checks:
max-len: string-max-len
unterminated-ok: true
-
name: changed
type: flag
-
name: type
type: u8
-
name: data
type: binary
-
name: removed
type: flag
-
name: port-ifindex
type: u32
doc: for per-port options
-
name: array-index
type: u32
doc: for array options
-
name: item-port
name-prefix: team-attr-item-
attr-cnt-name: __team-attr-item-port-max
attr-max-name: team-attr-item-port-max
attributes:
-
name: port-unspec
type: unused
value: 0
-
name: port
type: nest
nested-attributes: attr-port
-
name: attr-port
name-prefix: team-attr-port-
attributes:
-
name: unspec
type: unused
value: 0
-
name: ifindex
type: u32
-
name: changed
type: flag
-
name: linkup
type: flag
-
name: speed
type: u32
-
name: duplex
type: u8
-
name: removed
type: flag
operations:
list:
-
name: noop
doc: No operation
value: 0
attribute-set: team
dont-validate: [ strict ]
do:
# Actually it only reply the team netlink family
reply:
attributes:
- team-ifindex
-
name: options-set
doc: Set team options
attribute-set: team
dont-validate: [ strict ]
flags: [ admin-perm ]
do:
request: &option_attrs
attributes:
- team-ifindex
- list-option
reply: *option_attrs
-
name: options-get
doc: Get team options info
attribute-set: team
dont-validate: [ strict ]
flags: [ admin-perm ]
do:
request:
attributes:
- team-ifindex
reply: *option_attrs
-
name: port-list-get
doc: Get team ports info
attribute-set: team
dont-validate: [ strict ]
flags: [ admin-perm ]
do:
request:
attributes:
- team-ifindex
reply: &port_attrs
attributes:
- team-ifindex
- list-port

11
Documentation/networking/device_drivers/ethernet/mellanox/mlx5/counters.rst
View File

@ -300,6 +300,11 @@ the software port.
in the beginning of the queue. This is a normal condition.
- Informative
* - `tx[i]_timestamps`
- Transmitted packets that were hardware timestamped at the device's DMA
layer.
- Informative
* - `tx[i]_added_vlan_packets`
- The number of packets sent where vlan tag insertion was offloaded to the
hardware.
@ -702,6 +707,12 @@ the software port.
the device typically ensures not posting the CQE.
- Error
* - `ptp_cq[i]_lost_cqe`
- Number of times a CQE is expected to not be delivered on the PTP
timestamping CQE by the device due to a time delta elapsing. If such a
CQE is somehow delivered, `ptp_cq[i]_late_cqe` is incremented.
- Error
.. [#ring_global] The corresponding ring and global counters do not share the
same name (i.e. do not follow the common naming scheme).

5
Documentation/networking/devlink/devlink-info.rst
View File

@ -146,6 +146,11 @@ board.manufacture
An identifier of the company or the facility which produced the part.
board.part_number
-----------------
Part number of the board and its components.
fw
--

33
Documentation/networking/devlink/devlink-port.rst
View File

@ -134,6 +134,9 @@ Users may also set the IPsec crypto capability of the function using
Users may also set the IPsec packet capability of the function using
`devlink port function set ipsec_packet` command.
Users may also set the maximum IO event queues of the function
using `devlink port function set max_io_eqs` command.
Function attributes
===================
@ -295,6 +298,36 @@ policy is processed in software by the kernel.
function:
hw_addr 00:00:00:00:00:00 ipsec_packet enabled
Maximum IO events queues setup
------------------------------
When user sets maximum number of IO event queues for a SF or
a VF, such function driver is limited to consume only enforced
number of IO event queues.
IO event queues deliver events related to IO queues, including network
device transmit and receive queues (txq and rxq) and RDMA Queue Pairs (QPs).
For example, the number of netdevice channels and RDMA device completion
vectors are derived from the function's IO event queues. Usually, the number
of interrupt vectors consumed by the driver is limited by the number of IO
event queues per device, as each of the IO event queues is connected to an
interrupt vector.
- Get maximum IO event queues of the VF device::
$ devlink port show pci/0000:06:00.0/2
pci/0000:06:00.0/2: type eth netdev enp6s0pf0vf1 flavour pcivf pfnum 0 vfnum 1
function:
hw_addr 00:00:00:00:00:00 ipsec_packet disabled max_io_eqs 10
- Set maximum IO event queues of the VF device::
$ devlink port function set pci/0000:06:00.0/2 max_io_eqs 32
$ devlink port show pci/0000:06:00.0/2
pci/0000:06:00.0/2: type eth netdev enp6s0pf0vf1 flavour pcivf pfnum 0 vfnum 1
function:
hw_addr 00:00:00:00:00:00 ipsec_packet disabled max_io_eqs 32
Subfunction
============

5
Documentation/networking/devlink/hns3.rst
View File

@ -23,3 +23,8 @@ The ``hns3`` driver reports the following versions
* - ``fw``
- running
- Used to represent the firmware version.
* - ``fw.scc``
- running
- Used to represent the Soft Congestion Control (SSC) firmware version.
SCC is a firmware component which provides multiple RDMA congestion
control algorithms, including DCQCN.

47
Documentation/networking/devlink/ice.rst
View File

@ -21,6 +21,53 @@ Parameters
* - ``enable_iwarp``
- runtime
- mutually exclusive with ``enable_roce``
* - ``tx_scheduling_layers``
- permanent
- The ice hardware uses hierarchical scheduling for Tx with a fixed
number of layers in the scheduling tree. Each of them are decision
points. Root node represents a port, while all the leaves represent
the queues. This way of configuring the Tx scheduler allows features
like DCB or devlink-rate (documented below) to configure how much
bandwidth is given to any given queue or group of queues, enabling
fine-grained control because scheduling parameters can be configured
at any given layer of the tree.
The default 9-layer tree topology was deemed best for most workloads,
as it gives an optimal ratio of performance to configurability. However,
for some specific cases, this 9-layer topology might not be desired.
One example would be sending traffic to queues that are not a multiple
of 8. Because the maximum radix is limited to 8 in 9-layer topology,
the 9th queue has a different parent than the rest, and it's given
more bandwidth credits. This causes a problem when the system is
sending traffic to 9 queues:
| tx_queue_0_packets: 24163396
| tx_queue_1_packets: 24164623
| tx_queue_2_packets: 24163188
| tx_queue_3_packets: 24163701
| tx_queue_4_packets: 24163683
| tx_queue_5_packets: 24164668
| tx_queue_6_packets: 23327200
| tx_queue_7_packets: 24163853
| tx_queue_8_packets: 91101417 < Too much traffic is sent from 9th
To address this need, you can switch to a 5-layer topology, which
changes the maximum topology radix to 512. With this enhancement,
the performance characteristic is equal as all queues can be assigned
to the same parent in the tree. The obvious drawback of this solution
is a lower configuration depth of the tree.
Use the ``tx_scheduling_layer`` parameter with the devlink command
to change the transmit scheduler topology. To use 5-layer topology,
use a value of 5. For example:
$ devlink dev param set pci/0000:16:00.0 name tx_scheduling_layers
value 5 cmode permanent
Use a value of 9 to set it back to the default value.
You must do PCI slot powercycle for the selected topology to take effect.
To verify that value has been set:
$ devlink dev param show pci/0000:16:00.0 name tx_scheduling_layers
Info versions
=============

5
Documentation/networking/devlink/nfp.rst
View File

@ -32,7 +32,7 @@ The ``nfp`` driver reports the following versions
- Description
* - ``board.id``
- fixed
- Part number identifying the board design
- Identifier of the board design
* - ``board.rev``
- fixed
- Revision of the board design
@ -42,6 +42,9 @@ The ``nfp`` driver reports the following versions
* - ``board.model``
- fixed
- Model name of the board design
* - ``board.part_number``
- fixed
- Part number of the board and its components
* - ``fw.bundle_id``
- stored, running
- Firmware bundle id

4
Documentation/networking/dns_resolver.rst
View File

@ -118,7 +118,7 @@ Keys of dns_resolver type can be read from userspace using keyctl_read() or
Mechanism
=========
The dnsresolver module registers a key type called "dns_resolver". Keys of
The dns_resolver module registers a key type called "dns_resolver". Keys of
this type are used to transport and cache DNS lookup results from userspace.
When dns_query() is invoked, it calls request_key() to search the local
@ -152,4 +152,4 @@ Debugging
Debugging messages can be turned on dynamically by writing a 1 into the
following file::
/sys/module/dnsresolver/parameters/debug
/sys/module/dns_resolver/parameters/debug

36
Documentation/networking/ethtool-netlink.rst
View File

@ -57,6 +57,7 @@ Structure of this header is
``ETHTOOL_A_HEADER_DEV_INDEX`` u32 device ifindex
``ETHTOOL_A_HEADER_DEV_NAME`` string device name
``ETHTOOL_A_HEADER_FLAGS`` u32 flags common for all requests
``ETHTOOL_A_HEADER_PHY_INDEX`` u32 phy device index
============================== ====== =============================
``ETHTOOL_A_HEADER_DEV_INDEX`` and ``ETHTOOL_A_HEADER_DEV_NAME`` identify the
@ -81,6 +82,12 @@ the behaviour is backward compatible, i.e. requests from old clients not aware
of the flag should be interpreted the way the client expects. A client must
not set flags it does not understand.
``ETHTOOL_A_HEADER_PHY_INDEX`` identifies the Ethernet PHY the message relates to.
As there are numerous commands that are related to PHY configuration, and because
there may be more than one PHY on the link, the PHY index can be passed in the
request for the commands that needs it. It is, however, not mandatory, and if it
is not passed for commands that target a PHY, the net_device.phydev pointer
is used.
Bit sets
========
@ -1237,12 +1244,21 @@ Kernel response contents:
``ETHTOOL_A_TSINFO_TX_TYPES`` bitset supported Tx types
``ETHTOOL_A_TSINFO_RX_FILTERS`` bitset supported Rx filters
``ETHTOOL_A_TSINFO_PHC_INDEX`` u32 PTP hw clock index
``ETHTOOL_A_TSINFO_STATS`` nested HW timestamping statistics
===================================== ====== ==========================
``ETHTOOL_A_TSINFO_PHC_INDEX`` is absent if there is no associated PHC (there
is no special value for this case). The bitset attributes are omitted if they
would be empty (no bit set).
Additional hardware timestamping statistics response contents:
===================================== ====== ===================================
``ETHTOOL_A_TS_STAT_TX_PKTS`` uint Packets with Tx HW timestamps
``ETHTOOL_A_TS_STAT_TX_LOST`` uint Tx HW timestamp not arrived count
``ETHTOOL_A_TS_STAT_TX_ERR`` uint HW error request Tx timestamp count
===================================== ====== ===================================
CABLE_TEST
==========
@ -1717,6 +1733,10 @@ Kernel response contents:
PSE functions
``ETHTOOL_A_PODL_PSE_PW_D_STATUS`` u32 power detection status of the
PoDL PSE.
``ETHTOOL_A_C33_PSE_ADMIN_STATE`` u32 Operational state of the PoE
PSE functions.
``ETHTOOL_A_C33_PSE_PW_D_STATUS`` u32 power detection status of the
PoE PSE.
====================================== ====== =============================
When set, the optional ``ETHTOOL_A_PODL_PSE_ADMIN_STATE`` attribute identifies
@ -1728,6 +1748,12 @@ aPoDLPSEAdminState. Possible values are:
.. kernel-doc:: include/uapi/linux/ethtool.h
:identifiers: ethtool_podl_pse_admin_state
The same goes for ``ETHTOOL_A_C33_PSE_ADMIN_STATE`` implementing
``IEEE 802.3-2022`` 30.9.1.1.2 aPSEAdminState.
.. kernel-doc:: include/uapi/linux/ethtool.h
:identifiers: ethtool_c33_pse_admin_state
When set, the optional ``ETHTOOL_A_PODL_PSE_PW_D_STATUS`` attribute identifies
the power detection status of the PoDL PSE. The status depend on internal PSE
state machine and automatic PD classification support. This option is
@ -1737,6 +1763,12 @@ Possible values are:
.. kernel-doc:: include/uapi/linux/ethtool.h
:identifiers: ethtool_podl_pse_pw_d_status
The same goes for ``ETHTOOL_A_C33_PSE_ADMIN_PW_D_STATUS`` implementing
``IEEE 802.3-2022`` 30.9.1.1.5 aPSEPowerDetectionStatus.
.. kernel-doc:: include/uapi/linux/ethtool.h
:identifiers: ethtool_c33_pse_pw_d_status
PSE_SET
=======
@ -1747,6 +1779,7 @@ Request contents:
====================================== ====== =============================
``ETHTOOL_A_PSE_HEADER`` nested request header
``ETHTOOL_A_PODL_PSE_ADMIN_CONTROL`` u32 Control PoDL PSE Admin state
``ETHTOOL_A_C33_PSE_ADMIN_CONTROL`` u32 Control PSE Admin state
====================================== ====== =============================
When set, the optional ``ETHTOOL_A_PODL_PSE_ADMIN_CONTROL`` attribute is used
@ -1754,6 +1787,9 @@ to control PoDL PSE Admin functions. This option is implementing
``IEEE 802.3-2018`` 30.15.1.2.1 acPoDLPSEAdminControl. See
``ETHTOOL_A_PODL_PSE_ADMIN_STATE`` for supported values.
The same goes for ``ETHTOOL_A_C33_PSE_ADMIN_CONTROL`` implementing
``IEEE 802.3-2022`` 30.9.1.2.1 acPSEAdminControl.
RSS_GET
=======

1
Documentation/networking/index.rst
View File

@ -93,6 +93,7 @@ Contents:
plip
ppp_generic
proc_net_tcp
pse-pd/index
radiotap-headers
rds
regulatory

10
Documentation/networking/pse-pd/index.rst Normal file
View File

@ -0,0 +1,10 @@
.. SPDX-License-Identifier: GPL-2.0
Power Sourcing Equipment (PSE) Documentation
============================================
.. toctree::
:maxdepth: 2
introduction
pse-pi

73
Documentation/networking/pse-pd/introduction.rst Normal file
View File

@ -0,0 +1,73 @@
.. SPDX-License-Identifier: GPL-2.0
Power Sourcing Equipment (PSE) in IEEE 802.3 Standard
=====================================================
Overview
--------
Power Sourcing Equipment (PSE) is essential in networks for delivering power
along with data over Ethernet cables. It usually refers to devices like
switches and hubs that supply power to Powered Devices (PDs) such as IP
cameras, VoIP phones, and wireless access points.
PSE vs. PoDL PSE
----------------
PSE in the IEEE 802.3 standard generally refers to equipment that provides
power alongside data over Ethernet cables, typically associated with Power over
Ethernet (PoE).
PoDL PSE, or Power over Data Lines PSE, specifically denotes PSEs operating
with single balanced twisted-pair PHYs, as per Clause 104 of IEEE 802.3. PoDL
is significant in contexts like automotive and industrial controls where power
and data delivery over a single pair is advantageous.
IEEE 802.3-2018 Addendums and Related Clauses
---------------------------------------------
Key addenda to the IEEE 802.3-2018 standard relevant to power delivery over
Ethernet are as follows:
- **802.3af (Approved in 2003-06-12)**: Known as PoE in the market, detailed in
Clause 33, delivering up to 15.4W of power.
- **802.3at (Approved in 2009-09-11)**: Marketed as PoE+, enhancing PoE as
covered in Clause 33, increasing power delivery to up to 30W.
- **802.3bt (Approved in 2018-09-27)**: Known as 4PPoE in the market, outlined
in Clause 33. Type 3 delivers up to 60W, and Type 4 up to 100W.
- **802.3bu (Approved in 2016-12-07)**: Formerly referred to as PoDL, detailed
in Clause 104. Introduces Classes 0 - 9. Class 9 PoDL PSE delivers up to ~65W
Kernel Naming Convention Recommendations
----------------------------------------
For clarity and consistency within the Linux kernel's networking subsystem, the
following naming conventions are recommended:
- For general PSE (PoE) code, use "c33_pse" key words. For example:
``enum ethtool_c33_pse_admin_state c33_admin_control;``.
This aligns with Clause 33, encompassing various PoE forms.
- For PoDL PSE - specific code, use "podl_pse". For example:
``enum ethtool_podl_pse_admin_state podl_admin_control;`` to differentiate
PoDL PSE settings according to Clause 104.
Summary of Clause 33: Data Terminal Equipment (DTE) Power via Media Dependent Interface (MDI)
---------------------------------------------------------------------------------------------
Clause 33 of the IEEE 802.3 standard defines the functional and electrical
characteristics of Powered Device (PD) and Power Sourcing Equipment (PSE).
These entities enable power delivery using the same generic cabling as for data
transmission, integrating power with data communication for devices such as
10BASE-T, 100BASE-TX, or 1000BASE-T.
Summary of Clause 104: Power over Data Lines (PoDL) of Single Balanced Twisted-Pair Ethernet
--------------------------------------------------------------------------------------------
Clause 104 of the IEEE 802.3 standard delineates the functional and electrical
characteristics of PoDL Powered Devices (PDs) and PoDL Power Sourcing Equipment
(PSEs). These are designed for use with single balanced twisted-pair Ethernet
Physical Layers. In this clause, 'PSE' refers specifically to PoDL PSE, and
'PD' to PoDL PD. The key intent is to provide devices with a unified interface
for both data and the power required to process this data over a single
balanced twisted-pair Ethernet connection.

301
Documentation/networking/pse-pd/pse-pi.rst Normal file
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@ -0,0 +1,301 @@
.. SPDX-License-Identifier: GPL-2.0
PSE Power Interface (PSE PI) Documentation
==========================================
The Power Sourcing Equipment Power Interface (PSE PI) plays a pivotal role in
the architecture of Power over Ethernet (PoE) systems. It is essentially a
blueprint that outlines how one or multiple power sources are connected to the
eight-pin modular jack, commonly known as the Ethernet RJ45 port. This
connection scheme is crucial for enabling the delivery of power alongside data
over Ethernet cables.
Documentation and Standards
---------------------------
The IEEE 802.3 standard provides detailed documentation on the PSE PI.
Specifically:
- Section "33.2.3 PI pin assignments" covers the pin assignments for PoE
systems that utilize two pairs for power delivery.
- Section "145.2.4 PSE PI" addresses the configuration for PoE systems that
deliver power over all four pairs of an Ethernet cable.
PSE PI and Single Pair Ethernet
-------------------------------
Single Pair Ethernet (SPE) represents a different approach to Ethernet
connectivity, utilizing just one pair of conductors for both data and power
transmission. Unlike the configurations detailed in the PSE PI for standard
Ethernet, which can involve multiple power sourcing arrangements across four or
two pairs of wires, SPE operates on a simpler model due to its single-pair
design. As a result, the complexities of choosing between alternative pin
assignments for power delivery, as described in the PSE PI for multi-pair
Ethernet, are not applicable to SPE.
Understanding PSE PI
--------------------
The Power Sourcing Equipment Power Interface (PSE PI) is a framework defining
how Power Sourcing Equipment (PSE) delivers power to Powered Devices (PDs) over
Ethernet cables. It details two main configurations for power delivery, known
as Alternative A and Alternative B, which are distinguished not only by their
method of power transmission but also by the implications for polarity and data
transmission direction.
Alternative A and B Overview
----------------------------
- **Alternative A:** Utilizes RJ45 conductors 1, 2, 3 and 6. In either case of
networks 10/100BaseT or 1G/2G/5G/10GBaseT, the pairs used are carrying data.
The power delivery's polarity in this alternative can vary based on the MDI
(Medium Dependent Interface) or MDI-X (Medium Dependent Interface Crossover)
configuration.
- **Alternative B:** Utilizes RJ45 conductors 4, 5, 7 and 8. In case of
10/100BaseT network the pairs used are spare pairs without data and are less
influenced by data transmission direction. This is not the case for
1G/2G/5G/10GBaseT network. Alternative B includes two configurations with
different polarities, known as variant X and variant S, to accommodate
different network requirements and device specifications.
Table 145-3 PSE Pinout Alternatives
-----------------------------------
The following table outlines the pin configurations for both Alternative A and
Alternative B.
+------------+-------------------+-----------------+-----------------+-----------------+
| Conductor | Alternative A | Alternative A | Alternative B | Alternative B |
| | (MDI-X) | (MDI) | (X) | (S) |
+============+===================+=================+=================+=================+
| 1 | Negative V | Positive V | - | - |
+------------+-------------------+-----------------+-----------------+-----------------+
| 2 | Negative V | Positive V | - | - |
+------------+-------------------+-----------------+-----------------+-----------------+
| 3 | Positive V | Negative V | - | - |
+------------+-------------------+-----------------+-----------------+-----------------+
| 4 | - | - | Negative V | Positive V |
+------------+-------------------+-----------------+-----------------+-----------------+
| 5 | - | - | Negative V | Positive V |
+------------+-------------------+-----------------+-----------------+-----------------+
| 6 | Positive V | Negative V | - | - |
+------------+-------------------+-----------------+-----------------+-----------------+
| 7 | - | - | Positive V | Negative V |
+------------+-------------------+-----------------+-----------------+-----------------+
| 8 | - | - | Positive V | Negative V |
+------------+-------------------+-----------------+-----------------+-----------------+
.. note::
- "Positive V" and "Negative V" indicate the voltage polarity for each pin.
- "-" indicates that the pin is not used for power delivery in that
specific configuration.
PSE PI compatibilities
----------------------
The following table outlines the compatibility between the pinout alternative
and the 1000/2.5G/5G/10GBaseT in the PSE 2 pairs connection.
+---------+---------------+---------------------+-----------------------+
| Variant | Alternative | Power Feeding Type | Compatibility with |
| | (A/B) | (Direct/Phantom) | 1000/2.5G/5G/10GBaseT |
+=========+===============+=====================+=======================+
| 1 | A | Phantom | Yes |
+---------+---------------+---------------------+-----------------------+
| 2 | B | Phantom | Yes |
+---------+---------------+---------------------+-----------------------+
| 3 | B | Direct | No |
+---------+---------------+---------------------+-----------------------+
.. note::
- "Direct" indicate a variant where the power is injected directly to pairs
without using magnetics in case of spare pairs.
- "Phantom" indicate power path over coils/magnetics as it is done for
Alternative A variant.
In case of PSE 4 pairs, a PSE supporting only 10/100BaseT (which mean Direct
Power on pinout Alternative B) is not compatible with a 4 pairs
1000/2.5G/5G/10GBaseT.
PSE Power Interface (PSE PI) Connection Diagram
-----------------------------------------------
The diagram below illustrates the connection architecture between the RJ45
port, the Ethernet PHY (Physical Layer), and the PSE PI (Power Sourcing
Equipment Power Interface), demonstrating how power and data are delivered
simultaneously through an Ethernet cable. The RJ45 port serves as the physical
interface for these connections, with each of its eight pins connected to both
the Ethernet PHY for data transmission and the PSE PI for power delivery.
.. code-block::
+--------------------------+
| |
| RJ45 Port |
| |
+--+--+--+--+--+--+--+--+--+ +-------------+
1| 2| 3| 4| 5| 6| 7| 8| | |
| | | | | | | o-------------------+ |
| | | | | | o--|-------------------+ +<--- PSE 1
| | | | | o--|--|-------------------+ |
| | | | o--|--|--|-------------------+ |
| | | o--|--|--|--|-------------------+ PSE PI |
| | o--|--|--|--|--|-------------------+ |
| o--|--|--|--|--|--|-------------------+ +<--- PSE 2 (optional)
o--|--|--|--|--|--|--|-------------------+ |
| | | | | | | | | |
+--+--+--+--+--+--+--+--+--+ +-------------+
| |
| Ethernet PHY |
| |
+--------------------------+
Simple PSE PI Configuration for Alternative A
---------------------------------------------
The diagram below illustrates a straightforward PSE PI (Power Sourcing
Equipment Power Interface) configuration designed to support the Alternative A
setup for Power over Ethernet (PoE). This implementation is tailored to provide
power delivery through the data-carrying pairs of an Ethernet cable, suitable
for either MDI or MDI-X configurations, albeit supporting one variation at a
time.
.. code-block::
+-------------+
| PSE PI |
8 -----+ +-------------+
7 -----+ Rail 1 |
6 -----+------+----------------------+
5 -----+ | |
4 -----+ | Rail 2 | PSE 1
3 -----+------/ +------------+
2 -----+--+-------------/ |
1 -----+--/ +-------------+
|
+-------------+
In this configuration:
- Pins 1 and 2, as well as pins 3 and 6, are utilized for power delivery in
addition to data transmission. This aligns with the standard wiring for
10/100BaseT Ethernet networks where these pairs are used for data.
- Rail 1 and Rail 2 represent the positive and negative voltage rails, with
Rail 1 connected to pins 1 and 2, and Rail 2 connected to pins 3 and 6.
More advanced PSE PI configurations may include integrated or external
switches to change the polarity of the voltage rails, allowing for
compatibility with both MDI and MDI-X configurations.
More complex PSE PI configurations may include additional components, to support
Alternative B, or to provide additional features such as power management, or
additional power delivery capabilities such as 2-pair or 4-pair power delivery.
.. code-block::
+-------------+
| PSE PI |
| +---+
8 -----+--------+ | +-------------+
7 -----+--------+ | Rail 1 |
6 -----+--------+ +-----------------+
5 -----+--------+ | |
4 -----+--------+ | Rail 2 | PSE 1
3 -----+--------+ +----------------+
2 -----+--------+ | |
1 -----+--------+ | +-------------+
| +---+
+-------------+
Device Tree Configuration: Describing PSE PI Configurations
-----------------------------------------------------------
The necessity for a separate PSE PI node in the device tree is influenced by
the intricacy of the Power over Ethernet (PoE) system's setup. Here are
descriptions of both simple and complex PSE PI configurations to illustrate
this decision-making process:
**Simple PSE PI Configuration:**
In a straightforward scenario, the PSE PI setup involves a direct, one-to-one
connection between a single PSE controller and an Ethernet port. This setup
typically supports basic PoE functionality without the need for dynamic
configuration or management of multiple power delivery modes. For such simple
configurations, detailing the PSE PI within the existing PSE controller's node
may suffice, as the system does not encompass additional complexity that
warrants a separate node. The primary focus here is on the clear and direct
association of power delivery to a specific Ethernet port.
**Complex PSE PI Configuration:**
Contrastingly, a complex PSE PI setup may encompass multiple PSE controllers or
auxiliary circuits that collectively manage power delivery to one Ethernet
port. Such configurations might support a range of PoE standards and require
the capability to dynamically configure power delivery based on the operational
mode (e.g., PoE2 versus PoE4) or specific requirements of connected devices. In
these instances, a dedicated PSE PI node becomes essential for accurately
documenting the system architecture. This node would serve to detail the
interactions between different PSE controllers, the support for various PoE
modes, and any additional logic required to coordinate power delivery across
the network infrastructure.
**Guidance:**
For simple PSE setups, including PSE PI information in the PSE controller node
might suffice due to the straightforward nature of these systems. However,
complex configurations, involving multiple components or advanced PoE features,
benefit from a dedicated PSE PI node. This method adheres to IEEE 802.3
specifications, improving documentation clarity and ensuring accurate
representation of the PoE system's complexity.
PSE PI Node: Essential Information
----------------------------------
The PSE PI (Power Sourcing Equipment Power Interface) node in a device tree can
include several key pieces of information critical for defining the power
delivery capabilities and configurations of a PoE (Power over Ethernet) system.
Below is a list of such information, along with explanations for their
necessity and reasons why they might not be found within a PSE controller node:
1. **Powered Pairs Configuration**
- *Description:* Identifies the pairs used for power delivery in the
Ethernet cable.
- *Necessity:* Essential to ensure the correct pairs are powered according
to the board's design.
- *PSE Controller Node:* Typically lacks details on physical pair usage,
focusing on power regulation.
2. **Polarity of Powered Pairs**
- *Description:* Specifies the polarity (positive or negative) for each
powered pair.
- *Necessity:* Critical for safe and effective power transmission to PDs.
- *PSE Controller Node:* Polarity management may exceed the standard
functionalities of PSE controllers.
3. **PSE Cells Association**
- *Description:* Details the association of PSE cells with Ethernet ports or
pairs in multi-cell configurations.
- *Necessity:* Allows for optimized power resource allocation in complex
systems.
- *PSE Controller Node:* Controllers may not manage cell associations
directly, focusing instead on power flow regulation.
4. **Support for PoE Standards**
- *Description:* Lists the PoE standards and configurations supported by the
system.
- *Necessity:* Ensures system compatibility with various PDs and adherence
to industry standards.
- *PSE Controller Node:* Specific capabilities may depend on the overall PSE
PI design rather than the controller alone. Multiple PSE cells per PI
do not necessarily imply support for multiple PoE standards.
5. **Protection Mechanisms**
- *Description:* Outlines additional protection mechanisms, such as
overcurrent protection and thermal management.
- *Necessity:* Provides extra safety and stability, complementing PSE
controller protections.
- *PSE Controller Node:* Some protections may be implemented via
board-specific hardware or algorithms external to the controller.

6
Documentation/networking/xfrm_proc.rst
View File

@ -73,6 +73,9 @@ XfrmAcquireError:
XfrmFwdHdrError:
Forward routing of a packet is not allowed
XfrmInStateDirError:
State direction mismatch (lookup found an output state on the input path, expected input or no direction)
Outbound errors
~~~~~~~~~~~~~~~
XfrmOutError:
@ -111,3 +114,6 @@ XfrmOutPolError:
XfrmOutStateInvalid:
State is invalid, perhaps expired
XfrmOutStateDirError:
State direction mismatch (lookup found an input state on the output path, expected output or no direction)

2
Documentation/translations/zh_CN/mm/page_frags.rst
View File

@ -25,7 +25,7 @@ sk_buff->head使用，或者用于skb_shared_info的 “frags” 部分。
网络堆栈在每个CPU使用两个独立的缓存来处理碎片分配。netdev_alloc_cache被使用
netdev_alloc_frag和__netdev_alloc_skb调用的调用者使用。napi_alloc_cache
被调用__napi_alloc_frag和__napi_alloc_skb的调用者使用。这两个调用的主要区别是
被调用__napi_alloc_frag和napi_alloc_skb的调用者使用。这两个调用的主要区别是
它们可能被调用的环境。“netdev” 前缀的函数可以在任何上下文中使用，因为这些函数
将禁用中断，而 ”napi“ 前缀的函数只可以在softirq上下文中使用。

22
Documentation/userspace-api/netlink/genetlink-legacy.rst
View File

@ -46,10 +46,16 @@ For reference the ``multi-attr`` array may look like this::
where ``ARRAY-ATTR`` is the array entry type.
array-nest
~~~~~~~~~~
indexed-array
~~~~~~~~~~~~~
``array-nest`` creates the following structure::
``indexed-array`` wraps the entire array in an extra attribute (hence
limiting its size to 64kB). The ``ENTRY`` nests are special and have the
index of the entry as their type instead of normal attribute type.
A ``sub-type`` is needed to describe what type in the ``ENTRY``. A ``nest``
``sub-type`` means there are nest arrays in the ``ENTRY``, with the structure
looks like::
[SOME-OTHER-ATTR]
[ARRAY-ATTR]
@ -60,9 +66,13 @@ array-nest
[MEMBER1]
[MEMBER2]
It wraps the entire array in an extra attribute (hence limiting its size
to 64kB). The ``ENTRY`` nests are special and have the index of the entry
as their type instead of normal attribute type.
Other ``sub-type`` like ``u32`` means there is only one member as described
in ``sub-type`` in the ``ENTRY``. The structure looks like::
[SOME-OTHER-ATTR]
[ARRAY-ATTR]
[ENTRY u32]
[ENTRY u32]
type-value
~~~~~~~~~~

41
MAINTAINERS
View File

@ -3824,6 +3824,14 @@ F: kernel/bpf/tnum.c
F: kernel/bpf/trampoline.c
F: kernel/bpf/verifier.c
BPF [CRYPTO]
M: Vadim Fedorenko <vadim.fedorenko@linux.dev>
L: bpf@vger.kernel.org
S: Maintained
F: crypto/bpf_crypto_skcipher.c
F: include/linux/bpf_crypto.h
F: kernel/bpf/crypto.c
BPF [DOCUMENTATION] (Related to Standardization)
R: David Vernet <void@manifault.com>
L: bpf@vger.kernel.org
@ -8013,6 +8021,8 @@ F: include/linux/mii.h
F: include/linux/of_net.h
F: include/linux/phy.h
F: include/linux/phy_fixed.h
F: include/linux/phy_link_topology.h
F: include/linux/phy_link_topology_core.h
F: include/linux/phylib_stubs.h
F: include/linux/platform_data/mdio-bcm-unimac.h
F: include/linux/platform_data/mdio-gpio.h
@ -12388,6 +12398,26 @@ F: drivers/ata/
F: include/linux/ata.h
F: include/linux/libata.h
LIBETH COMMON ETHERNET LIBRARY
M: Alexander Lobakin <aleksander.lobakin@intel.com>
L: netdev@vger.kernel.org
L: intel-wired-lan@lists.osuosl.org (moderated for non-subscribers)
S: Supported
T: git https://github.com/alobakin/linux.git
F: drivers/net/ethernet/intel/libeth/
F: include/net/libeth/
K: libeth
LIBIE COMMON INTEL ETHERNET LIBRARY
M: Alexander Lobakin <aleksander.lobakin@intel.com>
L: intel-wired-lan@lists.osuosl.org (moderated for non-subscribers)
L: netdev@vger.kernel.org
S: Supported
T: git https://github.com/alobakin/linux.git
F: drivers/net/ethernet/intel/libie/
F: include/linux/net/intel/libie/
K: libie
LIBNVDIMM BTT: BLOCK TRANSLATION TABLE
M: Vishal Verma <vishal.l.verma@intel.com>
M: Dan Williams <dan.j.williams@intel.com>
@ -15259,6 +15289,7 @@ F: net/*/netfilter.c
F: net/*/netfilter/
F: net/bridge/br_netfilter*.c
F: net/netfilter/
F: tools/testing/selftests/net/netfilter/
NETROM NETWORK LAYER
M: Ralf Baechle <ralf@linux-mips.org>
@ -17767,6 +17798,14 @@ F: include/net/psample.h
F: include/uapi/linux/psample.h
F: net/psample
PSE NETWORK DRIVER
M: Oleksij Rempel <o.rempel@pengutronix.de>
M: Kory Maincent <kory.maincent@bootlin.com>
L: netdev@vger.kernel.org
S: Maintained
F: Documentation/devicetree/bindings/net/pse-pd/
F: drivers/net/pse-pd/
PSTORE FILESYSTEM
M: Kees Cook <keescook@chromium.org>
R: Tony Luck <tony.luck@intel.com>
@ -21661,6 +21700,7 @@ TEAM DRIVER
M: Jiri Pirko <jiri@resnulli.us>
L: netdev@vger.kernel.org
S: Supported
F: Documentation/netlink/specs/team.yaml
F: drivers/net/team/
F: include/linux/if_team.h
F: include/uapi/linux/if_team.h
@ -23426,6 +23466,7 @@ F: include/linux/virtio*.h
F: include/linux/vringh.h
F: include/uapi/linux/virtio_*.h
F: tools/virtio/
F: tools/testing/selftests/drivers/net/virtio_net/
VIRTIO CRYPTO DRIVER
M: Gonglei <arei.gonglei@huawei.com>

25
arch/arm/net/bpf_jit_32.c
View File

@ -2252,28 +2252,21 @@ struct bpf_prog *bpf_int_jit_compile(struct bpf_prog *prog)
/* If building the body of the JITed code fails somehow,
* we fall back to the interpretation.
*/
if (build_body(&ctx) < 0) {
image_ptr = NULL;
bpf_jit_binary_free(header);
prog = orig_prog;
goto out_imms;
}
if (build_body(&ctx) < 0)
goto out_free;
build_epilogue(&ctx);
/* 3.) Extra pass to validate JITed Code */
if (validate_code(&ctx)) {
image_ptr = NULL;
bpf_jit_binary_free(header);
prog = orig_prog;
goto out_imms;
}
if (validate_code(&ctx))
goto out_free;
flush_icache_range((u32)header, (u32)(ctx.target + ctx.idx));
if (bpf_jit_enable > 1)
/* there are 2 passes here */
bpf_jit_dump(prog->len, image_size, 2, ctx.target);
bpf_jit_binary_lock_ro(header);
if (bpf_jit_binary_lock_ro(header))
goto out_free;
prog->bpf_func = (void *)ctx.target;
prog->jited = 1;
prog->jited_len = image_size;
@ -2290,5 +2283,11 @@ out:
bpf_jit_prog_release_other(prog, prog == orig_prog ?
tmp : orig_prog);
return prog;
out_free:
image_ptr = NULL;
bpf_jit_binary_free(header);
prog = orig_prog;
goto out_imms;
}

93
arch/arm64/net/bpf_jit_comp.c
View File

@ -29,6 +29,7 @@
#define TCALL_CNT (MAX_BPF_JIT_REG + 2)
#define TMP_REG_3 (MAX_BPF_JIT_REG + 3)
#define FP_BOTTOM (MAX_BPF_JIT_REG + 4)
#define ARENA_VM_START (MAX_BPF_JIT_REG + 5)
#define check_imm(bits, imm) do { \
if ((((imm) > 0) && ((imm) >> (bits))) || \
@ -67,6 +68,8 @@ static const int bpf2a64[] = {
/* temporary register for blinding constants */
[BPF_REG_AX] = A64_R(9),
[FP_BOTTOM] = A64_R(27),
/* callee saved register for kern_vm_start address */
[ARENA_VM_START] = A64_R(28),
};
struct jit_ctx {
@ -79,6 +82,7 @@ struct jit_ctx {
__le32 *ro_image;
u32 stack_size;
int fpb_offset;
u64 user_vm_start;
};
struct bpf_plt {
@ -295,7 +299,7 @@ static bool is_lsi_offset(int offset, int scale)
#define PROLOGUE_OFFSET (BTI_INSNS + 2 + PAC_INSNS + 8)
static int build_prologue(struct jit_ctx *ctx, bool ebpf_from_cbpf,
bool is_exception_cb)
bool is_exception_cb, u64 arena_vm_start)
{
const struct bpf_prog *prog = ctx->prog;
const bool is_main_prog = !bpf_is_subprog(prog);
@ -306,6 +310,7 @@ static int build_prologue(struct jit_ctx *ctx, bool ebpf_from_cbpf,
const u8 fp = bpf2a64[BPF_REG_FP];
const u8 tcc = bpf2a64[TCALL_CNT];
const u8 fpb = bpf2a64[FP_BOTTOM];
const u8 arena_vm_base = bpf2a64[ARENA_VM_START];
const int idx0 = ctx->idx;
int cur_offset;
@ -411,6 +416,10 @@ static int build_prologue(struct jit_ctx *ctx, bool ebpf_from_cbpf,
/* Set up function call stack */
emit(A64_SUB_I(1, A64_SP, A64_SP, ctx->stack_size), ctx);
if (arena_vm_start)
emit_a64_mov_i64(arena_vm_base, arena_vm_start, ctx);
return 0;
}
@ -738,6 +747,7 @@ static void build_epilogue(struct jit_ctx *ctx, bool is_exception_cb)
#define BPF_FIXUP_OFFSET_MASK GENMASK(26, 0)
#define BPF_FIXUP_REG_MASK GENMASK(31, 27)
#define DONT_CLEAR 5 /* Unused ARM64 register from BPF's POV */
bool ex_handler_bpf(const struct exception_table_entry *ex,
struct pt_regs *regs)
@ -745,7 +755,8 @@ bool ex_handler_bpf(const struct exception_table_entry *ex,
off_t offset = FIELD_GET(BPF_FIXUP_OFFSET_MASK, ex->fixup);
int dst_reg = FIELD_GET(BPF_FIXUP_REG_MASK, ex->fixup);
regs->regs[dst_reg] = 0;
if (dst_reg != DONT_CLEAR)
regs->regs[dst_reg] = 0;
regs->pc = (unsigned long)&ex->fixup - offset;
return true;
}
@ -765,7 +776,8 @@ static int add_exception_handler(const struct bpf_insn *insn,
return 0;
if (BPF_MODE(insn->code) != BPF_PROBE_MEM &&
BPF_MODE(insn->code) != BPF_PROBE_MEMSX)
BPF_MODE(insn->code) != BPF_PROBE_MEMSX &&
BPF_MODE(insn->code) != BPF_PROBE_MEM32)
return 0;
if (!ctx->prog->aux->extable ||
@ -810,6 +822,9 @@ static int add_exception_handler(const struct bpf_insn *insn,
ex->insn = ins_offset;
if (BPF_CLASS(insn->code) != BPF_LDX)
dst_reg = DONT_CLEAR;
ex->fixup = FIELD_PREP(BPF_FIXUP_OFFSET_MASK, fixup_offset) |
FIELD_PREP(BPF_FIXUP_REG_MASK, dst_reg);
@ -829,12 +844,13 @@ static int build_insn(const struct bpf_insn *insn, struct jit_ctx *ctx,
bool extra_pass)
{
const u8 code = insn->code;
const u8 dst = bpf2a64[insn->dst_reg];
const u8 src = bpf2a64[insn->src_reg];
u8 dst = bpf2a64[insn->dst_reg];
u8 src = bpf2a64[insn->src_reg];
const u8 tmp = bpf2a64[TMP_REG_1];
const u8 tmp2 = bpf2a64[TMP_REG_2];
const u8 fp = bpf2a64[BPF_REG_FP];
const u8 fpb = bpf2a64[FP_BOTTOM];
const u8 arena_vm_base = bpf2a64[ARENA_VM_START];
const s16 off = insn->off;
const s32 imm = insn->imm;
const int i = insn - ctx->prog->insnsi;
@ -853,6 +869,15 @@ static int build_insn(const struct bpf_insn *insn, struct jit_ctx *ctx,
/* dst = src */
case BPF_ALU | BPF_MOV | BPF_X:
case BPF_ALU64 | BPF_MOV | BPF_X:
if (insn_is_cast_user(insn)) {
emit(A64_MOV(0, tmp, src), ctx); // 32-bit mov clears the upper 32 bits
emit_a64_mov_i(0, dst, ctx->user_vm_start >> 32, ctx);
emit(A64_LSL(1, dst, dst, 32), ctx);
emit(A64_CBZ(1, tmp, 2), ctx);
emit(A64_ORR(1, tmp, dst, tmp), ctx);
emit(A64_MOV(1, dst, tmp), ctx);
break;
}
switch (insn->off) {
case 0:
emit(A64_MOV(is64, dst, src), ctx);
@ -1237,7 +1262,15 @@ emit_cond_jmp:
case BPF_LDX | BPF_PROBE_MEMSX | BPF_B:
case BPF_LDX | BPF_PROBE_MEMSX | BPF_H:
case BPF_LDX | BPF_PROBE_MEMSX | BPF_W:
if (ctx->fpb_offset > 0 && src == fp) {
case BPF_LDX | BPF_PROBE_MEM32 | BPF_B:
case BPF_LDX | BPF_PROBE_MEM32 | BPF_H:
case BPF_LDX | BPF_PROBE_MEM32 | BPF_W:
case BPF_LDX | BPF_PROBE_MEM32 | BPF_DW:
if (BPF_MODE(insn->code) == BPF_PROBE_MEM32) {
emit(A64_ADD(1, tmp2, src, arena_vm_base), ctx);
src = tmp2;
}
if (ctx->fpb_offset > 0 && src == fp && BPF_MODE(insn->code) != BPF_PROBE_MEM32) {
src_adj = fpb;
off_adj = off + ctx->fpb_offset;
} else {
@ -1322,7 +1355,15 @@ emit_cond_jmp:
case BPF_ST | BPF_MEM | BPF_H:
case BPF_ST | BPF_MEM | BPF_B:
case BPF_ST | BPF_MEM | BPF_DW:
if (ctx->fpb_offset > 0 && dst == fp) {
case BPF_ST | BPF_PROBE_MEM32 | BPF_B:
case BPF_ST | BPF_PROBE_MEM32 | BPF_H:
case BPF_ST | BPF_PROBE_MEM32 | BPF_W:
case BPF_ST | BPF_PROBE_MEM32 | BPF_DW:
if (BPF_MODE(insn->code) == BPF_PROBE_MEM32) {
emit(A64_ADD(1, tmp2, dst, arena_vm_base), ctx);
dst = tmp2;
}
if (ctx->fpb_offset > 0 && dst == fp && BPF_MODE(insn->code) != BPF_PROBE_MEM32) {
dst_adj = fpb;
off_adj = off + ctx->fpb_offset;
} else {
@ -1365,6 +1406,10 @@ emit_cond_jmp:
}
break;
}
ret = add_exception_handler(insn, ctx, dst);
if (ret)
return ret;
break;
/* STX: *(size *)(dst + off) = src */
@ -1372,7 +1417,15 @@ emit_cond_jmp:
case BPF_STX | BPF_MEM | BPF_H:
case BPF_STX | BPF_MEM | BPF_B:
case BPF_STX | BPF_MEM | BPF_DW:
if (ctx->fpb_offset > 0 && dst == fp) {
case BPF_STX | BPF_PROBE_MEM32 | BPF_B:
case BPF_STX | BPF_PROBE_MEM32 | BPF_H:
case BPF_STX | BPF_PROBE_MEM32 | BPF_W:
case BPF_STX | BPF_PROBE_MEM32 | BPF_DW:
if (BPF_MODE(insn->code) == BPF_PROBE_MEM32) {
emit(A64_ADD(1, tmp2, dst, arena_vm_base), ctx);
dst = tmp2;
}
if (ctx->fpb_offset > 0 && dst == fp && BPF_MODE(insn->code) != BPF_PROBE_MEM32) {
dst_adj = fpb;
off_adj = off + ctx->fpb_offset;
} else {
@ -1413,6 +1466,10 @@ emit_cond_jmp:
}
break;
}
ret = add_exception_handler(insn, ctx, dst);
if (ret)
return ret;
break;
case BPF_STX | BPF_ATOMIC | BPF_W:
@ -1594,6 +1651,7 @@ struct bpf_prog *bpf_int_jit_compile(struct bpf_prog *prog)
bool tmp_blinded = false;
bool extra_pass = false;
struct jit_ctx ctx;
u64 arena_vm_start;
u8 *image_ptr;
u8 *ro_image_ptr;
@ -1611,6 +1669,7 @@ struct bpf_prog *bpf_int_jit_compile(struct bpf_prog *prog)
prog = tmp;
}
arena_vm_start = bpf_arena_get_kern_vm_start(prog->aux->arena);
jit_data = prog->aux->jit_data;
if (!jit_data) {
jit_data = kzalloc(sizeof(*jit_data), GFP_KERNEL);
@ -1641,6 +1700,7 @@ struct bpf_prog *bpf_int_jit_compile(struct bpf_prog *prog)
}
ctx.fpb_offset = find_fpb_offset(prog);
ctx.user_vm_start = bpf_arena_get_user_vm_start(prog->aux->arena);
/*
* 1. Initial fake pass to compute ctx->idx and ctx->offset.
@ -1648,7 +1708,8 @@ struct bpf_prog *bpf_int_jit_compile(struct bpf_prog *prog)
* BPF line info needs ctx->offset[i] to be the offset of
* instruction[i] in jited image, so build prologue first.
*/
if (build_prologue(&ctx, was_classic, prog->aux->exception_cb)) {
if (build_prologue(&ctx, was_classic, prog->aux->exception_cb,
arena_vm_start)) {
prog = orig_prog;
goto out_off;
}
@ -1696,7 +1757,7 @@ skip_init_ctx:
ctx.idx = 0;
ctx.exentry_idx = 0;
build_prologue(&ctx, was_classic, prog->aux->exception_cb);
build_prologue(&ctx, was_classic, prog->aux->exception_cb, arena_vm_start);
if (build_body(&ctx, extra_pass)) {
prog = orig_prog;
@ -2176,12 +2237,9 @@ void arch_free_bpf_trampoline(void *image, unsigned int size)
bpf_prog_pack_free(image, size);
}
void arch_protect_bpf_trampoline(void *image, unsigned int size)
{
}
void arch_unprotect_bpf_trampoline(void *image, unsigned int size)
int arch_protect_bpf_trampoline(void *image, unsigned int size)
{
return 0;
}
int arch_prepare_bpf_trampoline(struct bpf_tramp_image *im, void *ro_image,
@ -2464,6 +2522,11 @@ bool bpf_jit_supports_exceptions(void)
return true;
}
bool bpf_jit_supports_arena(void)
{
return true;
}
void bpf_jit_free(struct bpf_prog *prog)
{
if (prog->jited) {

22
arch/loongarch/net/bpf_jit.c
View File

@ -1294,16 +1294,19 @@ skip_init_ctx:
flush_icache_range((unsigned long)header, (unsigned long)(ctx.image + ctx.idx));
if (!prog->is_func || extra_pass) {
int err;
if (extra_pass && ctx.idx != jit_data->ctx.idx) {
pr_err_once("multi-func JIT bug %d != %d\n",
ctx.idx, jit_data->ctx.idx);
bpf_jit_binary_free(header);
prog->bpf_func = NULL;
prog->jited = 0;
prog->jited_len = 0;
goto out_offset;
goto out_free;
}
err = bpf_jit_binary_lock_ro(header);
if (err) {
pr_err_once("bpf_jit_binary_lock_ro() returned %d\n",
err);
goto out_free;
}
bpf_jit_binary_lock_ro(header);
} else {
jit_data->ctx = ctx;
jit_data->image = image_ptr;
@ -1334,6 +1337,13 @@ out:
out_offset = -1;
return prog;
out_free:
bpf_jit_binary_free(header);
prog->bpf_func = NULL;
prog->jited = 0;
prog->jited_len = 0;
goto out_offset;
}
/* Indicate the JIT backend supports mixing bpf2bpf and tailcalls. */

3
arch/mips/net/bpf_jit_comp.c
View File

@ -1012,7 +1012,8 @@ struct bpf_prog *bpf_int_jit_compile(struct bpf_prog *prog)
bpf_prog_fill_jited_linfo(prog, &ctx.descriptors[1]);
/* Set as read-only exec and flush instruction cache */
bpf_jit_binary_lock_ro(header);
if (bpf_jit_binary_lock_ro(header))
goto out_err;
flush_icache_range((unsigned long)header,
(unsigned long)&ctx.target[ctx.jit_index]);

8
arch/parisc/net/bpf_jit_core.c
View File

@ -167,7 +167,13 @@ skip_init_ctx:
bpf_flush_icache(jit_data->header, ctx->insns + ctx->ninsns);
if (!prog->is_func || extra_pass) {
bpf_jit_binary_lock_ro(jit_data->header);
if (bpf_jit_binary_lock_ro(jit_data->header)) {
bpf_jit_binary_free(jit_data->header);
prog->bpf_func = NULL;
prog->jited = 0;
prog->jited_len = 0;
goto out_offset;
}
prologue_len = ctx->epilogue_offset - ctx->body_len;
for (i = 0; i < prog->len; i++)
ctx->offset[i] += prologue_len;

2
arch/riscv/net/bpf_jit.h
View File

@ -81,6 +81,8 @@ struct rv_jit_context {
int nexentries;
unsigned long flags;
int stack_size;
u64 arena_vm_start;
u64 user_vm_start;
};
/* Convert from ninsns to bytes. */

203
arch/riscv/net/bpf_jit_comp64.c
View File

@ -18,6 +18,7 @@
#define RV_REG_TCC RV_REG_A6
#define RV_REG_TCC_SAVED RV_REG_S6 /* Store A6 in S6 if program do calls */
#define RV_REG_ARENA RV_REG_S7 /* For storing arena_vm_start */
static const int regmap[] = {
[BPF_REG_0] = RV_REG_A5,
@ -255,6 +256,10 @@ static void __build_epilogue(bool is_tail_call, struct rv_jit_context *ctx)
emit_ld(RV_REG_S6, store_offset, RV_REG_SP, ctx);
store_offset -= 8;
}
if (ctx->arena_vm_start) {
emit_ld(RV_REG_ARENA, store_offset, RV_REG_SP, ctx);
store_offset -= 8;
}
emit_addi(RV_REG_SP, RV_REG_SP, stack_adjust, ctx);
/* Set return value. */
@ -548,6 +553,7 @@ static void emit_atomic(u8 rd, u8 rs, s16 off, s32 imm, bool is64,
#define BPF_FIXUP_OFFSET_MASK GENMASK(26, 0)
#define BPF_FIXUP_REG_MASK GENMASK(31, 27)
#define REG_DONT_CLEAR_MARKER 0 /* RV_REG_ZERO unused in pt_regmap */
bool ex_handler_bpf(const struct exception_table_entry *ex,
struct pt_regs *regs)
@ -555,7 +561,8 @@ bool ex_handler_bpf(const struct exception_table_entry *ex,
off_t offset = FIELD_GET(BPF_FIXUP_OFFSET_MASK, ex->fixup);
int regs_offset = FIELD_GET(BPF_FIXUP_REG_MASK, ex->fixup);
*(unsigned long *)((void *)regs + pt_regmap[regs_offset]) = 0;
if (regs_offset != REG_DONT_CLEAR_MARKER)
*(unsigned long *)((void *)regs + pt_regmap[regs_offset]) = 0;
regs->epc = (unsigned long)&ex->fixup - offset;
return true;
@ -572,7 +579,8 @@ static int add_exception_handler(const struct bpf_insn *insn,
off_t fixup_offset;
if (!ctx->insns || !ctx->ro_insns || !ctx->prog->aux->extable ||
(BPF_MODE(insn->code) != BPF_PROBE_MEM && BPF_MODE(insn->code) != BPF_PROBE_MEMSX))
(BPF_MODE(insn->code) != BPF_PROBE_MEM && BPF_MODE(insn->code) != BPF_PROBE_MEMSX &&
BPF_MODE(insn->code) != BPF_PROBE_MEM32))
return 0;
if (WARN_ON_ONCE(ctx->nexentries >= ctx->prog->aux->num_exentries))
@ -1073,6 +1081,15 @@ int bpf_jit_emit_insn(const struct bpf_insn *insn, struct rv_jit_context *ctx,
/* dst = src */
case BPF_ALU | BPF_MOV | BPF_X:
case BPF_ALU64 | BPF_MOV | BPF_X:
if (insn_is_cast_user(insn)) {
emit_mv(RV_REG_T1, rs, ctx);
emit_zextw(RV_REG_T1, RV_REG_T1, ctx);
emit_imm(rd, (ctx->user_vm_start >> 32) << 32, ctx);
emit(rv_beq(RV_REG_T1, RV_REG_ZERO, 4), ctx);
emit_or(RV_REG_T1, rd, RV_REG_T1, ctx);
emit_mv(rd, RV_REG_T1, ctx);
break;
}
if (imm == 1) {
/* Special mov32 for zext */
emit_zextw(rd, rd, ctx);
@ -1539,6 +1556,11 @@ int bpf_jit_emit_insn(const struct bpf_insn *insn, struct rv_jit_context *ctx,
case BPF_LDX | BPF_PROBE_MEMSX | BPF_B:
case BPF_LDX | BPF_PROBE_MEMSX | BPF_H:
case BPF_LDX | BPF_PROBE_MEMSX | BPF_W:
/* LDX | PROBE_MEM32: dst = *(unsigned size *)(src + RV_REG_ARENA + off) */
case BPF_LDX | BPF_PROBE_MEM32 | BPF_B:
case BPF_LDX | BPF_PROBE_MEM32 | BPF_H:
case BPF_LDX | BPF_PROBE_MEM32 | BPF_W:
case BPF_LDX | BPF_PROBE_MEM32 | BPF_DW:
{
int insn_len, insns_start;
bool sign_ext;
@ -1546,6 +1568,11 @@ int bpf_jit_emit_insn(const struct bpf_insn *insn, struct rv_jit_context *ctx,
sign_ext = BPF_MODE(insn->code) == BPF_MEMSX ||
BPF_MODE(insn->code) == BPF_PROBE_MEMSX;
if (BPF_MODE(insn->code) == BPF_PROBE_MEM32) {
emit_add(RV_REG_T2, rs, RV_REG_ARENA, ctx);
rs = RV_REG_T2;
}
switch (BPF_SIZE(code)) {
case BPF_B:
if (is_12b_int(off)) {
@ -1682,6 +1709,86 @@ int bpf_jit_emit_insn(const struct bpf_insn *insn, struct rv_jit_context *ctx,
emit_sd(RV_REG_T2, 0, RV_REG_T1, ctx);
break;
case BPF_ST | BPF_PROBE_MEM32 | BPF_B:
case BPF_ST | BPF_PROBE_MEM32 | BPF_H:
case BPF_ST | BPF_PROBE_MEM32 | BPF_W:
case BPF_ST | BPF_PROBE_MEM32 | BPF_DW:
{
int insn_len, insns_start;
emit_add(RV_REG_T3, rd, RV_REG_ARENA, ctx);
rd = RV_REG_T3;
/* Load imm to a register then store it */
emit_imm(RV_REG_T1, imm, ctx);
switch (BPF_SIZE(code)) {
case BPF_B:
if (is_12b_int(off)) {
insns_start = ctx->ninsns;
emit(rv_sb(rd, off, RV_REG_T1), ctx);
insn_len = ctx->ninsns - insns_start;
break;
}
emit_imm(RV_REG_T2, off, ctx);
emit_add(RV_REG_T2, RV_REG_T2, rd, ctx);
insns_start = ctx->ninsns;
emit(rv_sb(RV_REG_T2, 0, RV_REG_T1), ctx);
insn_len = ctx->ninsns - insns_start;
break;
case BPF_H:
if (is_12b_int(off)) {
insns_start = ctx->ninsns;
emit(rv_sh(rd, off, RV_REG_T1), ctx);
insn_len = ctx->ninsns - insns_start;
break;
}
emit_imm(RV_REG_T2, off, ctx);
emit_add(RV_REG_T2, RV_REG_T2, rd, ctx);
insns_start = ctx->ninsns;
emit(rv_sh(RV_REG_T2, 0, RV_REG_T1), ctx);
insn_len = ctx->ninsns - insns_start;
break;
case BPF_W:
if (is_12b_int(off)) {
insns_start = ctx->ninsns;
emit_sw(rd, off, RV_REG_T1, ctx);
insn_len = ctx->ninsns - insns_start;
break;
}
emit_imm(RV_REG_T2, off, ctx);
emit_add(RV_REG_T2, RV_REG_T2, rd, ctx);
insns_start = ctx->ninsns;
emit_sw(RV_REG_T2, 0, RV_REG_T1, ctx);
insn_len = ctx->ninsns - insns_start;
break;
case BPF_DW:
if (is_12b_int(off)) {
insns_start = ctx->ninsns;
emit_sd(rd, off, RV_REG_T1, ctx);
insn_len = ctx->ninsns - insns_start;
break;
}
emit_imm(RV_REG_T2, off, ctx);
emit_add(RV_REG_T2, RV_REG_T2, rd, ctx);
insns_start = ctx->ninsns;
emit_sd(RV_REG_T2, 0, RV_REG_T1, ctx);
insn_len = ctx->ninsns - insns_start;
break;
}
ret = add_exception_handler(insn, ctx, REG_DONT_CLEAR_MARKER,
insn_len);
if (ret)
return ret;
break;
}
/* STX: *(size *)(dst + off) = src */
case BPF_STX | BPF_MEM | BPF_B:
if (is_12b_int(off)) {
@ -1728,6 +1835,84 @@ int bpf_jit_emit_insn(const struct bpf_insn *insn, struct rv_jit_context *ctx,
emit_atomic(rd, rs, off, imm,
BPF_SIZE(code) == BPF_DW, ctx);
break;
case BPF_STX | BPF_PROBE_MEM32 | BPF_B:
case BPF_STX | BPF_PROBE_MEM32 | BPF_H:
case BPF_STX | BPF_PROBE_MEM32 | BPF_W:
case BPF_STX | BPF_PROBE_MEM32 | BPF_DW:
{
int insn_len, insns_start;
emit_add(RV_REG_T2, rd, RV_REG_ARENA, ctx);
rd = RV_REG_T2;
switch (BPF_SIZE(code)) {
case BPF_B:
if (is_12b_int(off)) {
insns_start = ctx->ninsns;
emit(rv_sb(rd, off, rs), ctx);
insn_len = ctx->ninsns - insns_start;
break;
}
emit_imm(RV_REG_T1, off, ctx);
emit_add(RV_REG_T1, RV_REG_T1, rd, ctx);
insns_start = ctx->ninsns;
emit(rv_sb(RV_REG_T1, 0, rs), ctx);
insn_len = ctx->ninsns - insns_start;
break;
case BPF_H:
if (is_12b_int(off)) {
insns_start = ctx->ninsns;
emit(rv_sh(rd, off, rs), ctx);
insn_len = ctx->ninsns - insns_start;
break;
}
emit_imm(RV_REG_T1, off, ctx);
emit_add(RV_REG_T1, RV_REG_T1, rd, ctx);
insns_start = ctx->ninsns;
emit(rv_sh(RV_REG_T1, 0, rs), ctx);
insn_len = ctx->ninsns - insns_start;
break;
case BPF_W:
if (is_12b_int(off)) {
insns_start = ctx->ninsns;
emit_sw(rd, off, rs, ctx);
insn_len = ctx->ninsns - insns_start;
break;
}
emit_imm(RV_REG_T1, off, ctx);
emit_add(RV_REG_T1, RV_REG_T1, rd, ctx);
insns_start = ctx->ninsns;
emit_sw(RV_REG_T1, 0, rs, ctx);
insn_len = ctx->ninsns - insns_start;
break;
case BPF_DW:
if (is_12b_int(off)) {
insns_start = ctx->ninsns;
emit_sd(rd, off, rs, ctx);
insn_len = ctx->ninsns - insns_start;
break;
}
emit_imm(RV_REG_T1, off, ctx);
emit_add(RV_REG_T1, RV_REG_T1, rd, ctx);
insns_start = ctx->ninsns;
emit_sd(RV_REG_T1, 0, rs, ctx);
insn_len = ctx->ninsns - insns_start;
break;
}
ret = add_exception_handler(insn, ctx, REG_DONT_CLEAR_MARKER,
insn_len);
if (ret)
return ret;
break;
}
default:
pr_err("bpf-jit: unknown opcode %02x\n", code);
return -EINVAL;
@ -1759,6 +1944,8 @@ void bpf_jit_build_prologue(struct rv_jit_context *ctx, bool is_subprog)
stack_adjust += 8;
if (seen_reg(RV_REG_S6, ctx))
stack_adjust += 8;
if (ctx->arena_vm_start)
stack_adjust += 8;
stack_adjust = round_up(stack_adjust, 16);
stack_adjust += bpf_stack_adjust;
@ -1810,6 +1997,10 @@ void bpf_jit_build_prologue(struct rv_jit_context *ctx, bool is_subprog)
emit_sd(RV_REG_SP, store_offset, RV_REG_S6, ctx);
store_offset -= 8;
}
if (ctx->arena_vm_start) {
emit_sd(RV_REG_SP, store_offset, RV_REG_ARENA, ctx);
store_offset -= 8;
}
emit_addi(RV_REG_FP, RV_REG_SP, stack_adjust, ctx);
@ -1823,6 +2014,9 @@ void bpf_jit_build_prologue(struct rv_jit_context *ctx, bool is_subprog)
emit_mv(RV_REG_TCC_SAVED, RV_REG_TCC, ctx);
ctx->stack_size = stack_adjust;
if (ctx->arena_vm_start)
emit_imm(RV_REG_ARENA, ctx->arena_vm_start, ctx);
}
void bpf_jit_build_epilogue(struct rv_jit_context *ctx)
@ -1839,3 +2033,8 @@ bool bpf_jit_supports_ptr_xchg(void)
{
return true;
}
bool bpf_jit_supports_arena(void)
{
return true;
}

2
arch/riscv/net/bpf_jit_core.c
View File

@ -80,6 +80,8 @@ struct bpf_prog *bpf_int_jit_compile(struct bpf_prog *prog)
goto skip_init_ctx;
}
ctx->arena_vm_start = bpf_arena_get_kern_vm_start(prog->aux->arena);
ctx->user_vm_start = bpf_arena_get_user_vm_start(prog->aux->arena);
ctx->prog = prog;
ctx->offset = kcalloc(prog->len, sizeof(int), GFP_KERNEL);
if (!ctx->offset) {

6
arch/s390/net/bpf_jit_comp.c
View File

@ -2108,7 +2108,11 @@ skip_init_ctx:
print_fn_code(jit.prg_buf, jit.size_prg);
}
if (!fp->is_func || extra_pass) {
bpf_jit_binary_lock_ro(header);
if (bpf_jit_binary_lock_ro(header)) {
bpf_jit_binary_free(header);
fp = orig_fp;
goto free_addrs;
}
} else {
jit_data->header = header;
jit_data->ctx = jit;

6
arch/sparc/net/bpf_jit_comp_64.c
View File

@ -1602,7 +1602,11 @@ skip_init_ctx:
bpf_flush_icache(header, (u8 *)header + header->size);
if (!prog->is_func || extra_pass) {
bpf_jit_binary_lock_ro(header);
if (bpf_jit_binary_lock_ro(header)) {
bpf_jit_binary_free(header);
prog = orig_prog;
goto out_off;
}
} else {
jit_data->ctx = ctx;
jit_data->image = image_ptr;

102
arch/x86/net/bpf_jit_comp.c
View File

@ -816,9 +816,10 @@ done:
static void emit_mov_imm64(u8 **pprog, u32 dst_reg,
const u32 imm32_hi, const u32 imm32_lo)
{
u64 imm64 = ((u64)imm32_hi << 32) | (u32)imm32_lo;
u8 *prog = *pprog;
if (is_uimm32(((u64)imm32_hi << 32) | (u32)imm32_lo)) {
if (is_uimm32(imm64)) {
/*
* For emitting plain u32, where sign bit must not be
* propagated LLVM tends to load imm64 over mov32
@ -826,6 +827,8 @@ static void emit_mov_imm64(u8 **pprog, u32 dst_reg,
* 'mov %eax, imm32' instead.
*/
emit_mov_imm32(&prog, false, dst_reg, imm32_lo);
} else if (is_simm32(imm64)) {
emit_mov_imm32(&prog, true, dst_reg, imm32_lo);
} else {
/* movabsq rax, imm64 */
EMIT2(add_1mod(0x48, dst_reg), add_1reg(0xB8, dst_reg));
@ -1169,6 +1172,54 @@ static int emit_atomic(u8 **pprog, u8 atomic_op,
return 0;
}
static int emit_atomic_index(u8 **pprog, u8 atomic_op, u32 size,
u32 dst_reg, u32 src_reg, u32 index_reg, int off)
{
u8 *prog = *pprog;
EMIT1(0xF0); /* lock prefix */
switch (size) {
case BPF_W:
EMIT1(add_3mod(0x40, dst_reg, src_reg, index_reg));
break;
case BPF_DW:
EMIT1(add_3mod(0x48, dst_reg, src_reg, index_reg));
break;
default:
pr_err("bpf_jit: 1 and 2 byte atomics are not supported\n");
return -EFAULT;
}
/* emit opcode */
switch (atomic_op) {
case BPF_ADD:
case BPF_AND:
case BPF_OR:
case BPF_XOR:
/* lock *(u32/u64*)(dst_reg + idx_reg + off) <op>= src_reg */
EMIT1(simple_alu_opcodes[atomic_op]);
break;
case BPF_ADD | BPF_FETCH:
/* src_reg = atomic_fetch_add(dst_reg + idx_reg + off, src_reg); */
EMIT2(0x0F, 0xC1);
break;
case BPF_XCHG:
/* src_reg = atomic_xchg(dst_reg + idx_reg + off, src_reg); */
EMIT1(0x87);
break;
case BPF_CMPXCHG:
/* r0 = atomic_cmpxchg(dst_reg + idx_reg + off, r0, src_reg); */
EMIT2(0x0F, 0xB1);
break;
default:
pr_err("bpf_jit: unknown atomic opcode %02x\n", atomic_op);
return -EFAULT;
}
emit_insn_suffix_SIB(&prog, dst_reg, src_reg, index_reg, off);
*pprog = prog;
return 0;
}
#define DONT_CLEAR 1
bool ex_handler_bpf(const struct exception_table_entry *x, struct pt_regs *regs)
@ -1351,8 +1402,7 @@ static int do_jit(struct bpf_prog *bpf_prog, int *addrs, u8 *image, u8 *rw_image
break;
case BPF_ALU64 | BPF_MOV | BPF_X:
if (insn->off == BPF_ADDR_SPACE_CAST &&
insn->imm == 1U << 16) {
if (insn_is_cast_user(insn)) {
if (dst_reg != src_reg)
/* 32-bit mov */
emit_mov_reg(&prog, false, dst_reg, src_reg);
@ -1383,6 +1433,16 @@ static int do_jit(struct bpf_prog *bpf_prog, int *addrs, u8 *image, u8 *rw_image
maybe_emit_mod(&prog, AUX_REG, dst_reg, true);
EMIT3(0x0F, 0x44, add_2reg(0xC0, AUX_REG, dst_reg));
break;
} else if (insn_is_mov_percpu_addr(insn)) {
/* mov <dst>, <src> (if necessary) */
EMIT_mov(dst_reg, src_reg);
#ifdef CONFIG_SMP
/* add <dst>, gs:[<off>] */
EMIT2(0x65, add_1mod(0x48, dst_reg));
EMIT3(0x03, add_2reg(0x04, 0, dst_reg), 0x25);
EMIT((u32)(unsigned long)&this_cpu_off, 4);
#endif
break;
}
fallthrough;
case BPF_ALU | BPF_MOV | BPF_X:
@ -1963,6 +2023,15 @@ populate_extable:
return err;
break;
case BPF_STX | BPF_PROBE_ATOMIC | BPF_W:
case BPF_STX | BPF_PROBE_ATOMIC | BPF_DW:
start_of_ldx = prog;
err = emit_atomic_index(&prog, insn->imm, BPF_SIZE(insn->code),
dst_reg, src_reg, X86_REG_R12, insn->off);
if (err)
return err;
goto populate_extable;
/* call */
case BPF_JMP | BPF_CALL: {
u8 *ip = image + addrs[i - 1];
@ -2994,12 +3063,9 @@ void arch_free_bpf_trampoline(void *image, unsigned int size)
bpf_prog_pack_free(image, size);
}
void arch_protect_bpf_trampoline(void *image, unsigned int size)
{
}
void arch_unprotect_bpf_trampoline(void *image, unsigned int size)
int arch_protect_bpf_trampoline(void *image, unsigned int size)
{
return 0;
}
int arch_prepare_bpf_trampoline(struct bpf_tramp_image *im, void *image, void *image_end,
@ -3359,6 +3425,11 @@ bool bpf_jit_supports_subprog_tailcalls(void)
return true;
}
bool bpf_jit_supports_percpu_insn(void)
{
return true;
}
void bpf_jit_free(struct bpf_prog *prog)
{
if (prog->jited) {
@ -3462,6 +3533,21 @@ bool bpf_jit_supports_arena(void)
return true;
}
bool bpf_jit_supports_insn(struct bpf_insn *insn, bool in_arena)
{
if (!in_arena)
return true;
switch (insn->code) {
case BPF_STX | BPF_ATOMIC | BPF_W:
case BPF_STX | BPF_ATOMIC | BPF_DW:
if (insn->imm == (BPF_AND | BPF_FETCH) ||
insn->imm == (BPF_OR | BPF_FETCH) ||
insn->imm == (BPF_XOR | BPF_FETCH))
return false;
}
return true;
}
bool bpf_jit_supports_ptr_xchg(void)
{
return true;

3
arch/x86/net/bpf_jit_comp32.c
View File

@ -2600,8 +2600,7 @@ out_image:
if (bpf_jit_enable > 1)
bpf_jit_dump(prog->len, proglen, pass + 1, image);
if (image) {
bpf_jit_binary_lock_ro(header);
if (image && !bpf_jit_binary_lock_ro(header)) {
prog->bpf_func = (void *)image;
prog->jited = 1;
prog->jited_len = proglen;

3
crypto/Makefile
View File

@ -20,6 +20,9 @@ crypto_skcipher-y += lskcipher.o
crypto_skcipher-y += skcipher.o
obj-$(CONFIG_CRYPTO_SKCIPHER2) += crypto_skcipher.o
ifeq ($(CONFIG_BPF_SYSCALL),y)
obj-$(CONFIG_CRYPTO_SKCIPHER2) += bpf_crypto_skcipher.o
endif
obj-$(CONFIG_CRYPTO_SEQIV) += seqiv.o
obj-$(CONFIG_CRYPTO_ECHAINIV) += echainiv.o

4
crypto/af_alg.c
View File

@ -847,7 +847,7 @@ void af_alg_wmem_wakeup(struct sock *sk)
wake_up_interruptible_sync_poll(&wq->wait, EPOLLIN |
EPOLLRDNORM |
EPOLLRDBAND);
sk_wake_async(sk, SOCK_WAKE_WAITD, POLL_IN);
sk_wake_async_rcu(sk, SOCK_WAKE_WAITD, POLL_IN);
rcu_read_unlock();
}
EXPORT_SYMBOL_GPL(af_alg_wmem_wakeup);
@ -914,7 +914,7 @@ static void af_alg_data_wakeup(struct sock *sk)
wake_up_interruptible_sync_poll(&wq->wait, EPOLLOUT |
EPOLLRDNORM |
EPOLLRDBAND);
sk_wake_async(sk, SOCK_WAKE_SPACE, POLL_OUT);
sk_wake_async_rcu(sk, SOCK_WAKE_SPACE, POLL_OUT);
rcu_read_unlock();
}

82
crypto/bpf_crypto_skcipher.c Normal file
View File

@ -0,0 +1,82 @@
// SPDX-License-Identifier: GPL-2.0-only
/* Copyright (c) 2024 Meta, Inc */
#include <linux/types.h>
#include <linux/module.h>
#include <linux/bpf_crypto.h>
#include <crypto/skcipher.h>
static void *bpf_crypto_lskcipher_alloc_tfm(const char *algo)
{
return crypto_alloc_lskcipher(algo, 0, 0);
}
static void bpf_crypto_lskcipher_free_tfm(void *tfm)
{
crypto_free_lskcipher(tfm);
}
static int bpf_crypto_lskcipher_has_algo(const char *algo)
{
return crypto_has_skcipher(algo, CRYPTO_ALG_TYPE_LSKCIPHER, CRYPTO_ALG_TYPE_MASK);
}
static int bpf_crypto_lskcipher_setkey(void *tfm, const u8 *key, unsigned int keylen)
{
return crypto_lskcipher_setkey(tfm, key, keylen);
}
static u32 bpf_crypto_lskcipher_get_flags(void *tfm)
{
return crypto_lskcipher_get_flags(tfm);
}
static unsigned int bpf_crypto_lskcipher_ivsize(void *tfm)
{
return crypto_lskcipher_ivsize(tfm);
}
static unsigned int bpf_crypto_lskcipher_statesize(void *tfm)
{
return crypto_lskcipher_statesize(tfm);
}
static int bpf_crypto_lskcipher_encrypt(void *tfm, const u8 *src, u8 *dst,
unsigned int len, u8 *siv)
{
return crypto_lskcipher_encrypt(tfm, src, dst, len, siv);
}
static int bpf_crypto_lskcipher_decrypt(void *tfm, const u8 *src, u8 *dst,
unsigned int len, u8 *siv)
{
return crypto_lskcipher_decrypt(tfm, src, dst, len, siv);
}
static const struct bpf_crypto_type bpf_crypto_lskcipher_type = {
.alloc_tfm = bpf_crypto_lskcipher_alloc_tfm,
.free_tfm = bpf_crypto_lskcipher_free_tfm,
.has_algo = bpf_crypto_lskcipher_has_algo,
.setkey = bpf_crypto_lskcipher_setkey,
.encrypt = bpf_crypto_lskcipher_encrypt,
.decrypt = bpf_crypto_lskcipher_decrypt,
.ivsize = bpf_crypto_lskcipher_ivsize,
.statesize = bpf_crypto_lskcipher_statesize,
.get_flags = bpf_crypto_lskcipher_get_flags,
.owner = THIS_MODULE,
.name = "skcipher",
};
static int __init bpf_crypto_skcipher_init(void)
{
return bpf_crypto_register_type(&bpf_crypto_lskcipher_type);
}
static void __exit bpf_crypto_skcipher_exit(void)
{
int err = bpf_crypto_unregister_type(&bpf_crypto_lskcipher_type);
WARN_ON_ONCE(err);
}
module_init(bpf_crypto_skcipher_init);
module_exit(bpf_crypto_skcipher_exit);
MODULE_LICENSE("GPL");

3
drivers/atm/fore200e.c
View File

@ -94,9 +94,6 @@
static const struct atmdev_ops fore200e_ops;
static LIST_HEAD(fore200e_boards);
MODULE_AUTHOR("Christophe Lizzi - credits to Uwe Dannowski and Heikki Vatiainen");
MODULE_DESCRIPTION("FORE Systems 200E-series ATM driver - version " FORE200E_VERSION);

1
drivers/atm/fore200e.h
View File

@ -830,7 +830,6 @@ typedef struct fore200e_vc_map {
/* per-device data */
typedef struct fore200e {
struct list_head entry; /* next device */
const struct fore200e_bus* bus; /* bus-dependent code and data */
union fore200e_regs regs; /* bus-dependent registers */
struct atm_dev* atm_dev; /* ATM device */

6
drivers/bcma/host_soc.c
View File

@ -240,15 +240,13 @@ err_unmap_mmio:
return err;
}
static int bcma_host_soc_remove(struct platform_device *pdev)
static void bcma_host_soc_remove(struct platform_device *pdev)
{
struct bcma_bus *bus = platform_get_drvdata(pdev);
bcma_bus_unregister(bus);
iounmap(bus->mmio);
platform_set_drvdata(pdev, NULL);
return 0;
}
static const struct of_device_id bcma_host_soc_of_match[] = {
@ -263,7 +261,7 @@ static struct platform_driver bcma_host_soc_driver = {
.of_match_table = bcma_host_soc_of_match,
},
.probe = bcma_host_soc_probe,
.remove = bcma_host_soc_remove,
.remove_new = bcma_host_soc_remove,
};
int __init bcma_host_soc_register_driver(void)

4
drivers/bus/mhi/host/internal.h
View File

@ -80,6 +80,7 @@ enum dev_st_transition {
DEV_ST_TRANSITION_FP,
DEV_ST_TRANSITION_SYS_ERR,
DEV_ST_TRANSITION_DISABLE,
DEV_ST_TRANSITION_DISABLE_DESTROY_DEVICE,
DEV_ST_TRANSITION_MAX,
};
@ -90,7 +91,8 @@ enum dev_st_transition {
dev_st_trans(MISSION_MODE, "MISSION MODE") \
dev_st_trans(FP, "FLASH PROGRAMMER") \
dev_st_trans(SYS_ERR, "SYS ERROR") \
dev_st_trans_end(DISABLE, "DISABLE")
dev_st_trans(DISABLE, "DISABLE") \
dev_st_trans_end(DISABLE_DESTROY_DEVICE, "DISABLE (DESTROY DEVICE)")
extern const char * const dev_state_tran_str[DEV_ST_TRANSITION_MAX];
#define TO_DEV_STATE_TRANS_STR(state) (((state) >= DEV_ST_TRANSITION_MAX) ? \

42
drivers/bus/mhi/host/pm.c
View File

@ -468,7 +468,8 @@ error_mission_mode:
}
/* Handle shutdown transitions */
static void mhi_pm_disable_transition(struct mhi_controller *mhi_cntrl)
static void mhi_pm_disable_transition(struct mhi_controller *mhi_cntrl,
bool destroy_device)
{
enum mhi_pm_state cur_state;
struct mhi_event *mhi_event;
@ -530,8 +531,16 @@ skip_mhi_reset:
dev_dbg(dev, "Waiting for all pending threads to complete\n");
wake_up_all(&mhi_cntrl->state_event);
dev_dbg(dev, "Reset all active channels and remove MHI devices\n");
device_for_each_child(&mhi_cntrl->mhi_dev->dev, NULL, mhi_destroy_device);
/*
* Only destroy the 'struct device' for channels if indicated by the
* 'destroy_device' flag. Because, during system suspend or hibernation
* state, there is no need to destroy the 'struct device' as the endpoint
* device would still be physically attached to the machine.
*/
if (destroy_device) {
dev_dbg(dev, "Reset all active channels and remove MHI devices\n");
device_for_each_child(&mhi_cntrl->mhi_dev->dev, NULL, mhi_destroy_device);
}
mutex_lock(&mhi_cntrl->pm_mutex);
@ -821,7 +830,10 @@ void mhi_pm_st_worker(struct work_struct *work)
mhi_pm_sys_error_transition(mhi_cntrl);
break;
case DEV_ST_TRANSITION_DISABLE:
mhi_pm_disable_transition(mhi_cntrl);
mhi_pm_disable_transition(mhi_cntrl, false);
break;
case DEV_ST_TRANSITION_DISABLE_DESTROY_DEVICE:
mhi_pm_disable_transition(mhi_cntrl, true);
break;
default:
break;
@ -1175,7 +1187,8 @@ error_exit:
}
EXPORT_SYMBOL_GPL(mhi_async_power_up);
void mhi_power_down(struct mhi_controller *mhi_cntrl, bool graceful)
static void __mhi_power_down(struct mhi_controller *mhi_cntrl, bool graceful,
bool destroy_device)
{
enum mhi_pm_state cur_state, transition_state;
struct device *dev = &mhi_cntrl->mhi_dev->dev;
@ -1211,15 +1224,32 @@ void mhi_power_down(struct mhi_controller *mhi_cntrl, bool graceful)
write_unlock_irq(&mhi_cntrl->pm_lock);
mutex_unlock(&mhi_cntrl->pm_mutex);
mhi_queue_state_transition(mhi_cntrl, DEV_ST_TRANSITION_DISABLE);
if (destroy_device)
mhi_queue_state_transition(mhi_cntrl,
DEV_ST_TRANSITION_DISABLE_DESTROY_DEVICE);
else
mhi_queue_state_transition(mhi_cntrl,
DEV_ST_TRANSITION_DISABLE);
/* Wait for shutdown to complete */
flush_work(&mhi_cntrl->st_worker);
disable_irq(mhi_cntrl->irq[0]);
}
void mhi_power_down(struct mhi_controller *mhi_cntrl, bool graceful)
{
__mhi_power_down(mhi_cntrl, graceful, true);
}
EXPORT_SYMBOL_GPL(mhi_power_down);
void mhi_power_down_keep_dev(struct mhi_controller *mhi_cntrl,
bool graceful)
{
__mhi_power_down(mhi_cntrl, graceful, false);
}
EXPORT_SYMBOL_GPL(mhi_power_down_keep_dev);
int mhi_sync_power_up(struct mhi_controller *mhi_cntrl)
{
int ret = mhi_async_power_up(mhi_cntrl);

9
drivers/crypto/marvell/octeontx2/otx2_cpt_devlink.c
View File

@ -4,7 +4,8 @@
#include "otx2_cpt_devlink.h"
static int otx2_cpt_dl_egrp_create(struct devlink *dl, u32 id,
struct devlink_param_gset_ctx *ctx)
struct devlink_param_gset_ctx *ctx,
struct netlink_ext_ack *extack)
{
struct otx2_cpt_devlink *cpt_dl = devlink_priv(dl);
struct otx2_cptpf_dev *cptpf = cpt_dl->cptpf;
@ -13,7 +14,8 @@ static int otx2_cpt_dl_egrp_create(struct devlink *dl, u32 id,
}
static int otx2_cpt_dl_egrp_delete(struct devlink *dl, u32 id,
struct devlink_param_gset_ctx *ctx)
struct devlink_param_gset_ctx *ctx,
struct netlink_ext_ack *extack)
{
struct otx2_cpt_devlink *cpt_dl = devlink_priv(dl);
struct otx2_cptpf_dev *cptpf = cpt_dl->cptpf;
@ -45,7 +47,8 @@ static int otx2_cpt_dl_t106_mode_get(struct devlink *dl, u32 id,
}
static int otx2_cpt_dl_t106_mode_set(struct devlink *dl, u32 id,
struct devlink_param_gset_ctx *ctx)
struct devlink_param_gset_ctx *ctx,
struct netlink_ext_ack *extack)
{
struct otx2_cpt_devlink *cpt_dl = devlink_priv(dl);
struct otx2_cptpf_dev *cptpf = cpt_dl->cptpf;

12
drivers/infiniband/core/addr.c
View File

@ -348,16 +348,10 @@ static int dst_fetch_ha(const struct dst_entry *dst,
static bool has_gateway(const struct dst_entry *dst, sa_family_t family)
{
struct rtable *rt;
struct rt6_info *rt6;
if (family == AF_INET)
return dst_rtable(dst)->rt_uses_gateway;
if (family == AF_INET) {
rt = container_of(dst, struct rtable, dst);
return rt->rt_uses_gateway;
}
rt6 = container_of(dst, struct rt6_info, dst);
return rt6->rt6i_flags & RTF_GATEWAY;
return dst_rt6_info(dst)->rt6i_flags & RTF_GATEWAY;
}
static int fetch_ha(const struct dst_entry *dst, struct rdma_dev_addr *dev_addr,

2
drivers/infiniband/hw/hfi1/netdev.h
View File

@ -49,7 +49,7 @@ struct hfi1_netdev_rxq {
* When 0 receive queues will be freed.
*/
struct hfi1_netdev_rx {
struct net_device rx_napi;
struct net_device *rx_napi;
struct hfi1_devdata *dd;
struct hfi1_netdev_rxq *rxq;
int num_rx_q;

9
drivers/infiniband/hw/hfi1/netdev_rx.c
View File

@ -188,7 +188,7 @@ static int hfi1_netdev_rxq_init(struct hfi1_netdev_rx *rx)
int i;
int rc;
struct hfi1_devdata *dd = rx->dd;
struct net_device *dev = &rx->rx_napi;
struct net_device *dev = rx->rx_napi;
rx->num_rx_q = dd->num_netdev_contexts;
rx->rxq = kcalloc_node(rx->num_rx_q, sizeof(*rx->rxq),
@ -360,7 +360,11 @@ int hfi1_alloc_rx(struct hfi1_devdata *dd)
if (!rx)
return -ENOMEM;
rx->dd = dd;
init_dummy_netdev(&rx->rx_napi);
rx->rx_napi = alloc_netdev_dummy(0);
if (!rx->rx_napi) {
kfree(rx);
return -ENOMEM;
}
xa_init(&rx->dev_tbl);
atomic_set(&rx->enabled, 0);
@ -374,6 +378,7 @@ void hfi1_free_rx(struct hfi1_devdata *dd)
{
if (dd->netdev_rx) {
dd_dev_info(dd, "hfi1 rx freed\n");
free_netdev(dd->netdev_rx->rx_napi);
kfree(dd->netdev_rx);
dd->netdev_rx = NULL;
}

3
drivers/infiniband/hw/irdma/cm.c
View File

@ -1985,7 +1985,8 @@ static int irdma_addr_resolve_neigh(struct irdma_device *iwdev, u32 src_ip,
__be32 dst_ipaddr = htonl(dst_ip);
__be32 src_ipaddr = htonl(src_ip);
rt = ip_route_output(&init_net, dst_ipaddr, src_ipaddr, 0, 0);
rt = ip_route_output(&init_net, dst_ipaddr, src_ipaddr, 0, 0,
RT_SCOPE_UNIVERSE);
if (IS_ERR(rt)) {
ibdev_dbg(&iwdev->ibdev, "CM: ip_route_output fail\n");
return -EINVAL;

12
drivers/infiniband/hw/mana/qp.c
View File

@ -15,15 +15,13 @@ static int mana_ib_cfg_vport_steering(struct mana_ib_dev *dev,
struct mana_port_context *mpc = netdev_priv(ndev);
struct mana_cfg_rx_steer_req_v2 *req;
struct mana_cfg_rx_steer_resp resp = {};
mana_handle_t *req_indir_tab;
struct gdma_context *gc;
u32 req_buf_size;
int i, err;
gc = mdev_to_gc(dev);
req_buf_size =
sizeof(*req) + sizeof(mana_handle_t) * MANA_INDIRECT_TABLE_SIZE;
req_buf_size = struct_size(req, indir_tab, MANA_INDIRECT_TABLE_SIZE);
req = kzalloc(req_buf_size, GFP_KERNEL);
if (!req)
return -ENOMEM;
@ -44,20 +42,20 @@ static int mana_ib_cfg_vport_steering(struct mana_ib_dev *dev,
req->rss_enable = true;
req->num_indir_entries = MANA_INDIRECT_TABLE_SIZE;
req->indir_tab_offset = sizeof(*req);
req->indir_tab_offset = offsetof(struct mana_cfg_rx_steer_req_v2,
indir_tab);
req->update_indir_tab = true;
req->cqe_coalescing_enable = 1;
req_indir_tab = (mana_handle_t *)(req + 1);
/* The ind table passed to the hardware must have
* MANA_INDIRECT_TABLE_SIZE entries. Adjust the verb
* ind_table to MANA_INDIRECT_TABLE_SIZE if required
*/
ibdev_dbg(&dev->ib_dev, "ind table size %u\n", 1 << log_ind_tbl_size);
for (i = 0; i < MANA_INDIRECT_TABLE_SIZE; i++) {
req_indir_tab[i] = ind_table[i % (1 << log_ind_tbl_size)];
req->indir_tab[i] = ind_table[i % (1 << log_ind_tbl_size)];
ibdev_dbg(&dev->ib_dev, "index %u handle 0x%llx\n", i,
req_indir_tab[i]);
req->indir_tab[i]);
}
req->update_hashkey = true;

3
drivers/infiniband/hw/qedr/qedr_iw_cm.c
View File

@ -447,7 +447,8 @@ qedr_addr4_resolve(struct qedr_dev *dev,
struct rtable *rt = NULL;
int rc = 0;
rt = ip_route_output(&init_net, dst_ip, src_ip, 0, 0);
rt = ip_route_output(&init_net, dst_ip, src_ip, 0, 0,
RT_SCOPE_UNIVERSE);
if (IS_ERR(rt)) {
DP_ERR(dev, "ip_route_output returned error\n");
return -EINVAL;

4
drivers/infiniband/ulp/ipoib/ipoib_main.c
View File

@ -238,7 +238,7 @@ static int ipoib_change_mtu(struct net_device *dev, int new_mtu)
ipoib_warn(priv, "mtu > %d will cause multicast packet drops.\n",
priv->mcast_mtu);
dev->mtu = new_mtu;
WRITE_ONCE(dev->mtu, new_mtu);
return 0;
}
@ -265,7 +265,7 @@ static int ipoib_change_mtu(struct net_device *dev, int new_mtu)
if (carrier_status)
netif_carrier_on(dev);
} else {
dev->mtu = new_mtu;
WRITE_ONCE(dev->mtu, new_mtu);
}
return ret;

3
drivers/isdn/capi/Makefile
View File

@ -2,4 +2,5 @@
# Makefile for the CAPI subsystem used by BT_CMTP
obj-$(CONFIG_BT_CMTP) += kernelcapi.o
kernelcapi-y := kcapi.o capiutil.o capi.o kcapi_proc.o
kernelcapi-y := kcapi.o capiutil.o capi.o
kernelcapi-$(CONFIG_PROC_FS) += kcapi_proc.o

7
drivers/isdn/capi/kcapi.c
View File

@ -917,13 +917,16 @@ int __init kcapi_init(void)
return err;
}
kcapi_proc_init();
if (IS_ENABLED(CONFIG_PROC_FS))
kcapi_proc_init();
return 0;
}
void kcapi_exit(void)
{
kcapi_proc_exit();
if (IS_ENABLED(CONFIG_PROC_FS))
kcapi_proc_exit();
cdebug_exit();
destroy_workqueue(kcapi_wq);

5
drivers/md/dm-clone-metadata.c
View File

@ -465,11 +465,6 @@ static void __destroy_persistent_data_structures(struct dm_clone_metadata *cmd)
/*---------------------------------------------------------------------------*/
static size_t bitmap_size(unsigned long nr_bits)
{
return BITS_TO_LONGS(nr_bits) * sizeof(long);
}
static int __dirty_map_init(struct dirty_map *dmap, unsigned long nr_words,
unsigned long nr_regions)
{

16
drivers/net/Kconfig
View File

@ -290,6 +290,19 @@ config GTP
To compile this drivers as a module, choose M here: the module
will be called gtp.
config PFCP
tristate "Packet Forwarding Control Protocol (PFCP)"
depends on INET
select NET_UDP_TUNNEL
help
This allows one to create PFCP virtual interfaces that allows to
set up software and hardware offload of PFCP packets.
Note that this module does not support PFCP protocol in the kernel space.
There is no support for parsing any PFCP messages.
To compile this drivers as a module, choose M here: the module
will be called pfcp.
config AMT
tristate "Automatic Multicast Tunneling (AMT)"
depends on INET && IP_MULTICAST
@ -507,7 +520,7 @@ source "drivers/net/ipa/Kconfig"
config NET_SB1000
tristate "General Instruments Surfboard 1000"
depends on PNP
depends on ISA && PNP
help
This is a driver for the General Instrument (also known as
NextLevel) SURFboard 1000 internal
@ -627,6 +640,7 @@ config NETDEVSIM
depends on PSAMPLE || PSAMPLE=n
depends on PTP_1588_CLOCK_MOCK || PTP_1588_CLOCK_MOCK=n
select NET_DEVLINK
select PAGE_POOL
help
This driver is a developer testing tool and software model that can
be used to test various control path networking APIs, especially

1
drivers/net/Makefile
View File

@ -38,6 +38,7 @@ obj-$(CONFIG_GENEVE) += geneve.o
obj-$(CONFIG_BAREUDP) += bareudp.o
obj-$(CONFIG_GTP) += gtp.o
obj-$(CONFIG_NLMON) += nlmon.o
obj-$(CONFIG_PFCP) += pfcp.o
obj-$(CONFIG_NET_VRF) += vrf.o
obj-$(CONFIG_VSOCKMON) += vsockmon.o
obj-$(CONFIG_MHI_NET) += mhi_net.o

2
drivers/net/arcnet/Kconfig
View File

@ -4,7 +4,7 @@
#
menuconfig ARCNET
depends on NETDEVICES && (ISA || PCI || PCMCIA)
depends on NETDEVICES && (ISA || PCI || PCMCIA) && HAS_IOPORT
tristate "ARCnet support"
help
If you have a network card of this type, say Y and check out the

3
drivers/net/arcnet/arcdevice.h
View File

@ -16,6 +16,7 @@
#ifdef __KERNEL__
#include <linux/interrupt.h>
#include <linux/workqueue.h>
/*
* RECON_THRESHOLD is the maximum number of RECON messages to receive
@ -268,7 +269,7 @@ struct arcnet_local {
struct net_device *dev;
int reply_status;
struct tasklet_struct reply_tasklet;
struct work_struct reply_work;
/*
* Buffer management: an ARCnet card has 4 x 512-byte buffers, each of

11
drivers/net/arcnet/arcnet.c
View File

@ -54,6 +54,7 @@
#include <linux/errqueue.h>
#include <linux/leds.h>
#include <linux/workqueue.h>
#include "arcdevice.h"
#include "com9026.h"
@ -424,9 +425,9 @@ out:
rtnl_unlock();
}
static void arcnet_reply_tasklet(struct tasklet_struct *t)
static void arcnet_reply_work(struct work_struct *t)
{
struct arcnet_local *lp = from_tasklet(lp, t, reply_tasklet);
struct arcnet_local *lp = from_work(lp, t, reply_work);
struct sk_buff *ackskb, *skb;
struct sock_exterr_skb *serr;
@ -527,7 +528,7 @@ int arcnet_open(struct net_device *dev)
arc_cont(D_PROTO, "\n");
}
tasklet_setup(&lp->reply_tasklet, arcnet_reply_tasklet);
INIT_WORK(&lp->reply_work, arcnet_reply_work);
arc_printk(D_INIT, dev, "arcnet_open: resetting card.\n");
@ -620,7 +621,7 @@ int arcnet_close(struct net_device *dev)
netif_stop_queue(dev);
netif_carrier_off(dev);
tasklet_kill(&lp->reply_tasklet);
cancel_work_sync(&lp->reply_work);
/* flush TX and disable RX */
lp->hw.intmask(dev, 0);
@ -984,7 +985,7 @@ irqreturn_t arcnet_interrupt(int irq, void *dev_id)
->ack_tx(dev, ackstatus);
}
lp->reply_status = ackstatus;
tasklet_hi_schedule(&lp->reply_tasklet);
queue_work(system_bh_highpri_wq, &lp->reply_work);
}
if (lp->cur_tx != -1)
release_arcbuf(dev, lp->cur_tx);

19
drivers/net/bareudp.c
View File

@ -61,6 +61,7 @@ struct bareudp_dev {
static int bareudp_udp_encap_recv(struct sock *sk, struct sk_buff *skb)
{
struct metadata_dst *tun_dst = NULL;
IP_TUNNEL_DECLARE_FLAGS(key) = { };
struct bareudp_dev *bareudp;
unsigned short family;
unsigned int len;
@ -137,7 +138,10 @@ static int bareudp_udp_encap_recv(struct sock *sk, struct sk_buff *skb)
bareudp->dev->stats.rx_dropped++;
goto drop;
}
tun_dst = udp_tun_rx_dst(skb, family, TUNNEL_KEY, 0, 0);
__set_bit(IP_TUNNEL_KEY_BIT, key);
tun_dst = udp_tun_rx_dst(skb, family, key, 0, 0);
if (!tun_dst) {
bareudp->dev->stats.rx_dropped++;
goto drop;
@ -285,10 +289,10 @@ static int bareudp_xmit_skb(struct sk_buff *skb, struct net_device *dev,
struct bareudp_dev *bareudp,
const struct ip_tunnel_info *info)
{
bool udp_sum = test_bit(IP_TUNNEL_CSUM_BIT, info->key.tun_flags);
bool xnet = !net_eq(bareudp->net, dev_net(bareudp->dev));
bool use_cache = ip_tunnel_dst_cache_usable(skb, info);
struct socket *sock = rcu_dereference(bareudp->sock);
bool udp_sum = !!(info->key.tun_flags & TUNNEL_CSUM);
const struct ip_tunnel_key *key = &info->key;
struct rtable *rt;
__be16 sport, df;
@ -316,7 +320,8 @@ static int bareudp_xmit_skb(struct sk_buff *skb, struct net_device *dev,
tos = ip_tunnel_ecn_encap(key->tos, ip_hdr(skb), skb);
ttl = key->ttl;
df = key->tun_flags & TUNNEL_DONT_FRAGMENT ? htons(IP_DF) : 0;
df = test_bit(IP_TUNNEL_DONT_FRAGMENT_BIT, key->tun_flags) ?
htons(IP_DF) : 0;
skb_scrub_packet(skb, xnet);
err = -ENOSPC;
@ -338,7 +343,8 @@ static int bareudp_xmit_skb(struct sk_buff *skb, struct net_device *dev,
udp_tunnel_xmit_skb(rt, sock->sk, skb, saddr, info->key.u.ipv4.dst,
tos, ttl, df, sport, bareudp->port,
!net_eq(bareudp->net, dev_net(bareudp->dev)),
!(info->key.tun_flags & TUNNEL_CSUM));
!test_bit(IP_TUNNEL_CSUM_BIT,
info->key.tun_flags));
return 0;
free_dst:
@ -350,10 +356,10 @@ static int bareudp6_xmit_skb(struct sk_buff *skb, struct net_device *dev,
struct bareudp_dev *bareudp,
const struct ip_tunnel_info *info)
{
bool udp_sum = test_bit(IP_TUNNEL_CSUM_BIT, info->key.tun_flags);
bool xnet = !net_eq(bareudp->net, dev_net(bareudp->dev));
bool use_cache = ip_tunnel_dst_cache_usable(skb, info);
struct socket *sock = rcu_dereference(bareudp->sock);
bool udp_sum = !!(info->key.tun_flags & TUNNEL_CSUM);
const struct ip_tunnel_key *key = &info->key;
struct dst_entry *dst = NULL;
struct in6_addr saddr, daddr;
@ -402,7 +408,8 @@ static int bareudp6_xmit_skb(struct sk_buff *skb, struct net_device *dev,
udp_tunnel6_xmit_skb(dst, sock->sk, skb, dev,
&saddr, &daddr, prio, ttl,
info->key.label, sport, bareudp->port,
!(info->key.tun_flags & TUNNEL_CSUM));
!test_bit(IP_TUNNEL_CSUM_BIT,
info->key.tun_flags));
return 0;
free_dst:

12
drivers/net/bonding/bond_main.c
View File

@ -3014,8 +3014,8 @@ static void bond_arp_send_all(struct bonding *bond, struct slave *slave)
tags = NULL;
/* Find out through which dev should the packet go */
rt = ip_route_output(dev_net(bond->dev), targets[i], 0,
RTO_ONLINK, 0);
rt = ip_route_output(dev_net(bond->dev), targets[i], 0, 0, 0,
RT_SCOPE_LINK);
if (IS_ERR(rt)) {
/* there's no route to target - try to send arp
* probe to generate any traffic (arp_validate=0)
@ -4710,7 +4710,7 @@ static int bond_change_mtu(struct net_device *bond_dev, int new_mtu)
}
}
bond_dev->mtu = new_mtu;
WRITE_ONCE(bond_dev->mtu, new_mtu);
return 0;
@ -5245,7 +5245,7 @@ static inline int bond_slave_override(struct bonding *bond,
/* Find out if any slaves have the same mapping as this skb. */
bond_for_each_slave_rcu(bond, slave, iter) {
if (slave->queue_id == skb_get_queue_mapping(skb)) {
if (READ_ONCE(slave->queue_id) == skb_get_queue_mapping(skb)) {
if (bond_slave_is_up(slave) &&
slave->link == BOND_LINK_UP) {
bond_dev_queue_xmit(bond, skb, slave->dev);
@ -5933,7 +5933,7 @@ static void bond_uninit(struct net_device *bond_dev)
bond_set_slave_arr(bond, NULL, NULL);
list_del(&bond->bond_list);
list_del_rcu(&bond->bond_list);
bond_debug_unregister(bond);
}
@ -6347,7 +6347,7 @@ static int bond_init(struct net_device *bond_dev)
spin_lock_init(&bond->stats_lock);
netdev_lockdep_set_classes(bond_dev);
list_add_tail(&bond->bond_list, &bn->dev_list);
list_add_tail_rcu(&bond->bond_list, &bn->dev_list);
bond_prepare_sysfs_group(bond);

3
drivers/net/bonding/bond_netlink.c
View File

@ -51,7 +51,8 @@ static int bond_fill_slave_info(struct sk_buff *skb,
slave_dev->addr_len, slave->perm_hwaddr))
goto nla_put_failure;
if (nla_put_u16(skb, IFLA_BOND_SLAVE_QUEUE_ID, slave->queue_id))
if (nla_put_u16(skb, IFLA_BOND_SLAVE_QUEUE_ID,
READ_ONCE(slave->queue_id)))
goto nla_put_failure;
if (nla_put_s32(skb, IFLA_BOND_SLAVE_PRIO, slave->prio))

2
drivers/net/bonding/bond_options.c
View File

@ -1589,7 +1589,7 @@ static int bond_option_queue_id_set(struct bonding *bond,
goto err_no_cmd;
/* Actually set the qids for the slave */
update_slave->queue_id = qid;
WRITE_ONCE(update_slave->queue_id, qid);
out:
return ret;

2
drivers/net/bonding/bond_procfs.c
View File

@ -209,7 +209,7 @@ static void bond_info_show_slave(struct seq_file *seq,
seq_printf(seq, "Permanent HW addr: %*phC\n",
slave->dev->addr_len, slave->perm_hwaddr);
seq_printf(seq, "Slave queue ID: %d\n", slave->queue_id);
seq_printf(seq, "Slave queue ID: %d\n", READ_ONCE(slave->queue_id));
if (BOND_MODE(bond) == BOND_MODE_8023AD) {
const struct port *port = &SLAVE_AD_INFO(slave)->port;

25
drivers/net/bonding/bond_sysfs.c
View File

@ -37,12 +37,12 @@ static ssize_t bonding_show_bonds(const struct class *cls,
{
const struct bond_net *bn =
container_of_const(attr, struct bond_net, class_attr_bonding_masters);
int res = 0;
struct bonding *bond;
int res = 0;
rtnl_lock();
rcu_read_lock();
list_for_each_entry(bond, &bn->dev_list, bond_list) {
list_for_each_entry_rcu(bond, &bn->dev_list, bond_list) {
if (res > (PAGE_SIZE - IFNAMSIZ)) {
/* not enough space for another interface name */
if ((PAGE_SIZE - res) > 10)
@ -55,7 +55,7 @@ static ssize_t bonding_show_bonds(const struct class *cls,
if (res)
buf[res-1] = '\n'; /* eat the leftover space */
rtnl_unlock();
rcu_read_unlock();
return res;
}
@ -170,10 +170,9 @@ static ssize_t bonding_show_slaves(struct device *d,
struct slave *slave;
int res = 0;
if (!rtnl_trylock())
return restart_syscall();
rcu_read_lock();
bond_for_each_slave(bond, slave, iter) {
bond_for_each_slave_rcu(bond, slave, iter) {
if (res > (PAGE_SIZE - IFNAMSIZ)) {
/* not enough space for another interface name */
if ((PAGE_SIZE - res) > 10)
@ -184,7 +183,7 @@ static ssize_t bonding_show_slaves(struct device *d,
res += sysfs_emit_at(buf, res, "%s ", slave->dev->name);
}
rtnl_unlock();
rcu_read_unlock();
if (res)
buf[res-1] = '\n'; /* eat the leftover space */
@ -626,10 +625,9 @@ static ssize_t bonding_show_queue_id(struct device *d,
struct slave *slave;
int res = 0;
if (!rtnl_trylock())
return restart_syscall();
rcu_read_lock();
bond_for_each_slave(bond, slave, iter) {
bond_for_each_slave_rcu(bond, slave, iter) {
if (res > (PAGE_SIZE - IFNAMSIZ - 6)) {
/* not enough space for another interface_name:queue_id pair */
if ((PAGE_SIZE - res) > 10)
@ -638,12 +636,13 @@ static ssize_t bonding_show_queue_id(struct device *d,
break;
}
res += sysfs_emit_at(buf, res, "%s:%d ",
slave->dev->name, slave->queue_id);
slave->dev->name,
READ_ONCE(slave->queue_id));
}
if (res)
buf[res-1] = '\n'; /* eat the leftover space */
rtnl_unlock();
rcu_read_unlock();
return res;
}

2
drivers/net/bonding/bond_sysfs_slave.c
View File

@ -53,7 +53,7 @@ static SLAVE_ATTR_RO(perm_hwaddr);
static ssize_t queue_id_show(struct slave *slave, char *buf)
{
return sysfs_emit(buf, "%d\n", slave->queue_id);
return sysfs_emit(buf, "%d\n", READ_ONCE(slave->queue_id));
}
static SLAVE_ATTR_RO(queue_id);

1
drivers/net/can/cc770/Kconfig
View File

@ -7,6 +7,7 @@ if CAN_CC770
config CAN_CC770_ISA
tristate "ISA Bus based legacy CC770 driver"
depends on ISA
help
This driver adds legacy support for CC770 and AN82527 chips
connected to the ISA bus using I/O port, memory mapped or

2
drivers/net/can/dev/dev.c
View File

@ -338,7 +338,7 @@ int can_change_mtu(struct net_device *dev, int new_mtu)
return -EINVAL;
}
dev->mtu = new_mtu;
WRITE_ONCE(dev->mtu, new_mtu);
return 0;
}
EXPORT_SYMBOL_GPL(can_change_mtu);

1
drivers/net/can/sja1000/Kconfig
View File

@ -87,6 +87,7 @@ config CAN_PLX_PCI
config CAN_SJA1000_ISA
tristate "ISA Bus based legacy SJA1000 driver"
depends on ISA
help
This driver adds legacy support for SJA1000 chips connected to
the ISA bus using I/O port, memory mapped or indirect access.

2
drivers/net/can/vcan.c
View File

@ -140,7 +140,7 @@ static int vcan_change_mtu(struct net_device *dev, int new_mtu)
!can_is_canxl_dev_mtu(new_mtu))
return -EINVAL;
dev->mtu = new_mtu;
WRITE_ONCE(dev->mtu, new_mtu);
return 0;
}

2
drivers/net/can/vxcan.c
View File

@ -135,7 +135,7 @@ static int vxcan_change_mtu(struct net_device *dev, int new_mtu)
!can_is_canxl_dev_mtu(new_mtu))
return -EINVAL;
dev->mtu = new_mtu;
WRITE_ONCE(dev->mtu, new_mtu);
return 0;
}

212
drivers/net/dsa/b53/b53_common.c
View File

@ -1266,95 +1266,70 @@ static void b53_adjust_63xx_rgmii(struct dsa_switch *ds, int port,
phy_modes(interface));
}
static void b53_adjust_link(struct dsa_switch *ds, int port,
struct phy_device *phydev)
static void b53_adjust_531x5_rgmii(struct dsa_switch *ds, int port,
phy_interface_t interface)
{
struct b53_device *dev = ds->priv;
struct ethtool_keee *p = &dev->ports[port].eee;
u8 rgmii_ctrl = 0, reg = 0, off;
bool tx_pause = false;
bool rx_pause = false;
u8 rgmii_ctrl = 0, off;
if (!phy_is_pseudo_fixed_link(phydev))
return;
if (port == dev->imp_port)
off = B53_RGMII_CTRL_IMP;
else
off = B53_RGMII_CTRL_P(port);
/* Enable flow control on BCM5301x's CPU port */
if (is5301x(dev) && dsa_is_cpu_port(ds, port))
tx_pause = rx_pause = true;
/* Configure the port RGMII clock delay by DLL disabled and
* tx_clk aligned timing (restoring to reset defaults)
*/
b53_read8(dev, B53_CTRL_PAGE, off, &rgmii_ctrl);
rgmii_ctrl &= ~(RGMII_CTRL_DLL_RXC | RGMII_CTRL_DLL_TXC |
RGMII_CTRL_TIMING_SEL);
if (phydev->pause) {
if (phydev->asym_pause)
tx_pause = true;
rx_pause = true;
}
/* PHY_INTERFACE_MODE_RGMII_TXID means TX internal delay, make
* sure that we enable the port TX clock internal delay to
* account for this internal delay that is inserted, otherwise
* the switch won't be able to receive correctly.
*
* PHY_INTERFACE_MODE_RGMII means that we are not introducing
* any delay neither on transmission nor reception, so the
* BCM53125 must also be configured accordingly to account for
* the lack of delay and introduce
*
* The BCM53125 switch has its RX clock and TX clock control
* swapped, hence the reason why we modify the TX clock path in
* the "RGMII" case
*/
if (interface == PHY_INTERFACE_MODE_RGMII_TXID)
rgmii_ctrl |= RGMII_CTRL_DLL_TXC;
if (interface == PHY_INTERFACE_MODE_RGMII)
rgmii_ctrl |= RGMII_CTRL_DLL_TXC | RGMII_CTRL_DLL_RXC;
rgmii_ctrl |= RGMII_CTRL_TIMING_SEL;
b53_write8(dev, B53_CTRL_PAGE, off, rgmii_ctrl);
b53_force_port_config(dev, port, phydev->speed, phydev->duplex,
tx_pause, rx_pause);
b53_force_link(dev, port, phydev->link);
dev_info(ds->dev, "Configured port %d for %s\n", port,
phy_modes(interface));
}
if (is63xx(dev) && port >= B53_63XX_RGMII0)
b53_adjust_63xx_rgmii(ds, port, phydev->interface);
static void b53_adjust_5325_mii(struct dsa_switch *ds, int port)
{
struct b53_device *dev = ds->priv;
u8 reg = 0;
if (is531x5(dev) && phy_interface_is_rgmii(phydev)) {
if (port == dev->imp_port)
off = B53_RGMII_CTRL_IMP;
else
off = B53_RGMII_CTRL_P(port);
b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
&reg);
/* Configure the port RGMII clock delay by DLL disabled and
* tx_clk aligned timing (restoring to reset defaults)
*/
b53_read8(dev, B53_CTRL_PAGE, off, &rgmii_ctrl);
rgmii_ctrl &= ~(RGMII_CTRL_DLL_RXC | RGMII_CTRL_DLL_TXC |
RGMII_CTRL_TIMING_SEL);
/* PHY_INTERFACE_MODE_RGMII_TXID means TX internal delay, make
* sure that we enable the port TX clock internal delay to
* account for this internal delay that is inserted, otherwise
* the switch won't be able to receive correctly.
*
* PHY_INTERFACE_MODE_RGMII means that we are not introducing
* any delay neither on transmission nor reception, so the
* BCM53125 must also be configured accordingly to account for
* the lack of delay and introduce
*
* The BCM53125 switch has its RX clock and TX clock control
* swapped, hence the reason why we modify the TX clock path in
* the "RGMII" case
*/
if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
rgmii_ctrl |= RGMII_CTRL_DLL_TXC;
if (phydev->interface == PHY_INTERFACE_MODE_RGMII)
rgmii_ctrl |= RGMII_CTRL_DLL_TXC | RGMII_CTRL_DLL_RXC;
rgmii_ctrl |= RGMII_CTRL_TIMING_SEL;
b53_write8(dev, B53_CTRL_PAGE, off, rgmii_ctrl);
dev_info(ds->dev, "Configured port %d for %s\n", port,
phy_modes(phydev->interface));
}
/* configure MII port if necessary */
if (is5325(dev)) {
/* reverse mii needs to be enabled */
if (!(reg & PORT_OVERRIDE_RV_MII_25)) {
b53_write8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
reg | PORT_OVERRIDE_RV_MII_25);
b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
&reg);
/* reverse mii needs to be enabled */
if (!(reg & PORT_OVERRIDE_RV_MII_25)) {
b53_write8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
reg | PORT_OVERRIDE_RV_MII_25);
b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
&reg);
if (!(reg & PORT_OVERRIDE_RV_MII_25)) {
dev_err(ds->dev,
"Failed to enable reverse MII mode\n");
return;
}
dev_err(ds->dev,
"Failed to enable reverse MII mode\n");
return;
}
}
/* Re-negotiate EEE if it was enabled already */
p->eee_enabled = b53_eee_init(ds, port, phydev);
}
void b53_port_event(struct dsa_switch *ds, int port)
@ -1408,30 +1383,48 @@ static void b53_phylink_get_caps(struct dsa_switch *ds, int port,
dev->ops->phylink_get_caps(dev, port, config);
}
static struct phylink_pcs *b53_phylink_mac_select_pcs(struct dsa_switch *ds,
int port,
static struct phylink_pcs *b53_phylink_mac_select_pcs(struct phylink_config *config,
phy_interface_t interface)
{
struct b53_device *dev = ds->priv;
struct dsa_port *dp = dsa_phylink_to_port(config);
struct b53_device *dev = dp->ds->priv;
if (!dev->ops->phylink_mac_select_pcs)
return NULL;
return dev->ops->phylink_mac_select_pcs(dev, port, interface);
return dev->ops->phylink_mac_select_pcs(dev, dp->index, interface);
}
void b53_phylink_mac_config(struct dsa_switch *ds, int port,
unsigned int mode,
const struct phylink_link_state *state)
{
}
EXPORT_SYMBOL(b53_phylink_mac_config);
void b53_phylink_mac_link_down(struct dsa_switch *ds, int port,
unsigned int mode,
phy_interface_t interface)
static void b53_phylink_mac_config(struct phylink_config *config,
unsigned int mode,
const struct phylink_link_state *state)
{
struct dsa_port *dp = dsa_phylink_to_port(config);
phy_interface_t interface = state->interface;
struct dsa_switch *ds = dp->ds;
struct b53_device *dev = ds->priv;
int port = dp->index;
if (is63xx(dev) && port >= B53_63XX_RGMII0)
b53_adjust_63xx_rgmii(ds, port, interface);
if (mode == MLO_AN_FIXED) {
if (is531x5(dev) && phy_interface_mode_is_rgmii(interface))
b53_adjust_531x5_rgmii(ds, port, interface);
/* configure MII port if necessary */
if (is5325(dev))
b53_adjust_5325_mii(ds, port);
}
}
static void b53_phylink_mac_link_down(struct phylink_config *config,
unsigned int mode,
phy_interface_t interface)
{
struct dsa_port *dp = dsa_phylink_to_port(config);
struct b53_device *dev = dp->ds->priv;
int port = dp->index;
if (mode == MLO_AN_PHY)
return;
@ -1445,24 +1438,31 @@ void b53_phylink_mac_link_down(struct dsa_switch *ds, int port,
dev->ops->serdes_link_set)
dev->ops->serdes_link_set(dev, port, mode, interface, false);
}
EXPORT_SYMBOL(b53_phylink_mac_link_down);
void b53_phylink_mac_link_up(struct dsa_switch *ds, int port,
unsigned int mode,
phy_interface_t interface,
struct phy_device *phydev,
int speed, int duplex,
bool tx_pause, bool rx_pause)
static void b53_phylink_mac_link_up(struct phylink_config *config,
struct phy_device *phydev,
unsigned int mode,
phy_interface_t interface,
int speed, int duplex,
bool tx_pause, bool rx_pause)
{
struct dsa_port *dp = dsa_phylink_to_port(config);
struct dsa_switch *ds = dp->ds;
struct b53_device *dev = ds->priv;
struct ethtool_keee *p = &dev->ports[dp->index].eee;
int port = dp->index;
if (is63xx(dev) && port >= B53_63XX_RGMII0)
b53_adjust_63xx_rgmii(ds, port, interface);
if (mode == MLO_AN_PHY)
if (mode == MLO_AN_PHY) {
/* Re-negotiate EEE if it was enabled already */
p->eee_enabled = b53_eee_init(ds, port, phydev);
return;
}
if (mode == MLO_AN_FIXED) {
/* Force flow control on BCM5301x's CPU port */
if (is5301x(dev) && dsa_is_cpu_port(ds, port))
tx_pause = rx_pause = true;
b53_force_port_config(dev, port, speed, duplex,
tx_pause, rx_pause);
b53_force_link(dev, port, true);
@ -1473,7 +1473,6 @@ void b53_phylink_mac_link_up(struct dsa_switch *ds, int port,
dev->ops->serdes_link_set)
dev->ops->serdes_link_set(dev, port, mode, interface, true);
}
EXPORT_SYMBOL(b53_phylink_mac_link_up);
int b53_vlan_filtering(struct dsa_switch *ds, int port, bool vlan_filtering,
struct netlink_ext_ack *extack)
@ -2268,6 +2267,13 @@ static int b53_get_max_mtu(struct dsa_switch *ds, int port)
return JMS_MAX_SIZE;
}
static const struct phylink_mac_ops b53_phylink_mac_ops = {
.mac_select_pcs = b53_phylink_mac_select_pcs,
.mac_config = b53_phylink_mac_config,
.mac_link_down = b53_phylink_mac_link_down,
.mac_link_up = b53_phylink_mac_link_up,
};
static const struct dsa_switch_ops b53_switch_ops = {
.get_tag_protocol = b53_get_tag_protocol,
.setup = b53_setup,
@ -2278,12 +2284,7 @@ static const struct dsa_switch_ops b53_switch_ops = {
.get_ethtool_phy_stats = b53_get_ethtool_phy_stats,
.phy_read = b53_phy_read16,
.phy_write = b53_phy_write16,
.adjust_link = b53_adjust_link,
.phylink_get_caps = b53_phylink_get_caps,
.phylink_mac_select_pcs = b53_phylink_mac_select_pcs,
.phylink_mac_config = b53_phylink_mac_config,
.phylink_mac_link_down = b53_phylink_mac_link_down,
.phylink_mac_link_up = b53_phylink_mac_link_up,
.port_enable = b53_enable_port,
.port_disable = b53_disable_port,
.get_mac_eee = b53_get_mac_eee,
@ -2726,6 +2727,7 @@ struct b53_device *b53_switch_alloc(struct device *base,
dev->priv = priv;
dev->ops = ops;
ds->ops = &b53_switch_ops;
ds->phylink_mac_ops = &b53_phylink_mac_ops;
dev->vlan_enabled = true;
/* Let DSA handle the case were multiple bridges span the same switch
* device and different VLAN awareness settings are requested, which

12
drivers/net/dsa/b53/b53_priv.h
View File

@ -352,18 +352,6 @@ int b53_br_flags(struct dsa_switch *ds, int port,
struct netlink_ext_ack *extack);
int b53_setup_devlink_resources(struct dsa_switch *ds);
void b53_port_event(struct dsa_switch *ds, int port);
void b53_phylink_mac_config(struct dsa_switch *ds, int port,
unsigned int mode,
const struct phylink_link_state *state);
void b53_phylink_mac_link_down(struct dsa_switch *ds, int port,
unsigned int mode,
phy_interface_t interface);
void b53_phylink_mac_link_up(struct dsa_switch *ds, int port,
unsigned int mode,
phy_interface_t interface,
struct phy_device *phydev,
int speed, int duplex,
bool tx_pause, bool rx_pause);
int b53_vlan_filtering(struct dsa_switch *ds, int port, bool vlan_filtering,
struct netlink_ext_ack *extack);
int b53_vlan_add(struct dsa_switch *ds, int port,

49
drivers/net/dsa/bcm_sf2.c
View File

@ -740,16 +740,19 @@ static void bcm_sf2_sw_get_caps(struct dsa_switch *ds, int port,
MAC_10 | MAC_100 | MAC_1000;
}
static void bcm_sf2_sw_mac_config(struct dsa_switch *ds, int port,
static void bcm_sf2_sw_mac_config(struct phylink_config *config,
unsigned int mode,
const struct phylink_link_state *state)
{
struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
struct dsa_port *dp = dsa_phylink_to_port(config);
u32 id_mode_dis = 0, port_mode;
struct bcm_sf2_priv *priv;
u32 reg_rgmii_ctrl;
u32 reg;
if (port == core_readl(priv, CORE_IMP0_PRT_ID))
priv = bcm_sf2_to_priv(dp->ds);
if (dp->index == core_readl(priv, CORE_IMP0_PRT_ID))
return;
switch (state->interface) {
@ -770,7 +773,7 @@ static void bcm_sf2_sw_mac_config(struct dsa_switch *ds, int port,
return;
}
reg_rgmii_ctrl = bcm_sf2_reg_rgmii_cntrl(priv, port);
reg_rgmii_ctrl = bcm_sf2_reg_rgmii_cntrl(priv, dp->index);
/* Clear id_mode_dis bit, and the existing port mode, let
* RGMII_MODE_EN bet set by mac_link_{up,down}
@ -809,13 +812,16 @@ static void bcm_sf2_sw_mac_link_set(struct dsa_switch *ds, int port,
reg_writel(priv, reg, reg_rgmii_ctrl);
}
static void bcm_sf2_sw_mac_link_down(struct dsa_switch *ds, int port,
static void bcm_sf2_sw_mac_link_down(struct phylink_config *config,
unsigned int mode,
phy_interface_t interface)
{
struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
struct dsa_port *dp = dsa_phylink_to_port(config);
struct bcm_sf2_priv *priv;
int port = dp->index;
u32 reg, offset;
priv = bcm_sf2_to_priv(dp->ds);
if (priv->wol_ports_mask & BIT(port))
return;
@ -824,23 +830,26 @@ static void bcm_sf2_sw_mac_link_down(struct dsa_switch *ds, int port,
reg &= ~LINK_STS;
core_writel(priv, reg, offset);
bcm_sf2_sw_mac_link_set(ds, port, interface, false);
bcm_sf2_sw_mac_link_set(dp->ds, port, interface, false);
}
static void bcm_sf2_sw_mac_link_up(struct dsa_switch *ds, int port,
static void bcm_sf2_sw_mac_link_up(struct phylink_config *config,
struct phy_device *phydev,
unsigned int mode,
phy_interface_t interface,
struct phy_device *phydev,
int speed, int duplex,
bool tx_pause, bool rx_pause)
{
struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
struct ethtool_keee *p = &priv->dev->ports[port].eee;
struct dsa_port *dp = dsa_phylink_to_port(config);
struct bcm_sf2_priv *priv;
u32 reg_rgmii_ctrl = 0;
struct ethtool_keee *p;
int port = dp->index;
u32 reg, offset;
bcm_sf2_sw_mac_link_set(ds, port, interface, true);
bcm_sf2_sw_mac_link_set(dp->ds, port, interface, true);
priv = bcm_sf2_to_priv(dp->ds);
offset = bcm_sf2_port_override_offset(priv, port);
if (phy_interface_mode_is_rgmii(interface) ||
@ -886,8 +895,10 @@ static void bcm_sf2_sw_mac_link_up(struct dsa_switch *ds, int port,
core_writel(priv, reg, offset);
if (mode == MLO_AN_PHY && phydev)
p->eee_enabled = b53_eee_init(ds, port, phydev);
if (mode == MLO_AN_PHY && phydev) {
p = &priv->dev->ports[port].eee;
p->eee_enabled = b53_eee_init(dp->ds, port, phydev);
}
}
static void bcm_sf2_sw_fixed_state(struct dsa_switch *ds, int port,
@ -1196,6 +1207,12 @@ static int bcm_sf2_sw_get_sset_count(struct dsa_switch *ds, int port,
return cnt;
}
static const struct phylink_mac_ops bcm_sf2_phylink_mac_ops = {
.mac_config = bcm_sf2_sw_mac_config,
.mac_link_down = bcm_sf2_sw_mac_link_down,
.mac_link_up = bcm_sf2_sw_mac_link_up,
};
static const struct dsa_switch_ops bcm_sf2_ops = {
.get_tag_protocol = b53_get_tag_protocol,
.setup = bcm_sf2_sw_setup,
@ -1206,9 +1223,6 @@ static const struct dsa_switch_ops bcm_sf2_ops = {
.get_ethtool_phy_stats = b53_get_ethtool_phy_stats,
.get_phy_flags = bcm_sf2_sw_get_phy_flags,
.phylink_get_caps = bcm_sf2_sw_get_caps,
.phylink_mac_config = bcm_sf2_sw_mac_config,
.phylink_mac_link_down = bcm_sf2_sw_mac_link_down,
.phylink_mac_link_up = bcm_sf2_sw_mac_link_up,
.phylink_fixed_state = bcm_sf2_sw_fixed_state,
.suspend = bcm_sf2_sw_suspend,
.resume = bcm_sf2_sw_resume,
@ -1399,6 +1413,7 @@ static int bcm_sf2_sw_probe(struct platform_device *pdev)
priv->dev = dev;
ds = dev->ds;
ds->ops = &bcm_sf2_ops;
ds->phylink_mac_ops = &bcm_sf2_phylink_mac_ops;
/* Advertise the 8 egress queues */
ds->num_tx_queues = SF2_NUM_EGRESS_QUEUES;

25
drivers/net/dsa/hirschmann/hellcreek_ptp.c
View File

@ -27,7 +27,8 @@ void hellcreek_ptp_write(struct hellcreek *hellcreek, u16 data,
}
/* Get nanoseconds from PTP clock */
static u64 hellcreek_ptp_clock_read(struct hellcreek *hellcreek)
static u64 hellcreek_ptp_clock_read(struct hellcreek *hellcreek,
struct ptp_system_timestamp *sts)
{
u16 nsl, nsh;
@ -45,16 +46,19 @@ static u64 hellcreek_ptp_clock_read(struct hellcreek *hellcreek)
nsh = hellcreek_ptp_read(hellcreek, PR_SS_SYNC_DATA_C);
nsh = hellcreek_ptp_read(hellcreek, PR_SS_SYNC_DATA_C);
nsh = hellcreek_ptp_read(hellcreek, PR_SS_SYNC_DATA_C);
ptp_read_system_prets(sts);
nsl = hellcreek_ptp_read(hellcreek, PR_SS_SYNC_DATA_C);
ptp_read_system_postts(sts);
return (u64)nsl | ((u64)nsh << 16);
}
static u64 __hellcreek_ptp_gettime(struct hellcreek *hellcreek)
static u64 __hellcreek_ptp_gettime(struct hellcreek *hellcreek,
struct ptp_system_timestamp *sts)
{
u64 ns;
ns = hellcreek_ptp_clock_read(hellcreek);
ns = hellcreek_ptp_clock_read(hellcreek, sts);
if (ns < hellcreek->last_ts)
hellcreek->seconds++;
hellcreek->last_ts = ns;
@ -72,7 +76,7 @@ u64 hellcreek_ptp_gettime_seconds(struct hellcreek *hellcreek, u64 ns)
{
u64 s;
__hellcreek_ptp_gettime(hellcreek);
__hellcreek_ptp_gettime(hellcreek, NULL);
if (hellcreek->last_ts > ns)
s = hellcreek->seconds * NSEC_PER_SEC;
else
@ -81,14 +85,15 @@ u64 hellcreek_ptp_gettime_seconds(struct hellcreek *hellcreek, u64 ns)
return s;
}
static int hellcreek_ptp_gettime(struct ptp_clock_info *ptp,
struct timespec64 *ts)
static int hellcreek_ptp_gettimex(struct ptp_clock_info *ptp,
struct timespec64 *ts,
struct ptp_system_timestamp *sts)
{
struct hellcreek *hellcreek = ptp_to_hellcreek(ptp);
u64 ns;
mutex_lock(&hellcreek->ptp_lock);
ns = __hellcreek_ptp_gettime(hellcreek);
ns = __hellcreek_ptp_gettime(hellcreek, sts);
mutex_unlock(&hellcreek->ptp_lock);
*ts = ns_to_timespec64(ns);
@ -184,7 +189,7 @@ static int hellcreek_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta)
if (abs(delta) > MAX_SLOW_OFFSET_ADJ) {
struct timespec64 now, then = ns_to_timespec64(delta);
hellcreek_ptp_gettime(ptp, &now);
hellcreek_ptp_gettimex(ptp, &now, NULL);
now = timespec64_add(now, then);
hellcreek_ptp_settime(ptp, &now);
@ -233,7 +238,7 @@ static void hellcreek_ptp_overflow_check(struct work_struct *work)
hellcreek = dw_overflow_to_hellcreek(dw);
mutex_lock(&hellcreek->ptp_lock);
__hellcreek_ptp_gettime(hellcreek);
__hellcreek_ptp_gettime(hellcreek, NULL);
mutex_unlock(&hellcreek->ptp_lock);
schedule_delayed_work(&hellcreek->overflow_work,
@ -409,7 +414,7 @@ int hellcreek_ptp_setup(struct hellcreek *hellcreek)
hellcreek->ptp_clock_info.pps = 0;
hellcreek->ptp_clock_info.adjfine = hellcreek_ptp_adjfine;
hellcreek->ptp_clock_info.adjtime = hellcreek_ptp_adjtime;
hellcreek->ptp_clock_info.gettime64 = hellcreek_ptp_gettime;
hellcreek->ptp_clock_info.gettimex64 = hellcreek_ptp_gettimex;
hellcreek->ptp_clock_info.settime64 = hellcreek_ptp_settime;
hellcreek->ptp_clock_info.enable = hellcreek_ptp_enable;
hellcreek->ptp_clock_info.do_aux_work = hellcreek_hwtstamp_work;

38
drivers/net/dsa/lan9303-core.c
View File

@ -1007,15 +1007,14 @@ static const struct lan9303_mib_desc lan9303_mib[] = {
static void lan9303_get_strings(struct dsa_switch *ds, int port,
u32 stringset, uint8_t *data)
{
u8 *buf = data;
unsigned int u;
if (stringset != ETH_SS_STATS)
return;
for (u = 0; u < ARRAY_SIZE(lan9303_mib); u++) {
strncpy(data + u * ETH_GSTRING_LEN, lan9303_mib[u].name,
ETH_GSTRING_LEN);
}
for (u = 0; u < ARRAY_SIZE(lan9303_mib); u++)
ethtool_puts(&buf, lan9303_mib[u].name);
}
static void lan9303_get_ethtool_stats(struct dsa_switch *ds, int port,
@ -1293,14 +1292,29 @@ static void lan9303_phylink_get_caps(struct dsa_switch *ds, int port,
}
}
static void lan9303_phylink_mac_link_up(struct dsa_switch *ds, int port,
static void lan9303_phylink_mac_config(struct phylink_config *config,
unsigned int mode,
const struct phylink_link_state *state)
{
}
static void lan9303_phylink_mac_link_down(struct phylink_config *config,
unsigned int mode,
phy_interface_t interface)
{
}
static void lan9303_phylink_mac_link_up(struct phylink_config *config,
struct phy_device *phydev,
unsigned int mode,
phy_interface_t interface,
struct phy_device *phydev, int speed,
int duplex, bool tx_pause,
int speed, int duplex, bool tx_pause,
bool rx_pause)
{
struct lan9303 *chip = ds->priv;
struct dsa_port *dp = dsa_phylink_to_port(config);
struct lan9303 *chip = dp->ds->priv;
struct dsa_switch *ds = dp->ds;
int port = dp->index;
u32 ctl;
u32 reg;
@ -1330,6 +1344,12 @@ static void lan9303_phylink_mac_link_up(struct dsa_switch *ds, int port,
regmap_write(chip->regmap, flow_ctl_reg[port], reg);
}
static const struct phylink_mac_ops lan9303_phylink_mac_ops = {
.mac_config = lan9303_phylink_mac_config,
.mac_link_down = lan9303_phylink_mac_link_down,
.mac_link_up = lan9303_phylink_mac_link_up,
};
static const struct dsa_switch_ops lan9303_switch_ops = {
.get_tag_protocol = lan9303_get_tag_protocol,
.setup = lan9303_setup,
@ -1337,7 +1357,6 @@ static const struct dsa_switch_ops lan9303_switch_ops = {
.phy_read = lan9303_phy_read,
.phy_write = lan9303_phy_write,
.phylink_get_caps = lan9303_phylink_get_caps,
.phylink_mac_link_up = lan9303_phylink_mac_link_up,
.get_ethtool_stats = lan9303_get_ethtool_stats,
.get_sset_count = lan9303_get_sset_count,
.port_enable = lan9303_port_enable,
@ -1365,6 +1384,7 @@ static int lan9303_register_switch(struct lan9303 *chip)
chip->ds->num_ports = LAN9303_NUM_PORTS;
chip->ds->priv = chip;
chip->ds->ops = &lan9303_switch_ops;
chip->ds->phylink_mac_ops = &lan9303_phylink_mac_ops;
base = chip->phy_addr_base;
chip->ds->phys_mii_mask = GENMASK(LAN9303_NUM_PORTS - 1 + base, base);

39
drivers/net/dsa/lantiq_gswip.c
View File

@ -1670,11 +1670,13 @@ static void gswip_port_set_pause(struct gswip_priv *priv, int port,
mdio_phy, GSWIP_MDIO_PHYp(port));
}
static void gswip_phylink_mac_config(struct dsa_switch *ds, int port,
static void gswip_phylink_mac_config(struct phylink_config *config,
unsigned int mode,
const struct phylink_link_state *state)
{
struct gswip_priv *priv = ds->priv;
struct dsa_port *dp = dsa_phylink_to_port(config);
struct gswip_priv *priv = dp->ds->priv;
int port = dp->index;
u32 miicfg = 0;
miicfg |= GSWIP_MII_CFG_LDCLKDIS;
@ -1700,7 +1702,7 @@ static void gswip_phylink_mac_config(struct dsa_switch *ds, int port,
miicfg |= GSWIP_MII_CFG_MODE_GMII;
break;
default:
dev_err(ds->dev,
dev_err(dp->ds->dev,
"Unsupported interface: %d\n", state->interface);
return;
}
@ -1726,28 +1728,32 @@ static void gswip_phylink_mac_config(struct dsa_switch *ds, int port,
}
}
static void gswip_phylink_mac_link_down(struct dsa_switch *ds, int port,
static void gswip_phylink_mac_link_down(struct phylink_config *config,
unsigned int mode,
phy_interface_t interface)
{
struct gswip_priv *priv = ds->priv;
struct dsa_port *dp = dsa_phylink_to_port(config);
struct gswip_priv *priv = dp->ds->priv;
int port = dp->index;
gswip_mii_mask_cfg(priv, GSWIP_MII_CFG_EN, 0, port);
if (!dsa_is_cpu_port(ds, port))
if (!dsa_port_is_cpu(dp))
gswip_port_set_link(priv, port, false);
}
static void gswip_phylink_mac_link_up(struct dsa_switch *ds, int port,
static void gswip_phylink_mac_link_up(struct phylink_config *config,
struct phy_device *phydev,
unsigned int mode,
phy_interface_t interface,
struct phy_device *phydev,
int speed, int duplex,
bool tx_pause, bool rx_pause)
{
struct gswip_priv *priv = ds->priv;
struct dsa_port *dp = dsa_phylink_to_port(config);
struct gswip_priv *priv = dp->ds->priv;
int port = dp->index;
if (!dsa_is_cpu_port(ds, port)) {
if (!dsa_port_is_cpu(dp)) {
gswip_port_set_link(priv, port, true);
gswip_port_set_speed(priv, port, speed, interface);
gswip_port_set_duplex(priv, port, duplex);
@ -1824,6 +1830,12 @@ static int gswip_get_sset_count(struct dsa_switch *ds, int port, int sset)
return ARRAY_SIZE(gswip_rmon_cnt);
}
static const struct phylink_mac_ops gswip_phylink_mac_ops = {
.mac_config = gswip_phylink_mac_config,
.mac_link_down = gswip_phylink_mac_link_down,
.mac_link_up = gswip_phylink_mac_link_up,
};
static const struct dsa_switch_ops gswip_xrx200_switch_ops = {
.get_tag_protocol = gswip_get_tag_protocol,
.setup = gswip_setup,
@ -1842,9 +1854,6 @@ static const struct dsa_switch_ops gswip_xrx200_switch_ops = {
.port_change_mtu = gswip_port_change_mtu,
.port_max_mtu = gswip_port_max_mtu,
.phylink_get_caps = gswip_xrx200_phylink_get_caps,
.phylink_mac_config = gswip_phylink_mac_config,
.phylink_mac_link_down = gswip_phylink_mac_link_down,
.phylink_mac_link_up = gswip_phylink_mac_link_up,
.get_strings = gswip_get_strings,
.get_ethtool_stats = gswip_get_ethtool_stats,
.get_sset_count = gswip_get_sset_count,
@ -1868,9 +1877,6 @@ static const struct dsa_switch_ops gswip_xrx300_switch_ops = {
.port_change_mtu = gswip_port_change_mtu,
.port_max_mtu = gswip_port_max_mtu,
.phylink_get_caps = gswip_xrx300_phylink_get_caps,
.phylink_mac_config = gswip_phylink_mac_config,
.phylink_mac_link_down = gswip_phylink_mac_link_down,
.phylink_mac_link_up = gswip_phylink_mac_link_up,
.get_strings = gswip_get_strings,
.get_ethtool_stats = gswip_get_ethtool_stats,
.get_sset_count = gswip_get_sset_count,
@ -2136,6 +2142,7 @@ static int gswip_probe(struct platform_device *pdev)
priv->ds->num_ports = priv->hw_info->max_ports;
priv->ds->priv = priv;
priv->ds->ops = priv->hw_info->ops;
priv->ds->phylink_mac_ops = &gswip_phylink_mac_ops;
priv->dev = dev;
mutex_init(&priv->pce_table_lock);
version = gswip_switch_r(priv, GSWIP_VERSION);

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