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- stm32: race fix by adding a spinlock
- mhu: trim included headers - omap: add support for K3 SoCs - imx: Irq disable fix - bcm: tidy up extracting driver data - tegra: make resume 'noirq' - api: fix error handling -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEE6EwehDt/SOnwFyTyf9lkf8eYP5UFAl0qaioACgkQf9lkf8eY P5VT2Q//WJPFy/aB12RGN4hOrF2dLmk92AEWVDQDifbEbvKXOSJo9Qk8ebUgfPiG U3bjnYjvFm9b64yaFCw3PRvu52jPa/oMCUHgyi/cbqzbKQmTonmCaU/E60RCHukR 3A3aQR59cLxxt+WM7Gb36USPZkF6E4x7WJx7xPGLclkeXlcuqCDYZ77K+R3WGUPI gldCwF6cNxmimLHm9WGwkA9hw4aE/h4U4Nu2MJn5VPNSKU93GfAJ7X59SMzn93tO dbUODDYYwvUSn6voXbrvICe1Z+a9xCTLj9bS0NIM8ND3zlfZeuvogCIlwt5fLmOb 365rMMr0xyVLBokBBJVFvqqv8rX5z+XHbGzrWYB6hErmQH3rnzWIuauiN7ic5Pn8 ml8gLYpeJzUt2fRiW8mNR/AMjpLOsQOrVOrUfT7I2MKNTv4t0aiEXhIxaqesZjot NAifa9jUZ4OMgdt+Q53aoJCvuZwEN+9lOCKRQ/UmKArQVJkAdoX2yoVwMYfSMkr1 X8rPX5VJ1HrP8yQtXO4LK4y+D7l7TERatG5XYBXWJV6Sv7u6Xq1XX2LGv/O5NWBy YGRwzBkIlxK6WnVhg/xwoZnoRmXpTnQlG86d6H2XkzQJrt0VxvFz8QXulH665lNe dfEBSMEVnk7FBj3zpgW+kvpUfsdpUkEjeK3W4iIOlQAYjYuIQ24= =ZkSQ -----END PGP SIGNATURE----- Merge tag 'mailbox-v5.3' of git://git.linaro.org/landing-teams/working/fujitsu/integration Pull mailbox updates from Jassi Brar: - stm32: race fix by adding a spinlock - mhu: trim included headers - omap: add support for K3 SoCs - imx: Irq disable fix - bcm: tidy up extracting driver data - tegra: make resume 'noirq' - api: fix error handling * tag 'mailbox-v5.3' of git://git.linaro.org/landing-teams/working/fujitsu/integration: mailbox: handle failed named mailbox channel request mailbox: tegra: avoid resume NULL mailboxes mailbox: tegra: hsp: add noirq resume mailbox: bcm-flexrm-mailbox: using dev_get_drvdata directly mailbox: imx: Clear GIEn bit at shutdown mailbox: omap: Add support for TI K3 SoCs dt-bindings: mailbox: omap: Update bindings for TI K3 SoCs mailbox: arm_mhu: reorder header inclusion and drop unneeded ones mailbox: stm32_ipcc: add spinlock to fix channels concurrent access
This commit is contained in:
Linus Torvalds
commit
fde7dc63b1
@ -1,4 +1,4 @@
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OMAP2+ Mailbox Driver
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OMAP2+ and K3 Mailbox
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=====================
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The OMAP mailbox hardware facilitates communication between different processors
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@ -7,7 +7,7 @@ various processor subsystems and is connected on an interconnect bus. The
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communication is achieved through a set of registers for message storage and
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interrupt configuration registers.
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Each mailbox IP block has a certain number of h/w fifo queues and output
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Each mailbox IP block/cluster has a certain number of h/w fifo queues and output
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interrupt lines. An output interrupt line is routed to an interrupt controller
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within a processor subsystem, and there can be more than one line going to a
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specific processor's interrupt controller. The interrupt line connections are
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@ -23,12 +23,16 @@ All the current OMAP SoCs except for the newest DRA7xx SoC has a single IP
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instance. DRA7xx has multiple instances with different number of h/w fifo queues
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and interrupt lines between different instances. The interrupt lines can also be
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routed to different processor sub-systems on DRA7xx as they are routed through
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the Crossbar, a kind of interrupt router/multiplexer.
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the Crossbar, a kind of interrupt router/multiplexer. The K3 AM65x and J721E
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SoCs has each of these instances form a cluster and combine multiple clusters
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into a single IP block present within the Main NavSS. The interrupt lines from
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all these clusters are multiplexed and routed to different processor subsystems
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over a limited number of common interrupt output lines of an Interrupt Router.
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Mailbox Device Node:
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====================
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A Mailbox device node is used to represent a Mailbox IP instance within a SoC.
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The sub-mailboxes are represented as child nodes of this parent node.
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A Mailbox device node is used to represent a Mailbox IP instance/cluster within
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a SoC. The sub-mailboxes are represented as child nodes of this parent node.
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Required properties:
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--------------------
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@ -37,12 +41,12 @@ Required properties:
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"ti,omap3-mailbox" for OMAP3430, OMAP3630 SoCs
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"ti,omap4-mailbox" for OMAP44xx, OMAP54xx, AM33xx,
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AM43xx and DRA7xx SoCs
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"ti,am654-mailbox" for K3 AM65x and J721E SoCs
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- reg: Contains the mailbox register address range (base
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address and length)
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- interrupts: Contains the interrupt information for the mailbox
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device. The format is dependent on which interrupt
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controller the OMAP device uses
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- ti,hwmods: Name of the hwmod associated with the mailbox
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controller the Mailbox device uses
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- #mbox-cells: Common mailbox binding property to identify the number
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of cells required for the mailbox specifier. Should be
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1
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@ -50,6 +54,23 @@ Required properties:
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device can interrupt
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- ti,mbox-num-fifos: Number of h/w fifo queues within the mailbox IP block
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SoC-specific Required properties:
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---------------------------------
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The following are mandatory properties for the OMAP architecture based SoCs
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only:
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- ti,hwmods: Name of the hwmod associated with the mailbox. This
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should be defined in the mailbox node only if the node
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is not defined as a child node of a corresponding sysc
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interconnect node.
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The following are mandatory properties for the K3 AM65x and J721E SoCs only:
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- interrupt-parent: Should contain a phandle to the TI-SCI interrupt
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controller node that is used to dynamically program
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the interrupt routes between the IP and the main GIC
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controllers. See the following binding for additional
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details,
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Documentation/devicetree/bindings/interrupt-controller/ti,sci-intr.txt
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Child Nodes:
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============
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A child node is used for representing the actual sub-mailbox device that is
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@ -98,7 +119,7 @@ to be used by the client user.
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Example:
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--------
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/* OMAP4 */
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1. /* OMAP4 */
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mailbox: mailbox@4a0f4000 {
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compatible = "ti,omap4-mailbox";
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reg = <0x4a0f4000 0x200>;
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@ -123,7 +144,7 @@ dsp {
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...
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};
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/* AM33xx */
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2. /* AM33xx */
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mailbox: mailbox@480c8000 {
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compatible = "ti,omap4-mailbox";
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reg = <0x480C8000 0x200>;
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@ -137,3 +158,23 @@ mailbox: mailbox@480c8000 {
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ti,mbox-rx = <0 0 3>;
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};
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};
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3. /* AM65x */
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&cbass_main {
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cbass_main_navss: interconnect0 {
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mailbox0_cluster0: mailbox@31f80000 {
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compatible = "ti,am654-mailbox";
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reg = <0x00 0x31f80000 0x00 0x200>;
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#mbox-cells = <1>;
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ti,mbox-num-users = <4>;
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ti,mbox-num-fifos = <16>;
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interrupt-parent = <&intr_main_navss>;
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interrupts = <164 0>;
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mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
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ti,mbox-tx = <1 0 0>;
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ti,mbox-rx = <0 0 0>;
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};
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};
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};
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};
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@ -54,7 +54,7 @@ config ARMADA_37XX_RWTM_MBOX
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config OMAP2PLUS_MBOX
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tristate "OMAP2+ Mailbox framework support"
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depends on ARCH_OMAP2PLUS
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depends on ARCH_OMAP2PLUS || ARCH_K3
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help
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Mailbox implementation for OMAP family chips with hardware for
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interprocessor communication involving DSP, IVA1.0 and IVA2 in
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@ -5,16 +5,13 @@
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* Author: Jassi Brar <jaswinder.singh@linaro.org>
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*/
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#include <linux/interrupt.h>
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#include <linux/spinlock.h>
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#include <linux/mutex.h>
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#include <linux/delay.h>
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#include <linux/slab.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/amba/bus.h>
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#include <linux/device.h>
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#include <linux/err.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/mailbox_controller.h>
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#include <linux/module.h>
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#define INTR_STAT_OFS 0x0
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#define INTR_SET_OFS 0x8
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@ -1163,8 +1163,7 @@ static int flexrm_process_completions(struct flexrm_ring *ring)
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static int flexrm_debugfs_conf_show(struct seq_file *file, void *offset)
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{
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struct platform_device *pdev = to_platform_device(file->private);
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struct flexrm_mbox *mbox = platform_get_drvdata(pdev);
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struct flexrm_mbox *mbox = dev_get_drvdata(file->private);
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/* Write config in file */
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flexrm_write_config_in_seqfile(mbox, file);
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@ -1174,8 +1173,7 @@ static int flexrm_debugfs_conf_show(struct seq_file *file, void *offset)
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static int flexrm_debugfs_stats_show(struct seq_file *file, void *offset)
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{
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struct platform_device *pdev = to_platform_device(file->private);
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struct flexrm_mbox *mbox = platform_get_drvdata(pdev);
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struct flexrm_mbox *mbox = dev_get_drvdata(file->private);
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/* Write stats in file */
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flexrm_write_stats_in_seqfile(mbox, file);
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@ -217,8 +217,8 @@ static void imx_mu_shutdown(struct mbox_chan *chan)
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if (cp->type == IMX_MU_TYPE_TXDB)
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tasklet_kill(&cp->txdb_tasklet);
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imx_mu_xcr_rmw(priv, 0,
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IMX_MU_xCR_TIEn(cp->idx) | IMX_MU_xCR_RIEn(cp->idx));
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imx_mu_xcr_rmw(priv, 0, IMX_MU_xCR_TIEn(cp->idx) |
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IMX_MU_xCR_RIEn(cp->idx) | IMX_MU_xCR_GIEn(cp->idx));
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free_irq(priv->irq, chan);
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}
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@ -418,11 +418,13 @@ struct mbox_chan *mbox_request_channel_byname(struct mbox_client *cl,
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of_property_for_each_string(np, "mbox-names", prop, mbox_name) {
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if (!strncmp(name, mbox_name, strlen(name)))
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break;
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return mbox_request_channel(cl, index);
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index++;
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}
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return mbox_request_channel(cl, index);
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dev_err(cl->dev, "%s() could not locate channel named \"%s\"\n",
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__func__, name);
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return ERR_PTR(-EINVAL);
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}
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EXPORT_SYMBOL_GPL(mbox_request_channel_byname);
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@ -3,7 +3,7 @@
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* OMAP mailbox driver
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*
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* Copyright (C) 2006-2009 Nokia Corporation. All rights reserved.
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* Copyright (C) 2013-2016 Texas Instruments Incorporated - http://www.ti.com
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* Copyright (C) 2013-2019 Texas Instruments Incorporated - http://www.ti.com
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*
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* Contact: Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
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* Suman Anna <s-anna@ti.com>
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@ -141,14 +141,14 @@ void mbox_write_reg(struct omap_mbox_device *mdev, u32 val, size_t ofs)
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}
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/* Mailbox FIFO handle functions */
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static mbox_msg_t mbox_fifo_read(struct omap_mbox *mbox)
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static u32 mbox_fifo_read(struct omap_mbox *mbox)
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{
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struct omap_mbox_fifo *fifo = &mbox->rx_fifo;
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return (mbox_msg_t)mbox_read_reg(mbox->parent, fifo->msg);
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return mbox_read_reg(mbox->parent, fifo->msg);
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}
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static void mbox_fifo_write(struct omap_mbox *mbox, mbox_msg_t msg)
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static void mbox_fifo_write(struct omap_mbox *mbox, u32 msg)
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{
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struct omap_mbox_fifo *fifo = &mbox->tx_fifo;
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@ -256,14 +256,16 @@ static void mbox_rx_work(struct work_struct *work)
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{
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struct omap_mbox_queue *mq =
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container_of(work, struct omap_mbox_queue, work);
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mbox_msg_t msg;
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mbox_msg_t data;
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u32 msg;
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int len;
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while (kfifo_len(&mq->fifo) >= sizeof(msg)) {
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len = kfifo_out(&mq->fifo, (unsigned char *)&msg, sizeof(msg));
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WARN_ON(len != sizeof(msg));
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data = msg;
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mbox_chan_received_data(mq->mbox->chan, (void *)msg);
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mbox_chan_received_data(mq->mbox->chan, (void *)data);
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spin_lock_irq(&mq->lock);
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if (mq->full) {
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mq->full = false;
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@ -286,7 +288,7 @@ static void __mbox_tx_interrupt(struct omap_mbox *mbox)
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static void __mbox_rx_interrupt(struct omap_mbox *mbox)
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{
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struct omap_mbox_queue *mq = mbox->rxq;
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mbox_msg_t msg;
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u32 msg;
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int len;
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while (!mbox_fifo_empty(mbox)) {
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@ -540,13 +542,13 @@ static void omap_mbox_chan_shutdown(struct mbox_chan *chan)
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mutex_unlock(&mdev->cfg_lock);
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}
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static int omap_mbox_chan_send_noirq(struct omap_mbox *mbox, void *data)
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static int omap_mbox_chan_send_noirq(struct omap_mbox *mbox, u32 msg)
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{
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int ret = -EBUSY;
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if (!mbox_fifo_full(mbox)) {
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_omap_mbox_enable_irq(mbox, IRQ_RX);
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mbox_fifo_write(mbox, (mbox_msg_t)data);
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mbox_fifo_write(mbox, msg);
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ret = 0;
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_omap_mbox_disable_irq(mbox, IRQ_RX);
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@ -558,12 +560,12 @@ static int omap_mbox_chan_send_noirq(struct omap_mbox *mbox, void *data)
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return ret;
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}
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static int omap_mbox_chan_send(struct omap_mbox *mbox, void *data)
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static int omap_mbox_chan_send(struct omap_mbox *mbox, u32 msg)
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{
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int ret = -EBUSY;
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if (!mbox_fifo_full(mbox)) {
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mbox_fifo_write(mbox, (mbox_msg_t)data);
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mbox_fifo_write(mbox, msg);
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ret = 0;
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}
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@ -576,14 +578,15 @@ static int omap_mbox_chan_send_data(struct mbox_chan *chan, void *data)
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{
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struct omap_mbox *mbox = mbox_chan_to_omap_mbox(chan);
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int ret;
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u32 msg = omap_mbox_message(data);
|
||||
|
||||
if (!mbox)
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||||
return -EINVAL;
|
||||
|
||||
if (mbox->send_no_irq)
|
||||
ret = omap_mbox_chan_send_noirq(mbox, data);
|
||||
ret = omap_mbox_chan_send_noirq(mbox, msg);
|
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else
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ret = omap_mbox_chan_send(mbox, data);
|
||||
ret = omap_mbox_chan_send(mbox, msg);
|
||||
|
||||
return ret;
|
||||
}
|
||||
@ -656,6 +659,10 @@ static const struct of_device_id omap_mailbox_of_match[] = {
|
||||
.compatible = "ti,omap4-mailbox",
|
||||
.data = &omap4_data,
|
||||
},
|
||||
{
|
||||
.compatible = "ti,am654-mailbox",
|
||||
.data = &omap4_data,
|
||||
},
|
||||
{
|
||||
/* end */
|
||||
},
|
||||
@ -830,7 +837,10 @@ static int omap_mbox_probe(struct platform_device *pdev)
|
||||
mdev->intr_type = intr_type;
|
||||
mdev->mboxes = list;
|
||||
|
||||
/* OMAP does not have a Tx-Done IRQ, but rather a Tx-Ready IRQ */
|
||||
/*
|
||||
* OMAP/K3 Mailbox IP does not have a Tx-Done IRQ, but rather a Tx-Ready
|
||||
* IRQ and is needed to run the Tx state machine
|
||||
*/
|
||||
mdev->controller.txdone_irq = true;
|
||||
mdev->controller.dev = mdev->dev;
|
||||
mdev->controller.ops = &omap_mbox_chan_ops;
|
||||
@ -899,9 +909,8 @@ static int __init omap_mbox_init(void)
|
||||
return err;
|
||||
|
||||
/* kfifo size sanity check: alignment and minimal size */
|
||||
mbox_kfifo_size = ALIGN(mbox_kfifo_size, sizeof(mbox_msg_t));
|
||||
mbox_kfifo_size = max_t(unsigned int, mbox_kfifo_size,
|
||||
sizeof(mbox_msg_t));
|
||||
mbox_kfifo_size = ALIGN(mbox_kfifo_size, sizeof(u32));
|
||||
mbox_kfifo_size = max_t(unsigned int, mbox_kfifo_size, sizeof(u32));
|
||||
|
||||
err = platform_driver_register(&omap_mbox_driver);
|
||||
if (err)
|
||||
|
||||
@ -50,6 +50,7 @@ struct stm32_ipcc {
|
||||
void __iomem *reg_base;
|
||||
void __iomem *reg_proc;
|
||||
struct clk *clk;
|
||||
spinlock_t lock; /* protect access to IPCC registers */
|
||||
int irqs[IPCC_IRQ_NUM];
|
||||
int wkp;
|
||||
u32 proc_id;
|
||||
@ -58,14 +59,24 @@ struct stm32_ipcc {
|
||||
u32 xmr;
|
||||
};
|
||||
|
||||
static inline void stm32_ipcc_set_bits(void __iomem *reg, u32 mask)
|
||||
static inline void stm32_ipcc_set_bits(spinlock_t *lock, void __iomem *reg,
|
||||
u32 mask)
|
||||
{
|
||||
unsigned long flags;
|
||||
|
||||
spin_lock_irqsave(lock, flags);
|
||||
writel_relaxed(readl_relaxed(reg) | mask, reg);
|
||||
spin_unlock_irqrestore(lock, flags);
|
||||
}
|
||||
|
||||
static inline void stm32_ipcc_clr_bits(void __iomem *reg, u32 mask)
|
||||
static inline void stm32_ipcc_clr_bits(spinlock_t *lock, void __iomem *reg,
|
||||
u32 mask)
|
||||
{
|
||||
unsigned long flags;
|
||||
|
||||
spin_lock_irqsave(lock, flags);
|
||||
writel_relaxed(readl_relaxed(reg) & ~mask, reg);
|
||||
spin_unlock_irqrestore(lock, flags);
|
||||
}
|
||||
|
||||
static irqreturn_t stm32_ipcc_rx_irq(int irq, void *data)
|
||||
@ -92,7 +103,7 @@ static irqreturn_t stm32_ipcc_rx_irq(int irq, void *data)
|
||||
|
||||
mbox_chan_received_data(&ipcc->controller.chans[chan], NULL);
|
||||
|
||||
stm32_ipcc_set_bits(ipcc->reg_proc + IPCC_XSCR,
|
||||
stm32_ipcc_set_bits(&ipcc->lock, ipcc->reg_proc + IPCC_XSCR,
|
||||
RX_BIT_CHAN(chan));
|
||||
|
||||
ret = IRQ_HANDLED;
|
||||
@ -121,7 +132,7 @@ static irqreturn_t stm32_ipcc_tx_irq(int irq, void *data)
|
||||
dev_dbg(dev, "%s: chan:%d tx\n", __func__, chan);
|
||||
|
||||
/* mask 'tx channel free' interrupt */
|
||||
stm32_ipcc_set_bits(ipcc->reg_proc + IPCC_XMR,
|
||||
stm32_ipcc_set_bits(&ipcc->lock, ipcc->reg_proc + IPCC_XMR,
|
||||
TX_BIT_CHAN(chan));
|
||||
|
||||
mbox_chan_txdone(&ipcc->controller.chans[chan], 0);
|
||||
@ -141,10 +152,12 @@ static int stm32_ipcc_send_data(struct mbox_chan *link, void *data)
|
||||
dev_dbg(ipcc->controller.dev, "%s: chan:%d\n", __func__, chan);
|
||||
|
||||
/* set channel n occupied */
|
||||
stm32_ipcc_set_bits(ipcc->reg_proc + IPCC_XSCR, TX_BIT_CHAN(chan));
|
||||
stm32_ipcc_set_bits(&ipcc->lock, ipcc->reg_proc + IPCC_XSCR,
|
||||
TX_BIT_CHAN(chan));
|
||||
|
||||
/* unmask 'tx channel free' interrupt */
|
||||
stm32_ipcc_clr_bits(ipcc->reg_proc + IPCC_XMR, TX_BIT_CHAN(chan));
|
||||
stm32_ipcc_clr_bits(&ipcc->lock, ipcc->reg_proc + IPCC_XMR,
|
||||
TX_BIT_CHAN(chan));
|
||||
|
||||
return 0;
|
||||
}
|
||||
@ -163,7 +176,8 @@ static int stm32_ipcc_startup(struct mbox_chan *link)
|
||||
}
|
||||
|
||||
/* unmask 'rx channel occupied' interrupt */
|
||||
stm32_ipcc_clr_bits(ipcc->reg_proc + IPCC_XMR, RX_BIT_CHAN(chan));
|
||||
stm32_ipcc_clr_bits(&ipcc->lock, ipcc->reg_proc + IPCC_XMR,
|
||||
RX_BIT_CHAN(chan));
|
||||
|
||||
return 0;
|
||||
}
|
||||
@ -175,7 +189,7 @@ static void stm32_ipcc_shutdown(struct mbox_chan *link)
|
||||
controller);
|
||||
|
||||
/* mask rx/tx interrupt */
|
||||
stm32_ipcc_set_bits(ipcc->reg_proc + IPCC_XMR,
|
||||
stm32_ipcc_set_bits(&ipcc->lock, ipcc->reg_proc + IPCC_XMR,
|
||||
RX_BIT_CHAN(chan) | TX_BIT_CHAN(chan));
|
||||
|
||||
clk_disable_unprepare(ipcc->clk);
|
||||
@ -208,6 +222,8 @@ static int stm32_ipcc_probe(struct platform_device *pdev)
|
||||
if (!ipcc)
|
||||
return -ENOMEM;
|
||||
|
||||
spin_lock_init(&ipcc->lock);
|
||||
|
||||
/* proc_id */
|
||||
if (of_property_read_u32(np, "st,proc-id", &ipcc->proc_id)) {
|
||||
dev_err(dev, "Missing st,proc-id\n");
|
||||
@ -259,9 +275,10 @@ static int stm32_ipcc_probe(struct platform_device *pdev)
|
||||
}
|
||||
|
||||
/* mask and enable rx/tx irq */
|
||||
stm32_ipcc_set_bits(ipcc->reg_proc + IPCC_XMR,
|
||||
stm32_ipcc_set_bits(&ipcc->lock, ipcc->reg_proc + IPCC_XMR,
|
||||
RX_BIT_MASK | TX_BIT_MASK);
|
||||
stm32_ipcc_set_bits(ipcc->reg_proc + IPCC_XCR, XCR_RXOIE | XCR_TXOIE);
|
||||
stm32_ipcc_set_bits(&ipcc->lock, ipcc->reg_proc + IPCC_XCR,
|
||||
XCR_RXOIE | XCR_TXOIE);
|
||||
|
||||
/* wakeup */
|
||||
if (of_property_read_bool(np, "wakeup-source")) {
|
||||
|
||||
@ -775,18 +775,28 @@ static int __maybe_unused tegra_hsp_resume(struct device *dev)
|
||||
{
|
||||
struct tegra_hsp *hsp = dev_get_drvdata(dev);
|
||||
unsigned int i;
|
||||
struct tegra_hsp_doorbell *db;
|
||||
|
||||
for (i = 0; i < hsp->num_sm; i++) {
|
||||
struct tegra_hsp_mailbox *mb = &hsp->mailboxes[i];
|
||||
list_for_each_entry(db, &hsp->doorbells, list) {
|
||||
if (db && db->channel.chan)
|
||||
tegra_hsp_doorbell_startup(db->channel.chan);
|
||||
}
|
||||
|
||||
if (mb->channel.chan->cl)
|
||||
tegra_hsp_mailbox_startup(mb->channel.chan);
|
||||
if (hsp->mailboxes) {
|
||||
for (i = 0; i < hsp->num_sm; i++) {
|
||||
struct tegra_hsp_mailbox *mb = &hsp->mailboxes[i];
|
||||
|
||||
if (mb->channel.chan->cl)
|
||||
tegra_hsp_mailbox_startup(mb->channel.chan);
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static SIMPLE_DEV_PM_OPS(tegra_hsp_pm_ops, NULL, tegra_hsp_resume);
|
||||
static const struct dev_pm_ops tegra_hsp_pm_ops = {
|
||||
.resume_noirq = tegra_hsp_resume,
|
||||
};
|
||||
|
||||
static const struct tegra_hsp_db_map tegra186_hsp_db_map[] = {
|
||||
{ "ccplex", TEGRA_HSP_DB_MASTER_CCPLEX, HSP_DB_CCPLEX, },
|
||||
|
||||
@ -6,7 +6,9 @@
|
||||
#ifndef OMAP_MAILBOX_H
|
||||
#define OMAP_MAILBOX_H
|
||||
|
||||
typedef u32 mbox_msg_t;
|
||||
typedef uintptr_t mbox_msg_t;
|
||||
|
||||
#define omap_mbox_message(data) (u32)(mbox_msg_t)(data)
|
||||
|
||||
typedef int __bitwise omap_mbox_irq_t;
|
||||
#define IRQ_TX ((__force omap_mbox_irq_t) 1)
|
||||
|
||||
Loading…
Reference in New Issue
Block a user