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hwmon: (k10temp) Display up to eight sets of CCD temperatures
In HWiNFO, we see support for Tccd1, Tccd3, Tccd5, and Tccd7 temperature
sensors on Zen2 based Threadripper CPUs. Checking register maps on
Threadripper 3970X confirms SMN register addresses and values for those
sensors.
Register values observed in an idle system:
0x059950: 00000000 00000abc 00000000 00000ad8
0x059960: 00000000 00000ade 00000000 00000ae4
Under load:
0x059950: 00000000 00000c02 00000000 00000c14
0x059960: 00000000 00000c30 00000000 00000c22
More analysis shows that EPYC CPUs support up to 8 CCD temperature
sensors. EPYC 7601 supports three CCD temperature sensors. Unlike
Zen2 CPUs, the register space in Zen1 CPUs supports a maximum of four
sensors, so only search for a maximum of four sensors on Zen1 CPUs.
On top of that, in thm_10_0_sh_mask.h in the Linux kernel, we find
definitions for THM_DIE{1-3}_TEMP__VALID_MASK, set to 0x00000800, as well
as matching SMN addresses. This lets us conclude that bit 11 of the
respective registers is a valid bit. With this assumption, the temperature
offset is now 49 degrees C. This conveniently matches the documented
temperature offset for Tdie, again suggesting that above registers indeed
report temperatures sensor values. Assume that bit 11 is indeed a valid
bit, and add support for the additional sensors.
With this patch applied, output from 3970X (idle) looks as follows:
k10temp-pci-00c3
Adapter: PCI adapter
Tdie: +55.9°C
Tctl: +55.9°C
Tccd1: +39.8°C
Tccd3: +43.8°C
Tccd5: +43.8°C
Tccd7: +44.8°C
Tested-by: Michael Larabel <michael@phoronix.com>
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
This commit is contained in:
Guenter Roeck
parent
9c4a38f19e
commit
fd8bdb23b9
@ -7,7 +7,7 @@
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* Copyright (c) 2020 Guenter Roeck <linux@roeck-us.net>
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*
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* Implementation notes:
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* - CCD1 and CCD2 register address information as well as the calculation to
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* - CCD register address information as well as the calculation to
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* convert raw register values is from https://github.com/ocerman/zenpower.
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* The information is not confirmed from chip datasheets, but experiments
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* suggest that it provides reasonable temperature values.
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@ -18,11 +18,6 @@
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* normalized to report 1A/LSB for core current and and 0.25A/LSB for SoC
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* current. Reported values can be adjusted using the sensors configuration
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* file.
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* - It is unknown if the mechanism to read CCD1/CCD2 temperature as well as
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* current and voltage information works on higher-end Ryzen CPUs.
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* Information reported by Windows tools suggests that additional sensors
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* (both temperature and voltage/current) are supported, but their register
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* location is currently unknown.
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*/
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#include <linux/bitops.h>
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@ -80,8 +75,10 @@ static DEFINE_MUTEX(nb_smu_ind_mutex);
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/* F17h M01h Access througn SMN */
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#define F17H_M01H_REPORTED_TEMP_CTRL_OFFSET 0x00059800
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#define F17H_M70H_CCD1_TEMP 0x00059954
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#define F17H_M70H_CCD2_TEMP 0x00059958
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#define F17H_M70H_CCD_TEMP(x) (0x00059954 + ((x) * 4))
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#define F17H_M70H_CCD_TEMP_VALID BIT(11)
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#define F17H_M70H_CCD_TEMP_MASK GENMASK(10, 0)
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#define F17H_M01H_SVI 0x0005A000
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#define F17H_M01H_SVI_TEL_PLANE0 (F17H_M01H_SVI + 0xc)
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@ -100,8 +97,7 @@ struct k10temp_data {
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int temp_offset;
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u32 temp_adjust_mask;
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bool show_tdie;
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bool show_tccd1;
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bool show_tccd2;
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u32 show_tccd;
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u32 svi_addr[2];
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bool show_current;
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int cfactor[2];
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@ -188,6 +184,12 @@ const char *k10temp_temp_label[] = {
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"Tctl",
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"Tccd1",
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"Tccd2",
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"Tccd3",
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"Tccd4",
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"Tccd5",
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"Tccd6",
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"Tccd7",
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"Tccd8",
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};
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const char *k10temp_in_label[] = {
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@ -277,15 +279,10 @@ static int k10temp_read_temp(struct device *dev, u32 attr, int channel,
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if (*val < 0)
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*val = 0;
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break;
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case 2: /* Tccd1 */
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case 2 ... 9: /* Tccd{1-8} */
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amd_smn_read(amd_pci_dev_to_node_id(data->pdev),
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F17H_M70H_CCD1_TEMP, ®val);
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*val = (regval & 0xfff) * 125 - 305000;
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break;
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case 3: /* Tccd2 */
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amd_smn_read(amd_pci_dev_to_node_id(data->pdev),
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F17H_M70H_CCD2_TEMP, ®val);
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*val = (regval & 0xfff) * 125 - 305000;
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F17H_M70H_CCD_TEMP(channel - 2), ®val);
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*val = (regval & F17H_M70H_CCD_TEMP_MASK) * 125 - 49000;
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break;
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default:
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return -EOPNOTSUPP;
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@ -343,12 +340,8 @@ static umode_t k10temp_is_visible(const void *_data,
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if (!data->show_tdie)
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return 0;
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break;
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case 2: /* Tccd1 */
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if (!data->show_tccd1)
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return 0;
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break;
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case 3: /* Tccd2 */
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if (!data->show_tccd2)
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case 2 ... 9: /* Tccd{1-8} */
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if (!(data->show_tccd & BIT(channel - 2)))
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return 0;
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break;
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default:
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@ -382,12 +375,8 @@ static umode_t k10temp_is_visible(const void *_data,
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case 0: /* Tdie */
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case 1: /* Tctl */
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break;
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case 2: /* Tccd1 */
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if (!data->show_tccd1)
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return 0;
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break;
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case 3: /* Tccd2 */
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if (!data->show_tccd2)
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case 2 ... 9: /* Tccd{1-8} */
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if (!(data->show_tccd & BIT(channel - 2)))
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return 0;
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break;
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default:
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@ -520,6 +509,12 @@ static const struct hwmon_channel_info *k10temp_info[] = {
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HWMON_T_LABEL,
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HWMON_T_INPUT | HWMON_T_LABEL,
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HWMON_T_INPUT | HWMON_T_LABEL,
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HWMON_T_INPUT | HWMON_T_LABEL,
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HWMON_T_INPUT | HWMON_T_LABEL,
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HWMON_T_INPUT | HWMON_T_LABEL,
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HWMON_T_INPUT | HWMON_T_LABEL,
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HWMON_T_INPUT | HWMON_T_LABEL,
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HWMON_T_INPUT | HWMON_T_LABEL,
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HWMON_T_INPUT | HWMON_T_LABEL),
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HWMON_CHANNEL_INFO(in,
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HWMON_I_INPUT | HWMON_I_LABEL,
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@ -541,6 +536,20 @@ static const struct hwmon_chip_info k10temp_chip_info = {
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.info = k10temp_info,
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};
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static void k10temp_get_ccd_support(struct pci_dev *pdev,
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struct k10temp_data *data, int limit)
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{
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u32 regval;
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int i;
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for (i = 0; i < limit; i++) {
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amd_smn_read(amd_pci_dev_to_node_id(pdev),
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F17H_M70H_CCD_TEMP(i), ®val);
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if (regval & F17H_M70H_CCD_TEMP_VALID)
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data->show_tccd |= BIT(i);
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}
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}
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static int k10temp_probe(struct pci_dev *pdev, const struct pci_device_id *id)
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{
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int unreliable = has_erratum_319(pdev);
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@ -571,8 +580,6 @@ static int k10temp_probe(struct pci_dev *pdev, const struct pci_device_id *id)
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data->read_htcreg = read_htcreg_nb_f15;
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data->read_tempreg = read_tempreg_nb_f15;
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} else if (boot_cpu_data.x86 == 0x17 || boot_cpu_data.x86 == 0x18) {
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u32 regval;
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data->temp_adjust_mask = CUR_TEMP_RANGE_SEL_MASK;
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data->read_tempreg = read_tempreg_nb_f17;
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data->show_tdie = true;
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@ -587,6 +594,7 @@ static int k10temp_probe(struct pci_dev *pdev, const struct pci_device_id *id)
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data->svi_addr[1] = F17H_M01H_SVI_TEL_PLANE1;
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data->cfactor[0] = CFACTOR_ICORE;
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data->cfactor[1] = CFACTOR_ISOC;
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k10temp_get_ccd_support(pdev, data, 4);
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break;
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case 0x31: /* Zen2 Threadripper */
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case 0x71: /* Zen2 */
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@ -595,15 +603,7 @@ static int k10temp_probe(struct pci_dev *pdev, const struct pci_device_id *id)
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data->cfactor[1] = CFACTOR_ISOC;
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data->svi_addr[0] = F17H_M01H_SVI_TEL_PLANE1;
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data->svi_addr[1] = F17H_M01H_SVI_TEL_PLANE0;
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amd_smn_read(amd_pci_dev_to_node_id(pdev),
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F17H_M70H_CCD1_TEMP, ®val);
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if (regval & 0xfff)
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data->show_tccd1 = true;
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amd_smn_read(amd_pci_dev_to_node_id(pdev),
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F17H_M70H_CCD2_TEMP, ®val);
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if (regval & 0xfff)
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data->show_tccd2 = true;
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k10temp_get_ccd_support(pdev, data, 8);
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break;
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}
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} else {
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