mirror of
https://github.com/torvalds/linux.git
synced 2024-12-29 14:21:47 +00:00
clk: ti: add clkctrl data omap5 sgx
Looks like we have sgx clock missing currently so let's add it. Cc: Adam Ford <aford173@gmail.com> Cc: Filip Matijević <filip.matijevic.pz@gmail.com> Cc: "H. Nikolaus Schaller" <hns@goldelico.com> Cc: Ivaylo Dimitrov <ivo.g.dimitrov.75@gmail.com> Cc: moaz korena <moaz@korena.xyz> Cc: Merlijn Wajer <merlijn@wizzup.org> Cc: Michael Turquette <mturquette@baylibre.com> Cc: Paweł Chmiel <pawel.mikolaj.chmiel@gmail.com> Cc: Philipp Rossak <embed3d@gmail.com> Cc: Stephen Boyd <sboyd@kernel.org> Cc: Tero Kristo <t-kristo@ti.com> Cc: Tomi Valkeinen <tomi.valkeinen@ti.com> Cc: linux-clk@vger.kernel.org Acked-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Tony Lindgren <tony@atomide.com>
This commit is contained in:
parent
1b95c5a48f
commit
fd56837494
@ -314,6 +314,39 @@ static const struct omap_clkctrl_reg_data omap5_dss_clkctrl_regs[] __initconst =
|
||||
{ 0 },
|
||||
};
|
||||
|
||||
static const char * const omap5_gpu_core_mux_parents[] __initconst = {
|
||||
"dpll_core_h14x2_ck",
|
||||
"dpll_per_h14x2_ck",
|
||||
NULL,
|
||||
};
|
||||
|
||||
static const char * const omap5_gpu_hyd_mux_parents[] __initconst = {
|
||||
"dpll_core_h14x2_ck",
|
||||
"dpll_per_h14x2_ck",
|
||||
NULL,
|
||||
};
|
||||
|
||||
static const char * const omap5_gpu_sys_clk_parents[] __initconst = {
|
||||
"sys_clkin",
|
||||
NULL,
|
||||
};
|
||||
|
||||
static const struct omap_clkctrl_div_data omap5_gpu_sys_clk_data __initconst = {
|
||||
.max_div = 2,
|
||||
};
|
||||
|
||||
static const struct omap_clkctrl_bit_data omap5_gpu_core_bit_data[] __initconst = {
|
||||
{ 24, TI_CLK_MUX, omap5_gpu_core_mux_parents, NULL },
|
||||
{ 25, TI_CLK_MUX, omap5_gpu_hyd_mux_parents, NULL },
|
||||
{ 26, TI_CLK_DIVIDER, omap5_gpu_sys_clk_parents, &omap5_gpu_sys_clk_data },
|
||||
{ 0 },
|
||||
};
|
||||
|
||||
static const struct omap_clkctrl_reg_data omap5_gpu_clkctrl_regs[] __initconst = {
|
||||
{ OMAP5_GPU_CLKCTRL, omap5_gpu_core_bit_data, CLKF_SW_SUP, "gpu_cm:clk:0000:24" },
|
||||
{ 0 },
|
||||
};
|
||||
|
||||
static const char * const omap5_mmc1_fclk_mux_parents[] __initconst = {
|
||||
"func_128m_clk",
|
||||
"dpll_per_m2x2_ck",
|
||||
@ -470,6 +503,7 @@ const struct omap_clkctrl_data omap5_clkctrl_data[] __initconst = {
|
||||
{ 0x4a008e20, omap5_l3instr_clkctrl_regs },
|
||||
{ 0x4a009020, omap5_l4per_clkctrl_regs },
|
||||
{ 0x4a009420, omap5_dss_clkctrl_regs },
|
||||
{ 0x4a009520, omap5_gpu_clkctrl_regs },
|
||||
{ 0x4a009620, omap5_l3init_clkctrl_regs },
|
||||
{ 0x4ae07920, omap5_wkupaon_clkctrl_regs },
|
||||
{ 0 },
|
||||
|
@ -89,6 +89,9 @@
|
||||
/* dss clocks */
|
||||
#define OMAP5_DSS_CORE_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
|
||||
|
||||
/* gpu clocks */
|
||||
#define OMAP5_GPU_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
|
||||
|
||||
/* l3init clocks */
|
||||
#define OMAP5_MMC1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x28)
|
||||
#define OMAP5_MMC2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x30)
|
||||
|
Loading…
Reference in New Issue
Block a user