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ARM: i.MX: Use CLOCKSOURCE_OF_DECLARE() for DT targets
This patch uses clocksource_of_init() call for DT targets. Signed-off-by: Alexander Shiyan <shc_work@mail.ru> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
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@ -113,7 +113,5 @@ static void __init mx1_clocks_init_dt(struct device_node *np)
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clk_data.clks = clk;
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clk_data.clk_num = ARRAY_SIZE(clk);
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of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
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mxc_timer_init_dt(of_find_compatible_node(NULL, NULL, "fsl,imx1-gpt"));
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}
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CLK_OF_DECLARE(imx1_ccm, "fsl,imx1-ccm", mx1_clocks_init_dt);
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@ -167,7 +167,5 @@ static void __init mx21_clocks_init_dt(struct device_node *np)
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clk_data.clks = clk;
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clk_data.clk_num = ARRAY_SIZE(clk);
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of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
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mxc_timer_init_dt(of_find_compatible_node(NULL, NULL, "fsl,imx1-gpt"));
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}
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CLK_OF_DECLARE(imx27_ccm, "fsl,imx21-ccm", mx21_clocks_init_dt);
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@ -335,7 +335,5 @@ static void __init mx25_clocks_init_dt(struct device_node *np)
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clk_data.clks = clk;
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clk_data.clk_num = ARRAY_SIZE(clk);
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of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
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mxc_timer_init_dt(of_find_compatible_node(NULL, NULL, "fsl,imx25-gpt"));
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}
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CLK_OF_DECLARE(imx25_ccm, "fsl,imx25-ccm", mx25_clocks_init_dt);
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@ -254,7 +254,5 @@ static void __init mx27_clocks_init_dt(struct device_node *np)
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clk_data.clks = clk;
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clk_data.clk_num = ARRAY_SIZE(clk);
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of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
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mxc_timer_init_dt(of_find_compatible_node(NULL, NULL, "fsl,imx1-gpt"));
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}
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CLK_OF_DECLARE(imx27_ccm, "fsl,imx27-ccm", mx27_clocks_init_dt);
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@ -370,8 +370,6 @@ static void __init mx50_clocks_init(struct device_node *np)
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r = clk_round_rate(clk[IMX5_CLK_USBOH3_PER_GATE], 54000000);
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clk_set_rate(clk[IMX5_CLK_USBOH3_PER_GATE], r);
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mxc_timer_init_dt(of_find_compatible_node(NULL, NULL, "fsl,imx50-gpt"));
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}
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CLK_OF_DECLARE(imx50_ccm, "fsl,imx50-ccm", mx50_clocks_init);
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@ -443,9 +441,6 @@ static void __init mx51_clocks_init(struct device_node *np)
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clk_set_rate(clk[IMX5_CLK_ESDHC_A_PODF], 166250000);
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clk_set_rate(clk[IMX5_CLK_ESDHC_B_PODF], 166250000);
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/* System timer */
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mxc_timer_init_dt(of_find_compatible_node(NULL, NULL, "fsl,imx51-gpt"));
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clk_prepare_enable(clk[IMX5_CLK_IIM_GATE]);
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imx_print_silicon_rev("i.MX51", mx51_revision());
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clk_disable_unprepare(clk[IMX5_CLK_IIM_GATE]);
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@ -562,7 +557,5 @@ static void __init mx53_clocks_init(struct device_node *np)
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r = clk_round_rate(clk[IMX5_CLK_USBOH3_PER_GATE], 54000000);
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clk_set_rate(clk[IMX5_CLK_USBOH3_PER_GATE], r);
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mxc_timer_init_dt(of_find_compatible_node(NULL, NULL, "fsl,imx53-gpt"));
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}
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CLK_OF_DECLARE(imx53_ccm, "fsl,imx53-ccm", mx53_clocks_init);
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@ -455,7 +455,5 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
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/* Set initial power mode */
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imx6q_set_lpm(WAIT_CLOCKED);
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mxc_timer_init_dt(of_find_compatible_node(NULL, NULL, "fsl,imx6q-gpt"));
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}
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CLK_OF_DECLARE(imx6q, "fsl,imx6q-ccm", imx6q_clocks_init);
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@ -377,8 +377,5 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node)
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/* Set initial power mode */
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imx6q_set_lpm(WAIT_CLOCKED);
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np = of_find_compatible_node(NULL, NULL, "fsl,imx6sl-gpt");
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mxc_timer_init_dt(np);
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}
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CLK_OF_DECLARE(imx6sl, "fsl,imx6sl-ccm", imx6sl_clocks_init);
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@ -515,8 +515,5 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node)
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/* Set initial power mode */
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imx6q_set_lpm(WAIT_CLOCKED);
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np = of_find_compatible_node(NULL, NULL, "fsl,imx6sx-gpt");
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mxc_timer_init_dt(np);
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}
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CLK_OF_DECLARE(imx6sx, "fsl,imx6sx-ccm", imx6sx_clocks_init);
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@ -49,7 +49,6 @@ void imx31_soc_init(void);
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void imx35_soc_init(void);
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void epit_timer_init(void __iomem *base, int irq);
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void mxc_timer_init(void __iomem *, int);
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void mxc_timer_init_dt(struct device_node *);
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int mx1_clocks_init(unsigned long fref);
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int mx21_clocks_init(unsigned long lref, unsigned long fref);
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int mx25_clocks_init(void);
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@ -337,11 +337,14 @@ void __init mxc_timer_init(void __iomem *base, int irq)
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_mxc_timer_init(irq, clk_per, clk_ipg);
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}
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void __init mxc_timer_init_dt(struct device_node *np)
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static void __init mxc_timer_init_dt(struct device_node *np)
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{
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struct clk *clk_per, *clk_ipg;
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int irq;
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if (timer_base)
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return;
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timer_base = of_iomap(np, 0);
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WARN_ON(!timer_base);
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irq = irq_of_parse_and_map(np, 0);
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@ -351,3 +354,11 @@ void __init mxc_timer_init_dt(struct device_node *np)
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_mxc_timer_init(irq, clk_per, clk_ipg);
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}
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CLOCKSOURCE_OF_DECLARE(mx1_timer, "fsl,imx1-gpt", mxc_timer_init_dt);
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CLOCKSOURCE_OF_DECLARE(mx25_timer, "fsl,imx25-gpt", mxc_timer_init_dt);
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CLOCKSOURCE_OF_DECLARE(mx50_timer, "fsl,imx50-gpt", mxc_timer_init_dt);
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CLOCKSOURCE_OF_DECLARE(mx51_timer, "fsl,imx51-gpt", mxc_timer_init_dt);
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CLOCKSOURCE_OF_DECLARE(mx53_timer, "fsl,imx53-gpt", mxc_timer_init_dt);
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CLOCKSOURCE_OF_DECLARE(mx6q_timer, "fsl,imx6q-gpt", mxc_timer_init_dt);
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CLOCKSOURCE_OF_DECLARE(mx6sl_timer, "fsl,imx6sl-gpt", mxc_timer_init_dt);
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CLOCKSOURCE_OF_DECLARE(mx6sx_timer, "fsl,imx6sx-gpt", mxc_timer_init_dt);
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