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clk: pxa: export 32kHz PLL
This clock is especially used by the RTC driver, so export it so that devicetree users can use it. Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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@ -292,8 +292,10 @@ static void __init pxa25x_register_plls(void)
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{
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clk_register_fixed_rate(NULL, "osc_3_6864mhz", NULL,
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CLK_GET_RATE_NOCACHE, 3686400);
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clkdev_pxa_register(CLK_OSC32k768, "osc_32_768khz", NULL,
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clk_register_fixed_rate(NULL, "osc_32_768khz", NULL,
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CLK_GET_RATE_NOCACHE, 32768);
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CLK_GET_RATE_NOCACHE,
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32768));
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clk_register_fixed_rate(NULL, "clk_dummy", NULL, 0, 0);
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clk_register_fixed_factor(NULL, "ppll_95_85mhz", "osc_3_6864mhz",
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0, 26, 1);
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@ -314,9 +314,10 @@ static void __init pxa27x_register_plls(void)
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clk_register_fixed_rate(NULL, "osc_13mhz", NULL,
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CLK_GET_RATE_NOCACHE,
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13 * MHz);
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clkdev_pxa_register(CLK_OSC32k768, "osc_32_768khz", NULL,
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clk_register_fixed_rate(NULL, "osc_32_768khz", NULL,
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CLK_GET_RATE_NOCACHE,
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32768 * KHz);
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32768 * KHz));
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clk_register_fixed_rate(NULL, "clk_dummy", NULL, 0, 0);
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clk_register_fixed_factor(NULL, "ppll_312mhz", "osc_13mhz", 0, 24, 1);
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}
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@ -286,9 +286,10 @@ static void __init pxa3xx_register_plls(void)
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clk_register_fixed_rate(NULL, "osc_13mhz", NULL,
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CLK_GET_RATE_NOCACHE,
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13 * MHz);
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clkdev_pxa_register(CLK_OSC32k768, "osc_32_768khz", NULL,
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clk_register_fixed_rate(NULL, "osc_32_768khz", NULL,
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CLK_GET_RATE_NOCACHE,
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32768);
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32768));
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clk_register_fixed_rate(NULL, "ring_osc_120mhz", NULL,
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CLK_GET_RATE_NOCACHE,
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120 * MHz);
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@ -72,6 +72,7 @@
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#define CLK_USIM 58
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#define CLK_USIM1 59
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#define CLK_USMI0 60
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#define CLK_MAX 61
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#define CLK_OSC32k768 61
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#define CLK_MAX 62
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#endif
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