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MIPS: ralink: fix USB frequency scaling
Commit 418d29c870
("MIPS: ralink: Unify SoC id handling") was not fully
correct. The logic for the SoC check got inverted. We need to check if it
is not a MT76x8.
Signed-off-by: John Crispin <blogic@openwrt.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/11992/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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@ -459,7 +459,7 @@ void __init ralink_clk_init(void)
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ralink_clk_add("10000c00.uartlite", periph_rate);
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ralink_clk_add("10180000.wmac", xtal_rate);
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if (IS_ENABLED(CONFIG_USB) && is_mt76x8()) {
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if (IS_ENABLED(CONFIG_USB) && !is_mt76x8()) {
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/*
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* When the CPU goes into sleep mode, the BUS clock will be
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* too low for USB to function properly. Adjust the busses
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