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ASoC: cs35l45: Support for GPIO pins configuration.
Adds device tree configuration for cs35l45 GPIOs Signed-off-by: Vlad Karpovich <vkarpovi@opensource.cirrus.com> Link: https://lore.kernel.org/r/20230315154722.3911463-1-vkarpovi@opensource.cirrus.com Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Vlad.Karpovich
Mark Brown
parent
00a7ef3242
commit
fa8c052b4c
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@ -17,4 +17,61 @@
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#define CS35L45_ASP_TX_HIZ_UNUSED 0x1
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#define CS35L45_ASP_TX_HIZ_DISABLED 0x2
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/*
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* Optional GPIOX Sub-nodes:
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* The cs35l45 node can have up to three "cirrus,gpio-ctrlX" ('X' = [1,2,3])
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* sub-nodes for configuring the GPIO pins.
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*
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* - gpio-dir : GPIO pin direction. Valid only when 'gpio-ctrl'
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* is 1.
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* 0 = Output
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* 1 = Input (Default)
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*
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* - gpio-lvl : GPIO level. Valid only when 'gpio-ctrl' is 1 and 'gpio-dir' is 0.
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*
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* 0 = Low (Default)
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* 1 = High
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*
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* - gpio-op-cfg : GPIO output configuration. Valid only when 'gpio-ctrl' is 1
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* and 'gpio-dir' is 0.
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*
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* 0 = CMOS (Default)
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* 1 = Open Drain
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*
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* - gpio-pol : GPIO output polarity select. Valid only when 'gpio-ctrl' is 1
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* and 'gpio-dir' is 0.
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*
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* 0 = Non-inverted, Active High (Default)
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* 1 = Inverted, Active Low
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*
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* - gpio-invert : Defines the polarity of the GPIO pin if configured
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* as input.
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*
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* 0 = Not inverted (Default)
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* 1 = Inverted
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*
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* - gpio-ctrl : Defines the function of the GPIO pin.
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*
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* GPIO1:
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* 0 = High impedance input (Default)
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* 1 = Pin acts as a GPIO, direction controlled by 'gpio-dir'
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* 2 = Pin acts as MDSYNC, direction controlled by MDSYNC
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* 3-7 = Reserved
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*
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* GPIO2:
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* 0 = High impedance input (Default)
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* 1 = Pin acts as a GPIO, direction controlled by 'gpio-dir'
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* 2 = Pin acts as open drain INT
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* 3 = Reserved
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* 4 = Pin acts as push-pull output INT. Active low.
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* 5 = Pin acts as push-pull output INT. Active high.
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* 6,7 = Reserved
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*
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* GPIO3:
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* 0 = High impedance input (Default)
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* 1 = Pin acts as a GPIO, direction controlled by 'gpio-dir'
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* 2-7 = Reserved
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*/
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#define CS35L45_NUM_GPIOS 0x3
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#endif /* DT_CS35L45_H */
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@ -43,6 +43,9 @@ EXPORT_SYMBOL_NS_GPL(cs35l45_apply_patch, SND_SOC_CS35L45);
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static const struct reg_default cs35l45_defaults[] = {
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{ CS35L45_BLOCK_ENABLES, 0x00003323 },
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{ CS35L45_BLOCK_ENABLES2, 0x00000010 },
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{ CS35L45_SYNC_GPIO1, 0x00000007 },
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{ CS35L45_INTB_GPIO2_MCLK_REF, 0x00000005 },
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{ CS35L45_GPIO3, 0x00000005 },
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{ CS35L45_REFCLK_INPUT, 0x00000510 },
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{ CS35L45_GLOBAL_SAMPLE_RATE, 0x00000003 },
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{ CS35L45_ASP_ENABLES1, 0x00000000 },
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@ -61,6 +64,9 @@ static const struct reg_default cs35l45_defaults[] = {
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{ CS35L45_ASPTX4_INPUT, 0x00000028 },
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{ CS35L45_ASPTX5_INPUT, 0x00000048 },
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{ CS35L45_AMP_PCM_CONTROL, 0x00100000 },
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{ CS35L45_GPIO1_CTRL1, 0x81000001 },
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{ CS35L45_GPIO2_CTRL1, 0x81000001 },
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{ CS35L45_GPIO3_CTRL1, 0x81000001 },
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};
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static bool cs35l45_readable_reg(struct device *dev, unsigned int reg)
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@ -72,6 +78,9 @@ static bool cs35l45_readable_reg(struct device *dev, unsigned int reg)
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case CS35L45_BLOCK_ENABLES:
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case CS35L45_BLOCK_ENABLES2:
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case CS35L45_ERROR_RELEASE:
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case CS35L45_SYNC_GPIO1:
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case CS35L45_INTB_GPIO2_MCLK_REF:
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case CS35L45_GPIO3:
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case CS35L45_REFCLK_INPUT:
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case CS35L45_GLOBAL_SAMPLE_RATE:
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case CS35L45_ASP_ENABLES1:
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@ -92,6 +101,10 @@ static bool cs35l45_readable_reg(struct device *dev, unsigned int reg)
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case CS35L45_AMP_PCM_CONTROL:
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case CS35L45_AMP_PCM_HPF_TST:
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case CS35L45_IRQ1_EINT_4:
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case CS35L45_GPIO_STATUS1:
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case CS35L45_GPIO1_CTRL1:
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case CS35L45_GPIO2_CTRL1:
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case CS35L45_GPIO3_CTRL1:
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return true;
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default:
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return false;
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@ -107,6 +120,7 @@ static bool cs35l45_volatile_reg(struct device *dev, unsigned int reg)
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case CS35L45_ERROR_RELEASE:
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case CS35L45_AMP_PCM_HPF_TST: /* not cachable */
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case CS35L45_IRQ1_EINT_4:
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case CS35L45_GPIO_STATUS1:
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return true;
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default:
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return false;
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@ -536,7 +536,63 @@ static int __maybe_unused cs35l45_runtime_resume(struct device *dev)
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static int cs35l45_apply_property_config(struct cs35l45_private *cs35l45)
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{
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struct device_node *node = cs35l45->dev->of_node;
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unsigned int gpio_regs[] = {CS35L45_GPIO1_CTRL1, CS35L45_GPIO2_CTRL1,
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CS35L45_GPIO3_CTRL1};
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unsigned int pad_regs[] = {CS35L45_SYNC_GPIO1,
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CS35L45_INTB_GPIO2_MCLK_REF, CS35L45_GPIO3};
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struct device_node *child;
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unsigned int val;
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char of_name[32];
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int ret, i;
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if (!node)
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return 0;
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for (i = 0; i < CS35L45_NUM_GPIOS; i++) {
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sprintf(of_name, "cirrus,gpio-ctrl%d", i + 1);
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child = of_get_child_by_name(node, of_name);
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if (!child)
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continue;
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ret = of_property_read_u32(child, "gpio-dir", &val);
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if (!ret)
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regmap_update_bits(cs35l45->regmap, gpio_regs[i],
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CS35L45_GPIO_DIR_MASK,
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val << CS35L45_GPIO_DIR_SHIFT);
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ret = of_property_read_u32(child, "gpio-lvl", &val);
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if (!ret)
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regmap_update_bits(cs35l45->regmap, gpio_regs[i],
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CS35L45_GPIO_LVL_MASK,
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val << CS35L45_GPIO_LVL_SHIFT);
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ret = of_property_read_u32(child, "gpio-op-cfg", &val);
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if (!ret)
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regmap_update_bits(cs35l45->regmap, gpio_regs[i],
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CS35L45_GPIO_OP_CFG_MASK,
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val << CS35L45_GPIO_OP_CFG_SHIFT);
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ret = of_property_read_u32(child, "gpio-pol", &val);
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if (!ret)
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regmap_update_bits(cs35l45->regmap, gpio_regs[i],
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CS35L45_GPIO_POL_MASK,
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val << CS35L45_GPIO_POL_SHIFT);
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ret = of_property_read_u32(child, "gpio-ctrl", &val);
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if (!ret)
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regmap_update_bits(cs35l45->regmap, pad_regs[i],
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CS35L45_GPIO_CTRL_MASK,
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val << CS35L45_GPIO_CTRL_SHIFT);
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ret = of_property_read_u32(child, "gpio-invert", &val);
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if (!ret)
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regmap_update_bits(cs35l45->regmap, pad_regs[i],
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CS35L45_GPIO_INVERT_MASK,
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val << CS35L45_GPIO_INVERT_SHIFT);
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of_node_put(child);
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}
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if (device_property_read_u32(cs35l45->dev,
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"cirrus,asp-sdout-hiz-ctrl", &val) == 0) {
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@ -14,6 +14,7 @@
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#include <linux/pm_runtime.h>
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#include <linux/regmap.h>
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#include <linux/regulator/consumer.h>
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#include <dt-bindings/sound/cs35l45.h>
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#define CS35L45_DEVID 0x00000000
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#define CS35L45_REVID 0x00000004
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@ -24,6 +25,9 @@
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#define CS35L45_BLOCK_ENABLES 0x00002018
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#define CS35L45_BLOCK_ENABLES2 0x0000201C
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#define CS35L45_ERROR_RELEASE 0x00002034
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#define CS35L45_SYNC_GPIO1 0x00002430
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#define CS35L45_INTB_GPIO2_MCLK_REF 0x00002434
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#define CS35L45_GPIO3 0x00002438
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#define CS35L45_REFCLK_INPUT 0x00002C04
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#define CS35L45_GLOBAL_SAMPLE_RATE 0x00002C0C
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#define CS35L45_BOOST_CCM_CFG 0x00003808
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@ -48,8 +52,11 @@
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#define CS35L45_AMP_PCM_CONTROL 0x00007000
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#define CS35L45_AMP_PCM_HPF_TST 0x00007004
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#define CS35L45_IRQ1_EINT_4 0x0000E01C
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#define CS35L45_LASTREG 0x0000E01C
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#define CS35L45_GPIO_STATUS1 0x0000F000
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#define CS35L45_GPIO1_CTRL1 0x0000F008
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#define CS35L45_GPIO2_CTRL1 0x0000F00C
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#define CS35L45_GPIO3_CTRL1 0x0000F010
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#define CS35L45_LASTREG 0x0000F010
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/* SFT_RESET */
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#define CS35L45_SOFT_RESET_TRIGGER 0x5A000000
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@ -165,6 +172,22 @@
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#define CS35L45_OTP_BOOT_DONE_STS_MASK BIT(1)
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#define CS35L45_OTP_BUSY_MASK BIT(0)
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/* GPIOX_CTRL1 */
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#define CS35L45_GPIO_DIR_SHIFT 31
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#define CS35L45_GPIO_DIR_MASK BIT(31)
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#define CS35L45_GPIO_LVL_SHIFT 15
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#define CS35L45_GPIO_LVL_MASK BIT(15)
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#define CS35L45_GPIO_OP_CFG_SHIFT 14
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#define CS35L45_GPIO_OP_CFG_MASK BIT(14)
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#define CS35L45_GPIO_POL_SHIFT 12
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#define CS35L45_GPIO_POL_MASK BIT(12)
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/* SYNC_GPIO1, INTB_GPIO2_MCLK_REF, GPIO3 */
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#define CS35L45_GPIO_CTRL_SHIFT 20
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#define CS35L45_GPIO_CTRL_MASK GENMASK(22, 20)
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#define CS35L45_GPIO_INVERT_SHIFT 19
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#define CS35L45_GPIO_INVERT_MASK BIT(19)
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/* Mixer sources */
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#define CS35L45_PCM_SRC_MASK 0x7F
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#define CS35L45_PCM_SRC_ZERO 0x00
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