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arm64: insn: add encoders for atomic operations
It is a preparation patch for eBPF atomic supports under arm64. eBPF
needs support atomic[64]_fetch_add, atomic[64]_[fetch_]{and,or,xor} and
atomic[64]_{xchg|cmpxchg}. The ordering semantics of eBPF atomics are
the same with the implementations in linux kernel.
Add three helpers to support LDCLR/LDEOR/LDSET/SWP, CAS and DMB
instructions. STADD/STCLR/STEOR/STSET are simply encoded as aliases for
LDADD/LDCLR/LDEOR/LDSET with XZR as the destination register, so no extra
helper is added. atomic_fetch_add() and other atomic ops needs support for
STLXR instruction, so extend enum aarch64_insn_ldst_type to do that.
LDADD/LDEOR/LDSET/SWP and CAS instructions are only available when LSE
atomics is enabled, so just return AARCH64_BREAK_FAULT directly in
these newly-added helpers if CONFIG_ARM64_LSE_ATOMICS is disabled.
Signed-off-by: Hou Tao <houtao1@huawei.com>
Link: https://lore.kernel.org/r/20220217072232.1186625-3-houtao1@huawei.com
Signed-off-by: Will Deacon <will@kernel.org>
This commit is contained in:
Hou Tao
Will Deacon
parent
97e58e395e
commit
fa1114d9eb
@ -205,7 +205,9 @@ enum aarch64_insn_ldst_type {
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AARCH64_INSN_LDST_LOAD_PAIR_POST_INDEX,
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AARCH64_INSN_LDST_STORE_PAIR_POST_INDEX,
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AARCH64_INSN_LDST_LOAD_EX,
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AARCH64_INSN_LDST_LOAD_ACQ_EX,
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AARCH64_INSN_LDST_STORE_EX,
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AARCH64_INSN_LDST_STORE_REL_EX,
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};
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enum aarch64_insn_adsb_type {
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@ -280,6 +282,36 @@ enum aarch64_insn_adr_type {
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AARCH64_INSN_ADR_TYPE_ADR,
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};
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enum aarch64_insn_mem_atomic_op {
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AARCH64_INSN_MEM_ATOMIC_ADD,
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AARCH64_INSN_MEM_ATOMIC_CLR,
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AARCH64_INSN_MEM_ATOMIC_EOR,
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AARCH64_INSN_MEM_ATOMIC_SET,
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AARCH64_INSN_MEM_ATOMIC_SWP,
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};
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enum aarch64_insn_mem_order_type {
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AARCH64_INSN_MEM_ORDER_NONE,
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AARCH64_INSN_MEM_ORDER_ACQ,
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AARCH64_INSN_MEM_ORDER_REL,
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AARCH64_INSN_MEM_ORDER_ACQREL,
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};
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enum aarch64_insn_mb_type {
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AARCH64_INSN_MB_SY,
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AARCH64_INSN_MB_ST,
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AARCH64_INSN_MB_LD,
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AARCH64_INSN_MB_ISH,
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AARCH64_INSN_MB_ISHST,
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AARCH64_INSN_MB_ISHLD,
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AARCH64_INSN_MB_NSH,
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AARCH64_INSN_MB_NSHST,
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AARCH64_INSN_MB_NSHLD,
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AARCH64_INSN_MB_OSH,
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AARCH64_INSN_MB_OSHST,
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AARCH64_INSN_MB_OSHLD,
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};
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#define __AARCH64_INSN_FUNCS(abbr, mask, val) \
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static __always_inline bool aarch64_insn_is_##abbr(u32 code) \
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{ \
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@ -303,6 +335,11 @@ __AARCH64_INSN_FUNCS(store_post, 0x3FE00C00, 0x38000400)
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__AARCH64_INSN_FUNCS(load_post, 0x3FE00C00, 0x38400400)
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__AARCH64_INSN_FUNCS(str_reg, 0x3FE0EC00, 0x38206800)
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__AARCH64_INSN_FUNCS(ldadd, 0x3F20FC00, 0x38200000)
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__AARCH64_INSN_FUNCS(ldclr, 0x3F20FC00, 0x38201000)
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__AARCH64_INSN_FUNCS(ldeor, 0x3F20FC00, 0x38202000)
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__AARCH64_INSN_FUNCS(ldset, 0x3F20FC00, 0x38203000)
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__AARCH64_INSN_FUNCS(swp, 0x3F20FC00, 0x38208000)
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__AARCH64_INSN_FUNCS(cas, 0x3FA07C00, 0x08A07C00)
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__AARCH64_INSN_FUNCS(ldr_reg, 0x3FE0EC00, 0x38606800)
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__AARCH64_INSN_FUNCS(ldr_lit, 0xBF000000, 0x18000000)
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__AARCH64_INSN_FUNCS(ldrsw_lit, 0xFF000000, 0x98000000)
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@ -474,13 +511,6 @@ u32 aarch64_insn_gen_load_store_ex(enum aarch64_insn_register reg,
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enum aarch64_insn_register state,
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enum aarch64_insn_size_type size,
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enum aarch64_insn_ldst_type type);
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u32 aarch64_insn_gen_ldadd(enum aarch64_insn_register result,
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enum aarch64_insn_register address,
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enum aarch64_insn_register value,
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enum aarch64_insn_size_type size);
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u32 aarch64_insn_gen_stadd(enum aarch64_insn_register address,
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enum aarch64_insn_register value,
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enum aarch64_insn_size_type size);
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u32 aarch64_insn_gen_add_sub_imm(enum aarch64_insn_register dst,
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enum aarch64_insn_register src,
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int imm, enum aarch64_insn_variant variant,
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@ -541,6 +571,42 @@ u32 aarch64_insn_gen_prefetch(enum aarch64_insn_register base,
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enum aarch64_insn_prfm_type type,
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enum aarch64_insn_prfm_target target,
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enum aarch64_insn_prfm_policy policy);
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#ifdef CONFIG_ARM64_LSE_ATOMICS
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u32 aarch64_insn_gen_atomic_ld_op(enum aarch64_insn_register result,
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enum aarch64_insn_register address,
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enum aarch64_insn_register value,
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enum aarch64_insn_size_type size,
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enum aarch64_insn_mem_atomic_op op,
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enum aarch64_insn_mem_order_type order);
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u32 aarch64_insn_gen_cas(enum aarch64_insn_register result,
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enum aarch64_insn_register address,
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enum aarch64_insn_register value,
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enum aarch64_insn_size_type size,
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enum aarch64_insn_mem_order_type order);
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#else
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static inline
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u32 aarch64_insn_gen_atomic_ld_op(enum aarch64_insn_register result,
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enum aarch64_insn_register address,
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enum aarch64_insn_register value,
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enum aarch64_insn_size_type size,
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enum aarch64_insn_mem_atomic_op op,
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enum aarch64_insn_mem_order_type order)
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{
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return AARCH64_BREAK_FAULT;
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}
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static inline
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u32 aarch64_insn_gen_cas(enum aarch64_insn_register result,
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enum aarch64_insn_register address,
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enum aarch64_insn_register value,
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enum aarch64_insn_size_type size,
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enum aarch64_insn_mem_order_type order)
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{
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return AARCH64_BREAK_FAULT;
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}
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#endif
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u32 aarch64_insn_gen_dmb(enum aarch64_insn_mb_type type);
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s32 aarch64_get_branch_offset(u32 insn);
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u32 aarch64_set_branch_offset(u32 insn, s32 offset);
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@ -578,10 +578,16 @@ u32 aarch64_insn_gen_load_store_ex(enum aarch64_insn_register reg,
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switch (type) {
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case AARCH64_INSN_LDST_LOAD_EX:
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case AARCH64_INSN_LDST_LOAD_ACQ_EX:
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insn = aarch64_insn_get_load_ex_value();
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if (type == AARCH64_INSN_LDST_LOAD_ACQ_EX)
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insn |= BIT(15);
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break;
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case AARCH64_INSN_LDST_STORE_EX:
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case AARCH64_INSN_LDST_STORE_REL_EX:
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insn = aarch64_insn_get_store_ex_value();
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if (type == AARCH64_INSN_LDST_STORE_REL_EX)
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insn |= BIT(15);
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break;
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default:
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pr_err("%s: unknown load/store exclusive encoding %d\n", __func__, type);
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@ -603,12 +609,65 @@ u32 aarch64_insn_gen_load_store_ex(enum aarch64_insn_register reg,
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state);
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}
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u32 aarch64_insn_gen_ldadd(enum aarch64_insn_register result,
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enum aarch64_insn_register address,
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enum aarch64_insn_register value,
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enum aarch64_insn_size_type size)
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#ifdef CONFIG_ARM64_LSE_ATOMICS
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static u32 aarch64_insn_encode_ldst_order(enum aarch64_insn_mem_order_type type,
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u32 insn)
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{
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u32 insn = aarch64_insn_get_ldadd_value();
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u32 order;
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switch (type) {
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case AARCH64_INSN_MEM_ORDER_NONE:
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order = 0;
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break;
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case AARCH64_INSN_MEM_ORDER_ACQ:
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order = 2;
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break;
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case AARCH64_INSN_MEM_ORDER_REL:
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order = 1;
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break;
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case AARCH64_INSN_MEM_ORDER_ACQREL:
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order = 3;
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break;
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default:
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pr_err("%s: unknown mem order %d\n", __func__, type);
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return AARCH64_BREAK_FAULT;
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}
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insn &= ~GENMASK(23, 22);
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insn |= order << 22;
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return insn;
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}
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u32 aarch64_insn_gen_atomic_ld_op(enum aarch64_insn_register result,
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enum aarch64_insn_register address,
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enum aarch64_insn_register value,
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enum aarch64_insn_size_type size,
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enum aarch64_insn_mem_atomic_op op,
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enum aarch64_insn_mem_order_type order)
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{
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u32 insn;
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switch (op) {
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case AARCH64_INSN_MEM_ATOMIC_ADD:
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insn = aarch64_insn_get_ldadd_value();
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break;
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case AARCH64_INSN_MEM_ATOMIC_CLR:
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insn = aarch64_insn_get_ldclr_value();
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break;
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case AARCH64_INSN_MEM_ATOMIC_EOR:
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insn = aarch64_insn_get_ldeor_value();
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break;
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case AARCH64_INSN_MEM_ATOMIC_SET:
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insn = aarch64_insn_get_ldset_value();
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break;
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case AARCH64_INSN_MEM_ATOMIC_SWP:
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insn = aarch64_insn_get_swp_value();
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break;
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default:
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pr_err("%s: unimplemented mem atomic op %d\n", __func__, op);
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return AARCH64_BREAK_FAULT;
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}
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switch (size) {
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case AARCH64_INSN_SIZE_32:
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@ -621,6 +680,8 @@ u32 aarch64_insn_gen_ldadd(enum aarch64_insn_register result,
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insn = aarch64_insn_encode_ldst_size(size, insn);
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insn = aarch64_insn_encode_ldst_order(order, insn);
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insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RT, insn,
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result);
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@ -631,18 +692,69 @@ u32 aarch64_insn_gen_ldadd(enum aarch64_insn_register result,
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value);
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}
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u32 aarch64_insn_gen_stadd(enum aarch64_insn_register address,
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enum aarch64_insn_register value,
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enum aarch64_insn_size_type size)
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static u32 aarch64_insn_encode_cas_order(enum aarch64_insn_mem_order_type type,
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u32 insn)
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{
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/*
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* STADD is simply encoded as an alias for LDADD with XZR as
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* the destination register.
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*/
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return aarch64_insn_gen_ldadd(AARCH64_INSN_REG_ZR, address,
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value, size);
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u32 order;
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switch (type) {
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case AARCH64_INSN_MEM_ORDER_NONE:
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order = 0;
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break;
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case AARCH64_INSN_MEM_ORDER_ACQ:
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order = BIT(22);
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break;
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case AARCH64_INSN_MEM_ORDER_REL:
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order = BIT(15);
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break;
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case AARCH64_INSN_MEM_ORDER_ACQREL:
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order = BIT(15) | BIT(22);
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break;
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default:
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pr_err("%s: unknown mem order %d\n", __func__, type);
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return AARCH64_BREAK_FAULT;
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}
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insn &= ~(BIT(15) | BIT(22));
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insn |= order;
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return insn;
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}
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u32 aarch64_insn_gen_cas(enum aarch64_insn_register result,
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enum aarch64_insn_register address,
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enum aarch64_insn_register value,
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enum aarch64_insn_size_type size,
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enum aarch64_insn_mem_order_type order)
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{
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u32 insn;
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switch (size) {
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case AARCH64_INSN_SIZE_32:
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case AARCH64_INSN_SIZE_64:
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break;
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default:
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pr_err("%s: unimplemented size encoding %d\n", __func__, size);
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return AARCH64_BREAK_FAULT;
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}
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insn = aarch64_insn_get_cas_value();
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insn = aarch64_insn_encode_ldst_size(size, insn);
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insn = aarch64_insn_encode_cas_order(order, insn);
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insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RT, insn,
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result);
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insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN, insn,
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address);
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return aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RS, insn,
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value);
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}
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#endif
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static u32 aarch64_insn_encode_prfm_imm(enum aarch64_insn_prfm_type type,
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enum aarch64_insn_prfm_target target,
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enum aarch64_insn_prfm_policy policy,
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@ -1456,3 +1568,48 @@ u32 aarch64_insn_gen_extr(enum aarch64_insn_variant variant,
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insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN, insn, Rn);
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return aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RM, insn, Rm);
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}
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u32 aarch64_insn_gen_dmb(enum aarch64_insn_mb_type type)
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{
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u32 opt;
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u32 insn;
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switch (type) {
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case AARCH64_INSN_MB_SY:
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opt = 0xf;
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break;
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case AARCH64_INSN_MB_ST:
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opt = 0xe;
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break;
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case AARCH64_INSN_MB_LD:
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opt = 0xd;
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break;
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case AARCH64_INSN_MB_ISH:
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opt = 0xb;
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break;
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case AARCH64_INSN_MB_ISHST:
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opt = 0xa;
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break;
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case AARCH64_INSN_MB_ISHLD:
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opt = 0x9;
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break;
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case AARCH64_INSN_MB_NSH:
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opt = 0x7;
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break;
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case AARCH64_INSN_MB_NSHST:
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opt = 0x6;
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break;
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case AARCH64_INSN_MB_NSHLD:
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opt = 0x5;
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break;
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default:
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pr_err("%s: unknown dmb type %d\n", __func__, type);
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return AARCH64_BREAK_FAULT;
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}
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insn = aarch64_insn_get_dmb_value();
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insn &= ~GENMASK(11, 8);
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insn |= (opt << 8);
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return insn;
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}
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@ -89,9 +89,16 @@
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#define A64_STXR(sf, Rt, Rn, Rs) \
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A64_LSX(sf, Rt, Rn, Rs, STORE_EX)
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/* LSE atomics */
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/*
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* LSE atomics
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*
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* STADD is simply encoded as an alias for LDADD with XZR as
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* the destination register.
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*/
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#define A64_STADD(sf, Rn, Rs) \
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aarch64_insn_gen_stadd(Rn, Rs, A64_SIZE(sf))
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aarch64_insn_gen_atomic_ld_op(A64_ZR, Rn, Rs, \
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A64_SIZE(sf), AARCH64_INSN_MEM_ATOMIC_ADD, \
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AARCH64_INSN_MEM_ORDER_NONE)
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/* Add/subtract (immediate) */
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#define A64_ADDSUB_IMM(sf, Rd, Rn, imm12, type) \
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