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KVM: arm64: pmu: Use generated define for PMSELR_EL0.SEL access
ARMV8_PMU_COUNTER_MASK is really a mask for the PMSELR_EL0.SEL register field. Make that clear by adding a standard sysreg definition for the register, and using it instead. Reviewed-by: Mark Rutland <mark.rutland@arm.com> Acked-by: Mark Rutland <mark.rutland@arm.com> Reviewed-by: Marc Zyngier <maz@kernel.org> Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Tested-by: James Clark <james.clark@linaro.org> Link: https://lore.kernel.org/r/20240731-arm-pmu-3-9-icntr-v3-4-280a8d7ff465@kernel.org Signed-off-by: Will Deacon <will@kernel.org>
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@ -403,7 +403,6 @@
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#define SYS_PMCNTENCLR_EL0 sys_reg(3, 3, 9, 12, 2)
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#define SYS_PMOVSCLR_EL0 sys_reg(3, 3, 9, 12, 3)
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#define SYS_PMSWINC_EL0 sys_reg(3, 3, 9, 12, 4)
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#define SYS_PMSELR_EL0 sys_reg(3, 3, 9, 12, 5)
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#define SYS_PMCEID0_EL0 sys_reg(3, 3, 9, 12, 6)
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#define SYS_PMCEID1_EL0 sys_reg(3, 3, 9, 12, 7)
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#define SYS_PMCCNTR_EL0 sys_reg(3, 3, 9, 13, 0)
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@ -887,7 +887,7 @@ static u64 reset_pmevtyper(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
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static u64 reset_pmselr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
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{
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reset_unknown(vcpu, r);
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__vcpu_sys_reg(vcpu, r->reg) &= ARMV8_PMU_COUNTER_MASK;
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__vcpu_sys_reg(vcpu, r->reg) &= PMSELR_EL0_SEL_MASK;
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return __vcpu_sys_reg(vcpu, r->reg);
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}
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@ -979,7 +979,7 @@ static bool access_pmselr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
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else
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/* return PMSELR.SEL field */
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p->regval = __vcpu_sys_reg(vcpu, PMSELR_EL0)
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& ARMV8_PMU_COUNTER_MASK;
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& PMSELR_EL0_SEL_MASK;
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return true;
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}
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@ -1047,8 +1047,8 @@ static bool access_pmu_evcntr(struct kvm_vcpu *vcpu,
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if (pmu_access_event_counter_el0_disabled(vcpu))
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return false;
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idx = __vcpu_sys_reg(vcpu, PMSELR_EL0)
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& ARMV8_PMU_COUNTER_MASK;
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idx = SYS_FIELD_GET(PMSELR_EL0, SEL,
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__vcpu_sys_reg(vcpu, PMSELR_EL0));
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} else if (r->Op2 == 0) {
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/* PMCCNTR_EL0 */
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if (pmu_access_cycle_counter_el0_disabled(vcpu))
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@ -1098,7 +1098,7 @@ static bool access_pmu_evtyper(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
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if (r->CRn == 9 && r->CRm == 13 && r->Op2 == 1) {
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/* PMXEVTYPER_EL0 */
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idx = __vcpu_sys_reg(vcpu, PMSELR_EL0) & ARMV8_PMU_COUNTER_MASK;
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idx = SYS_FIELD_GET(PMSELR_EL0, SEL, __vcpu_sys_reg(vcpu, PMSELR_EL0));
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reg = PMEVTYPER0_EL0 + idx;
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} else if (r->CRn == 14 && (r->CRm & 12) == 12) {
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idx = ((r->CRm & 3) << 3) | (r->Op2 & 7);
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@ -2153,6 +2153,11 @@ Field 4 P
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Field 3:0 ALIGN
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EndSysreg
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Sysreg PMSELR_EL0 3 3 9 12 5
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Res0 63:5
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Field 4:0 SEL
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EndSysreg
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SysregFields CONTEXTIDR_ELx
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Res0 63:32
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Field 31:0 PROCID
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@ -8,7 +8,6 @@
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#define ARMV8_PMU_MAX_GENERAL_COUNTERS 31
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#define ARMV8_PMU_MAX_COUNTERS 32
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#define ARMV8_PMU_COUNTER_MASK (ARMV8_PMU_MAX_COUNTERS - 1)
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/*
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* Common architectural and microarchitectural event numbers.
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