usb: host: xhci-plat: Make enum xhci_plat_type start at a non zero value

Otherwise generic-xhci and xhci-platform which have no data get wrongly
detected as XHCI_PLAT_TYPE_MARVELL_ARMADA by xhci_plat_type_is().

This fixes a regression in v4.5 for STiH407 family SoC's which use the
synopsis dwc3 IP, whereby the disable_clk error path gets taken due to
wrongly being detected as XHCI_PLAT_TYPE_MARVELL_ARMADA and the hcd never
gets added.

I suspect this will also fix other dwc3 DT platforms such as Exynos,
although I've only tested on STih410 SoC.

Fixes: 4efb2f6941 ("usb: host: xhci-plat: add struct xhci_plat_priv")
Cc: stable@vger.kernel.org
Cc: gregory.clement@free-electrons.com
Cc: yoshihiro.shimoda.uh@renesas.com
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Peter Griffin 2016-04-13 19:58:44 +03:00 committed by Greg Kroah-Hartman
parent 98d74f9cea
commit f9a85f6e61

View File

@ -14,7 +14,7 @@
#include "xhci.h" /* for hcd_to_xhci() */ #include "xhci.h" /* for hcd_to_xhci() */
enum xhci_plat_type { enum xhci_plat_type {
XHCI_PLAT_TYPE_MARVELL_ARMADA, XHCI_PLAT_TYPE_MARVELL_ARMADA = 1,
XHCI_PLAT_TYPE_RENESAS_RCAR_GEN2, XHCI_PLAT_TYPE_RENESAS_RCAR_GEN2,
XHCI_PLAT_TYPE_RENESAS_RCAR_GEN3, XHCI_PLAT_TYPE_RENESAS_RCAR_GEN3,
}; };