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MIPS: RBTX4927: More explicit initialization

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* Make sure all interrupts cleared on startup
* Initialize some GPIOs

Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Atsushi Nemoto 2008-08-19 22:55:05 +09:00 committed by Ralf Baechle
parent 9fa32c6b02
commit f96a3383cf
3 changed files with 16 additions and 0 deletions
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5
arch/mips/txx9/rbtx4927/irq.c
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@ -142,6 +142,11 @@ static void __init toshiba_rbtx4927_irq_ioc_init(void)
{ {
int i; int i;
/* mask all IOC interrupts */
writeb(0, rbtx4927_imask_addr);
/* clear SoftInt interrupts */
writeb(0, rbtx4927_softint_addr);
for (i = RBTX4927_IRQ_IOC; for (i = RBTX4927_IRQ_IOC;
i < RBTX4927_IRQ_IOC + RBTX4927_NR_IRQ_IOC; i++) i < RBTX4927_IRQ_IOC + RBTX4927_NR_IRQ_IOC; i++)
set_irq_chip_and_handler(i, &toshiba_rbtx4927_irq_ioc_type, set_irq_chip_and_handler(i, &toshiba_rbtx4927_irq_ioc_type,

9
arch/mips/txx9/rbtx4927/setup.c
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@ -48,6 +48,7 @@
#include <linux/ioport.h> #include <linux/ioport.h>
#include <linux/platform_device.h> #include <linux/platform_device.h>
#include <linux/delay.h> #include <linux/delay.h>
#include <linux/gpio.h>
#include <asm/io.h> #include <asm/io.h>
#include <asm/reboot.h> #include <asm/reboot.h>
#include <asm/txx9/generic.h> #include <asm/txx9/generic.h>
@ -212,6 +213,14 @@ static void __init rbtx4927_mem_setup(void)
set_io_port_base(KSEG1 + RBTX4927_ISA_IO_OFFSET); set_io_port_base(KSEG1 + RBTX4927_ISA_IO_OFFSET);
#endif #endif
/* TX4927-SIO DTR on (PIO[15]) */
gpio_request(15, "sio-dtr");
gpio_direction_output(15, 1);
gpio_request(0, "led");
gpio_direction_output(0, 1);
gpio_request(1, "led");
gpio_direction_output(1, 1);
tx4927_sio_init(0, 0); tx4927_sio_init(0, 0);
#ifdef CONFIG_SERIAL_TXX9_CONSOLE #ifdef CONFIG_SERIAL_TXX9_CONSOLE
argptr = prom_getcmdline(); argptr = prom_getcmdline();

2
include/asm-mips/txx9/rbtx4927.h
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@ -36,6 +36,7 @@
#define RBTX4927_IMASK_ADDR (IO_BASE + TXX9_CE(2) + 0x00002000) #define RBTX4927_IMASK_ADDR (IO_BASE + TXX9_CE(2) + 0x00002000)
#define RBTX4927_IMSTAT_ADDR (IO_BASE + TXX9_CE(2) + 0x00002006) #define RBTX4927_IMSTAT_ADDR (IO_BASE + TXX9_CE(2) + 0x00002006)
#define RBTX4927_SOFTINT_ADDR (IO_BASE + TXX9_CE(2) + 0x00003000)
#define RBTX4927_SOFTRESET_ADDR (IO_BASE + TXX9_CE(2) + 0x0000f000) #define RBTX4927_SOFTRESET_ADDR (IO_BASE + TXX9_CE(2) + 0x0000f000)
#define RBTX4927_SOFTRESETLOCK_ADDR (IO_BASE + TXX9_CE(2) + 0x0000f002) #define RBTX4927_SOFTRESETLOCK_ADDR (IO_BASE + TXX9_CE(2) + 0x0000f002)
#define RBTX4927_PCIRESET_ADDR (IO_BASE + TXX9_CE(2) + 0x0000f006) #define RBTX4927_PCIRESET_ADDR (IO_BASE + TXX9_CE(2) + 0x0000f006)
@ -47,6 +48,7 @@
#define rbtx4927_imask_addr ((__u8 __iomem *)RBTX4927_IMASK_ADDR) #define rbtx4927_imask_addr ((__u8 __iomem *)RBTX4927_IMASK_ADDR)
#define rbtx4927_imstat_addr ((__u8 __iomem *)RBTX4927_IMSTAT_ADDR) #define rbtx4927_imstat_addr ((__u8 __iomem *)RBTX4927_IMSTAT_ADDR)
#define rbtx4927_softint_addr ((__u8 __iomem *)RBTX4927_SOFTINT_ADDR)
#define rbtx4927_softreset_addr ((__u8 __iomem *)RBTX4927_SOFTRESET_ADDR) #define rbtx4927_softreset_addr ((__u8 __iomem *)RBTX4927_SOFTRESET_ADDR)
#define rbtx4927_softresetlock_addr \ #define rbtx4927_softresetlock_addr \
((__u8 __iomem *)RBTX4927_SOFTRESETLOCK_ADDR) ((__u8 __iomem *)RBTX4927_SOFTRESETLOCK_ADDR)