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amd64_edac: add ECC reporting initializers
Borislav:
- convert to the new {rd|wr}msr_on_cpus interfaces.
- convert pvt->old_mcgctl to a bitmask thus saving some bytes
- fix/cleanup comments
- fix function return value patterns
- add a proper bugfix found by Doug to amd64_check_ecc_enabled where we
missed checking for the ECC enabled bit in NB CFG.
- cleanup debug calls
Reviewed-by: Mauro Carvalho Chehab <mchehab@redhat.com>
Signed-off-by: Doug Thompson <dougthompson@xmission.com>
Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
This commit is contained in:
Doug Thompson
Borislav Petkov
parent
0ec449ee95
commit
f9431992b6
@ -2771,3 +2771,210 @@ static int amd64_init_csrows(struct mem_ctl_info *mci)
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return empty;
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}
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/*
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* Only if 'ecc_enable_override' is set AND BIOS had ECC disabled, do "we"
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* enable it.
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*/
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static void amd64_enable_ecc_error_reporting(struct mem_ctl_info *mci)
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{
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struct amd64_pvt *pvt = mci->pvt_info;
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const cpumask_t *cpumask = cpumask_of_node(pvt->mc_node_id);
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int cpu, idx = 0, err = 0;
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struct msr msrs[cpumask_weight(cpumask)];
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u32 value;
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u32 mask = K8_NBCTL_CECCEn | K8_NBCTL_UECCEn;
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if (!ecc_enable_override)
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return;
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memset(msrs, 0, sizeof(msrs));
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amd64_printk(KERN_WARNING,
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"'ecc_enable_override' parameter is active, "
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"Enabling AMD ECC hardware now: CAUTION\n");
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err = pci_read_config_dword(pvt->misc_f3_ctl, K8_NBCTL, &value);
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if (err)
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debugf0("Reading K8_NBCTL failed\n");
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/* turn on UECCn and CECCEn bits */
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pvt->old_nbctl = value & mask;
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pvt->nbctl_mcgctl_saved = 1;
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value |= mask;
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pci_write_config_dword(pvt->misc_f3_ctl, K8_NBCTL, value);
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rdmsr_on_cpus(cpumask, K8_MSR_MCGCTL, msrs);
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for_each_cpu(cpu, cpumask) {
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if (msrs[idx].l & K8_MSR_MCGCTL_NBE)
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set_bit(idx, &pvt->old_mcgctl);
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msrs[idx].l |= K8_MSR_MCGCTL_NBE;
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idx++;
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}
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wrmsr_on_cpus(cpumask, K8_MSR_MCGCTL, msrs);
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err = pci_read_config_dword(pvt->misc_f3_ctl, K8_NBCFG, &value);
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if (err)
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debugf0("Reading K8_NBCFG failed\n");
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debugf0("NBCFG(1)= 0x%x CHIPKILL= %s ECC_ENABLE= %s\n", value,
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(value & K8_NBCFG_CHIPKILL) ? "Enabled" : "Disabled",
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(value & K8_NBCFG_ECC_ENABLE) ? "Enabled" : "Disabled");
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if (!(value & K8_NBCFG_ECC_ENABLE)) {
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amd64_printk(KERN_WARNING,
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"This node reports that DRAM ECC is "
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"currently Disabled; ENABLING now\n");
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/* Attempt to turn on DRAM ECC Enable */
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value |= K8_NBCFG_ECC_ENABLE;
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pci_write_config_dword(pvt->misc_f3_ctl, K8_NBCFG, value);
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err = pci_read_config_dword(pvt->misc_f3_ctl, K8_NBCFG, &value);
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if (err)
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debugf0("Reading K8_NBCFG failed\n");
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if (!(value & K8_NBCFG_ECC_ENABLE)) {
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amd64_printk(KERN_WARNING,
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"Hardware rejects Enabling DRAM ECC checking\n"
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"Check memory DIMM configuration\n");
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} else {
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amd64_printk(KERN_DEBUG,
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"Hardware accepted DRAM ECC Enable\n");
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}
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}
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debugf0("NBCFG(2)= 0x%x CHIPKILL= %s ECC_ENABLE= %s\n", value,
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(value & K8_NBCFG_CHIPKILL) ? "Enabled" : "Disabled",
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(value & K8_NBCFG_ECC_ENABLE) ? "Enabled" : "Disabled");
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pvt->ctl_error_info.nbcfg = value;
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}
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static void amd64_restore_ecc_error_reporting(struct amd64_pvt *pvt)
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{
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const cpumask_t *cpumask = cpumask_of_node(pvt->mc_node_id);
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int cpu, idx = 0, err = 0;
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struct msr msrs[cpumask_weight(cpumask)];
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u32 value;
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u32 mask = K8_NBCTL_CECCEn | K8_NBCTL_UECCEn;
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if (!pvt->nbctl_mcgctl_saved)
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return;
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memset(msrs, 0, sizeof(msrs));
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err = pci_read_config_dword(pvt->misc_f3_ctl, K8_NBCTL, &value);
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if (err)
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debugf0("Reading K8_NBCTL failed\n");
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value &= ~mask;
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value |= pvt->old_nbctl;
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/* restore the NB Enable MCGCTL bit */
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pci_write_config_dword(pvt->misc_f3_ctl, K8_NBCTL, value);
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rdmsr_on_cpus(cpumask, K8_MSR_MCGCTL, msrs);
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for_each_cpu(cpu, cpumask) {
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msrs[idx].l &= ~K8_MSR_MCGCTL_NBE;
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msrs[idx].l |=
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test_bit(idx, &pvt->old_mcgctl) << K8_MSR_MCGCTL_NBE;
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idx++;
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}
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wrmsr_on_cpus(cpumask, K8_MSR_MCGCTL, msrs);
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}
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static void check_mcg_ctl(void *ret)
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{
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u64 msr_val = 0;
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u8 nbe;
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rdmsrl(MSR_IA32_MCG_CTL, msr_val);
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nbe = msr_val & K8_MSR_MCGCTL_NBE;
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debugf0("core: %u, MCG_CTL: 0x%llx, NB MSR is %s\n",
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raw_smp_processor_id(), msr_val,
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(nbe ? "enabled" : "disabled"));
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if (!nbe)
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*(int *)ret = 0;
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}
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/* check MCG_CTL on all the cpus on this node */
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static int amd64_mcg_ctl_enabled_on_cpus(const cpumask_t *mask)
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{
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int ret = 1;
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preempt_disable();
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smp_call_function_many(mask, check_mcg_ctl, &ret, 1);
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preempt_enable();
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return ret;
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}
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/*
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* EDAC requires that the BIOS have ECC enabled before taking over the
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* processing of ECC errors. This is because the BIOS can properly initialize
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* the memory system completely. A command line option allows to force-enable
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* hardware ECC later in amd64_enable_ecc_error_reporting().
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*/
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static int amd64_check_ecc_enabled(struct amd64_pvt *pvt)
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{
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u32 value;
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int err = 0, ret = 0;
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u8 ecc_enabled = 0;
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err = pci_read_config_dword(pvt->misc_f3_ctl, K8_NBCFG, &value);
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if (err)
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debugf0("Reading K8_NBCTL failed\n");
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ecc_enabled = !!(value & K8_NBCFG_ECC_ENABLE);
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ret = amd64_mcg_ctl_enabled_on_cpus(cpumask_of_node(pvt->mc_node_id));
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debugf0("K8_NBCFG=0x%x, DRAM ECC is %s\n", value,
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(value & K8_NBCFG_ECC_ENABLE ? "enabled" : "disabled"));
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if (!ecc_enabled || !ret) {
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if (!ecc_enabled) {
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amd64_printk(KERN_WARNING, "This node reports that "
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"Memory ECC is currently "
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"disabled.\n");
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amd64_printk(KERN_WARNING, "bit 0x%lx in register "
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"F3x%x of the MISC_CONTROL device (%s) "
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"should be enabled\n", K8_NBCFG_ECC_ENABLE,
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K8_NBCFG, pci_name(pvt->misc_f3_ctl));
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}
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if (!ret) {
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amd64_printk(KERN_WARNING, "bit 0x%016lx in MSR 0x%08x "
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"of node %d should be enabled\n",
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K8_MSR_MCGCTL_NBE, MSR_IA32_MCG_CTL,
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pvt->mc_node_id);
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}
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if (!ecc_enable_override) {
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amd64_printk(KERN_WARNING, "WARNING: ECC is NOT "
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"currently enabled by the BIOS. Module "
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"will NOT be loaded.\n"
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" Either Enable ECC in the BIOS, "
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"or use the 'ecc_enable_override' "
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"parameter.\n"
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" Might be a BIOS bug, if BIOS says "
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"ECC is enabled\n"
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" Use of the override can cause "
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"unknown side effects.\n");
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ret = -ENODEV;
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}
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} else {
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amd64_printk(KERN_INFO,
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"ECC is enabled by BIOS, Proceeding "
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"with EDAC module initialization\n");
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/* CLEAR the override, since BIOS controlled it */
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ecc_enable_override = 0;
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}
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return ret;
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}
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@ -70,6 +70,7 @@
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#include <linux/slab.h>
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#include <linux/mmzone.h>
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#include <linux/edac.h>
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#include <asm/msr.h>
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#include "edac_core.h"
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#define amd64_printk(level, fmt, arg...) \
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@ -549,7 +550,7 @@ struct amd64_pvt {
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/* Save old hw registers' values before we modified them */
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u32 nbctl_mcgctl_saved; /* When true, following 2 are valid */
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u32 old_nbctl;
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u32 *old_mcgctl; /* per core on this node */
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unsigned long old_mcgctl; /* per core on this node */
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/* MC Type Index value: socket F vs Family 10h */
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u32 mc_type_index;
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