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i2c: uniphier-f: reword according to newest specification
Change the wording of this driver wrt. the newest I2C v7 and SMBus 3.2 specifications and replace "master/slave" with more appropriate terms. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Andi Shyti <andi.shyti@kernel.org> Signed-off-by: Andi Shyti <andi.shyti@kernel.org>
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@ -12,15 +12,15 @@
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#include <linux/platform_device.h>
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#define UNIPHIER_FI2C_CR 0x00 /* control register */
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#define UNIPHIER_FI2C_CR_MST BIT(3) /* master mode */
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#define UNIPHIER_FI2C_CR_MST BIT(3) /* controller mode */
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#define UNIPHIER_FI2C_CR_STA BIT(2) /* start condition */
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#define UNIPHIER_FI2C_CR_STO BIT(1) /* stop condition */
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#define UNIPHIER_FI2C_CR_NACK BIT(0) /* do not return ACK */
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#define UNIPHIER_FI2C_DTTX 0x04 /* TX FIFO */
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#define UNIPHIER_FI2C_DTTX_CMD BIT(8) /* send command (slave addr) */
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#define UNIPHIER_FI2C_DTTX_CMD BIT(8) /* send command (target addr) */
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#define UNIPHIER_FI2C_DTTX_RD BIT(0) /* read transaction */
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#define UNIPHIER_FI2C_DTRX 0x04 /* RX FIFO */
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#define UNIPHIER_FI2C_SLAD 0x0c /* slave address */
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#define UNIPHIER_FI2C_SLAD 0x0c /* target address */
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#define UNIPHIER_FI2C_CYC 0x10 /* clock cycle control */
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#define UNIPHIER_FI2C_LCTL 0x14 /* clock low period control */
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#define UNIPHIER_FI2C_SSUT 0x18 /* restart/stop setup time control */
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@ -96,7 +96,7 @@ static void uniphier_fi2c_fill_txfifo(struct uniphier_fi2c_priv *priv,
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int fifo_space = UNIPHIER_FI2C_FIFO_SIZE;
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/*
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* TX-FIFO stores slave address in it for the first access.
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* TX-FIFO stores target address in it for the first access.
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* Decrement the counter.
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*/
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if (first)
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@ -252,7 +252,7 @@ static void uniphier_fi2c_tx_init(struct uniphier_fi2c_priv *priv, u16 addr,
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/* do not use TX byte counter */
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writel(0, priv->membase + UNIPHIER_FI2C_TBC);
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/* set slave address */
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/* set target address */
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writel(UNIPHIER_FI2C_DTTX_CMD | addr << 1,
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priv->membase + UNIPHIER_FI2C_DTTX);
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/*
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@ -288,7 +288,7 @@ static void uniphier_fi2c_rx_init(struct uniphier_fi2c_priv *priv, u16 addr)
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uniphier_fi2c_set_irqs(priv);
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/* set slave address with RD bit */
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/* set target address with RD bit */
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writel(UNIPHIER_FI2C_DTTX_CMD | UNIPHIER_FI2C_DTTX_RD | addr << 1,
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priv->membase + UNIPHIER_FI2C_DTTX);
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}
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@ -310,9 +310,8 @@ static void uniphier_fi2c_recover(struct uniphier_fi2c_priv *priv)
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i2c_recover_bus(&priv->adap);
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}
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static int uniphier_fi2c_master_xfer_one(struct i2c_adapter *adap,
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struct i2c_msg *msg, bool repeat,
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bool stop)
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static int uniphier_fi2c_xfer_one(struct i2c_adapter *adap, struct i2c_msg *msg,
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bool repeat, bool stop)
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{
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struct uniphier_fi2c_priv *priv = i2c_get_adapdata(adap);
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bool is_read = msg->flags & I2C_M_RD;
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@ -340,7 +339,7 @@ static int uniphier_fi2c_master_xfer_one(struct i2c_adapter *adap,
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uniphier_fi2c_tx_init(priv, msg->addr, repeat);
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/*
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* For a repeated START condition, writing a slave address to the FIFO
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* For a repeated START condition, writing a target address to the FIFO
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* kicks the controller. So, the UNIPHIER_FI2C_CR register should be
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* written only for a non-repeated START condition.
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*/
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@ -403,8 +402,7 @@ static int uniphier_fi2c_check_bus_busy(struct i2c_adapter *adap)
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return 0;
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}
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static int uniphier_fi2c_master_xfer(struct i2c_adapter *adap,
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struct i2c_msg *msgs, int num)
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static int uniphier_fi2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
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{
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struct i2c_msg *msg, *emsg = msgs + num;
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bool repeat = false;
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@ -418,7 +416,7 @@ static int uniphier_fi2c_master_xfer(struct i2c_adapter *adap,
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/* Emit STOP if it is the last message or I2C_M_STOP is set. */
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bool stop = (msg + 1 == emsg) || (msg->flags & I2C_M_STOP);
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ret = uniphier_fi2c_master_xfer_one(adap, msg, repeat, stop);
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ret = uniphier_fi2c_xfer_one(adap, msg, repeat, stop);
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if (ret)
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return ret;
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@ -434,7 +432,7 @@ static u32 uniphier_fi2c_functionality(struct i2c_adapter *adap)
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}
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static const struct i2c_algorithm uniphier_fi2c_algo = {
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.master_xfer = uniphier_fi2c_master_xfer,
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.xfer = uniphier_fi2c_xfer,
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.functionality = uniphier_fi2c_functionality,
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};
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