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MIPS: Loongson-3: Add some unaligned instructions emulation
1, Add unaligned gslq, gssq, gslqc1, gssqc1 emulation;
2, Add unaligned gsl{h, w, d}x, gss{h, w, d}x emulation;
3, Add unaligned gslwxc1, gsswxc1, gsldxc1, gssdxc1 emulation.
Signed-off-by: Huacai Chen <chenhc@lemote.com>
Signed-off-by: Pei Huang <huangpei@loongson.cn>
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
This commit is contained in:
Huacai Chen
Thomas Bogendoerfer
parent
d339cd02b8
commit
f83e4f9896
@ -988,6 +988,30 @@ struct mm16_r5_format { /* Load/store from stack pointer format */
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;))))
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};
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/*
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* Loongson-3 overridden COP2 instruction formats (32-bit length)
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*/
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struct loongson3_lswc2_format { /* Loongson-3 overridden lwc2/swc2 Load/Store format */
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__BITFIELD_FIELD(unsigned int opcode : 6,
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__BITFIELD_FIELD(unsigned int base : 5,
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__BITFIELD_FIELD(unsigned int rt : 5,
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__BITFIELD_FIELD(unsigned int fr : 1,
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__BITFIELD_FIELD(unsigned int offset : 9,
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__BITFIELD_FIELD(unsigned int ls : 1,
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__BITFIELD_FIELD(unsigned int rq : 5,
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;)))))))
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};
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struct loongson3_lsdc2_format { /* Loongson-3 overridden ldc2/sdc2 Load/Store format */
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__BITFIELD_FIELD(unsigned int opcode : 6,
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__BITFIELD_FIELD(unsigned int base : 5,
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__BITFIELD_FIELD(unsigned int rt : 5,
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__BITFIELD_FIELD(unsigned int index : 5,
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__BITFIELD_FIELD(unsigned int offset : 8,
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__BITFIELD_FIELD(unsigned int opcode1 : 3,
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;))))))
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};
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/*
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* MIPS16e instruction formats (16-bit length)
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*/
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@ -1088,6 +1112,8 @@ union mips_instruction {
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struct mm16_rb_format mm16_rb_format;
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struct mm16_r3_format mm16_r3_format;
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struct mm16_r5_format mm16_r5_format;
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struct loongson3_lswc2_format loongson3_lswc2_format;
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struct loongson3_lsdc2_format loongson3_lsdc2_format;
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};
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union mips16e_instruction {
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@ -14,17 +14,29 @@
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#include <linux/sched.h>
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#include <linux/notifier.h>
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#include <linux/ptrace.h>
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#include <linux/uaccess.h>
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#include <linux/sched/signal.h>
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#include <asm/fpu.h>
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#include <asm/cop2.h>
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#include <asm/inst.h>
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#include <asm/branch.h>
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#include <asm/current.h>
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#include <asm/mipsregs.h>
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static int loongson_cu2_call(struct notifier_block *nfb, unsigned long action,
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void *data)
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{
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int fpu_owned;
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unsigned int res, fpu_owned;
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unsigned long ra, value, value_next;
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union mips_instruction insn;
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int fr = !test_thread_flag(TIF_32BIT_FPREGS);
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struct pt_regs *regs = (struct pt_regs *)data;
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void __user *addr = (void __user *)regs->cp0_badvaddr;
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unsigned int __user *pc = (unsigned int __user *)exception_epc(regs);
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ra = regs->regs[31];
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__get_user(insn.word, pc);
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switch (action) {
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case CU2_EXCEPTION:
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@ -49,9 +61,284 @@ static int loongson_cu2_call(struct notifier_block *nfb, unsigned long action,
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preempt_enable();
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return NOTIFY_STOP; /* Don't call default notifier */
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case CU2_LWC2_OP:
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if (insn.loongson3_lswc2_format.ls == 0)
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goto sigbus;
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if (insn.loongson3_lswc2_format.fr == 0) { /* gslq */
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if (!access_ok(addr, 16))
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goto sigbus;
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LoadDW(addr, value, res);
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if (res)
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goto fault;
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LoadDW(addr + 8, value_next, res);
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if (res)
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goto fault;
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regs->regs[insn.loongson3_lswc2_format.rt] = value;
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regs->regs[insn.loongson3_lswc2_format.rq] = value_next;
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compute_return_epc(regs);
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} else { /* gslqc1 */
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if (!access_ok(addr, 16))
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goto sigbus;
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lose_fpu(1);
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LoadDW(addr, value, res);
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if (res)
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goto fault;
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LoadDW(addr + 8, value_next, res);
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if (res)
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goto fault;
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set_fpr64(current->thread.fpu.fpr,
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insn.loongson3_lswc2_format.rt, value);
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set_fpr64(current->thread.fpu.fpr,
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insn.loongson3_lswc2_format.rq, value_next);
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compute_return_epc(regs);
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own_fpu(1);
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}
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return NOTIFY_STOP; /* Don't call default notifier */
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case CU2_SWC2_OP:
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if (insn.loongson3_lswc2_format.ls == 0)
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goto sigbus;
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if (insn.loongson3_lswc2_format.fr == 0) { /* gssq */
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if (!access_ok(addr, 16))
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goto sigbus;
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/* write upper 8 bytes first */
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value_next = regs->regs[insn.loongson3_lswc2_format.rq];
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StoreDW(addr + 8, value_next, res);
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if (res)
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goto fault;
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value = regs->regs[insn.loongson3_lswc2_format.rt];
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StoreDW(addr, value, res);
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if (res)
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goto fault;
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compute_return_epc(regs);
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} else { /* gssqc1 */
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if (!access_ok(addr, 16))
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goto sigbus;
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lose_fpu(1);
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value_next = get_fpr64(current->thread.fpu.fpr,
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insn.loongson3_lswc2_format.rq);
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StoreDW(addr + 8, value_next, res);
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if (res)
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goto fault;
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value = get_fpr64(current->thread.fpu.fpr,
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insn.loongson3_lswc2_format.rt);
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StoreDW(addr, value, res);
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if (res)
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goto fault;
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compute_return_epc(regs);
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own_fpu(1);
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}
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return NOTIFY_STOP; /* Don't call default notifier */
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case CU2_LDC2_OP:
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switch (insn.loongson3_lsdc2_format.opcode1) {
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/*
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* Loongson-3 overridden ldc2 instructions.
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* opcode1 instruction
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* 0x1 gslhx: load 2 bytes to GPR
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* 0x2 gslwx: load 4 bytes to GPR
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* 0x3 gsldx: load 8 bytes to GPR
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* 0x6 gslwxc1: load 4 bytes to FPR
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* 0x7 gsldxc1: load 8 bytes to FPR
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*/
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case 0x1:
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if (!access_ok(addr, 2))
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goto sigbus;
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LoadHW(addr, value, res);
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if (res)
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goto fault;
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compute_return_epc(regs);
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regs->regs[insn.loongson3_lsdc2_format.rt] = value;
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break;
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case 0x2:
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if (!access_ok(addr, 4))
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goto sigbus;
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LoadW(addr, value, res);
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if (res)
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goto fault;
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compute_return_epc(regs);
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regs->regs[insn.loongson3_lsdc2_format.rt] = value;
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break;
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case 0x3:
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if (!access_ok(addr, 8))
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goto sigbus;
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LoadDW(addr, value, res);
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if (res)
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goto fault;
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compute_return_epc(regs);
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regs->regs[insn.loongson3_lsdc2_format.rt] = value;
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break;
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case 0x6:
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die_if_kernel("Unaligned FP access in kernel code", regs);
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BUG_ON(!used_math());
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if (!access_ok(addr, 4))
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goto sigbus;
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lose_fpu(1);
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LoadW(addr, value, res);
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if (res)
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goto fault;
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set_fpr64(current->thread.fpu.fpr,
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insn.loongson3_lsdc2_format.rt, value);
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compute_return_epc(regs);
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own_fpu(1);
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break;
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case 0x7:
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die_if_kernel("Unaligned FP access in kernel code", regs);
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BUG_ON(!used_math());
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if (!access_ok(addr, 8))
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goto sigbus;
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lose_fpu(1);
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LoadDW(addr, value, res);
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if (res)
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goto fault;
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set_fpr64(current->thread.fpu.fpr,
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insn.loongson3_lsdc2_format.rt, value);
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compute_return_epc(regs);
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own_fpu(1);
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break;
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}
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return NOTIFY_STOP; /* Don't call default notifier */
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case CU2_SDC2_OP:
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switch (insn.loongson3_lsdc2_format.opcode1) {
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/*
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* Loongson-3 overridden sdc2 instructions.
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* opcode1 instruction
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* 0x1 gsshx: store 2 bytes from GPR
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* 0x2 gsswx: store 4 bytes from GPR
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* 0x3 gssdx: store 8 bytes from GPR
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* 0x6 gsswxc1: store 4 bytes from FPR
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* 0x7 gssdxc1: store 8 bytes from FPR
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*/
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case 0x1:
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if (!access_ok(addr, 2))
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goto sigbus;
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compute_return_epc(regs);
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value = regs->regs[insn.loongson3_lsdc2_format.rt];
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StoreHW(addr, value, res);
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if (res)
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goto fault;
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break;
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case 0x2:
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if (!access_ok(addr, 4))
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goto sigbus;
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compute_return_epc(regs);
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value = regs->regs[insn.loongson3_lsdc2_format.rt];
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StoreW(addr, value, res);
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if (res)
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goto fault;
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break;
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case 0x3:
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if (!access_ok(addr, 8))
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goto sigbus;
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compute_return_epc(regs);
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value = regs->regs[insn.loongson3_lsdc2_format.rt];
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StoreDW(addr, value, res);
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if (res)
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goto fault;
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break;
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case 0x6:
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die_if_kernel("Unaligned FP access in kernel code", regs);
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BUG_ON(!used_math());
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if (!access_ok(addr, 4))
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goto sigbus;
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lose_fpu(1);
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value = get_fpr64(current->thread.fpu.fpr,
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insn.loongson3_lsdc2_format.rt);
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StoreW(addr, value, res);
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if (res)
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goto fault;
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compute_return_epc(regs);
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own_fpu(1);
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break;
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case 0x7:
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die_if_kernel("Unaligned FP access in kernel code", regs);
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BUG_ON(!used_math());
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if (!access_ok(addr, 8))
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goto sigbus;
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lose_fpu(1);
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value = get_fpr64(current->thread.fpu.fpr,
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insn.loongson3_lsdc2_format.rt);
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StoreDW(addr, value, res);
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if (res)
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goto fault;
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compute_return_epc(regs);
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own_fpu(1);
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break;
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}
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return NOTIFY_STOP; /* Don't call default notifier */
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}
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return NOTIFY_OK; /* Let default notifier send signals */
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fault:
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/* roll back jump/branch */
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regs->regs[31] = ra;
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regs->cp0_epc = (unsigned long)pc;
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/* Did we have an exception handler installed? */
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if (fixup_exception(regs))
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return NOTIFY_STOP; /* Don't call default notifier */
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die_if_kernel("Unhandled kernel unaligned access", regs);
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force_sig(SIGSEGV);
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return NOTIFY_STOP; /* Don't call default notifier */
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sigbus:
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die_if_kernel("Unhandled kernel unaligned access", regs);
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force_sig(SIGBUS);
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return NOTIFY_STOP; /* Don't call default notifier */
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}
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static int __init loongson_cu2_setup(void)
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