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drm/amdgpu: Disable dpm_enabled flag while VF is in reset
VFs do not perform HW fini/suspend in FLR, so the dpm_enabled is incorrectly kept enabled. Add interface to disable it in virt_pre_reset call. v2: Made implementation generic for all asics v3: Re-order conditionals so PP_MP1_STATE_FLR is only evaluated on VF Signed-off-by: Victor Skvortsov <victor.skvortsov@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -5289,10 +5289,8 @@ int amdgpu_device_pre_asic_reset(struct amdgpu_device *adev,
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if (reset_context->reset_req_dev == adev)
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job = reset_context->job;
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if (amdgpu_sriov_vf(adev)) {
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/* stop the data exchange thread */
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amdgpu_virt_fini_data_exchange(adev);
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}
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if (amdgpu_sriov_vf(adev))
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amdgpu_virt_pre_reset(adev);
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amdgpu_fence_driver_isr_toggle(adev, true);
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@ -33,6 +33,7 @@
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#include "amdgpu.h"
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#include "amdgpu_ras.h"
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#include "amdgpu_reset.h"
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#include "amdgpu_dpm.h"
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#include "vi.h"
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#include "soc15.h"
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#include "nv.h"
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@ -849,6 +850,13 @@ enum amdgpu_sriov_vf_mode amdgpu_virt_get_sriov_vf_mode(struct amdgpu_device *ad
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return mode;
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}
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void amdgpu_virt_pre_reset(struct amdgpu_device *adev)
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{
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/* stop the data exchange thread */
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amdgpu_virt_fini_data_exchange(adev);
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amdgpu_dpm_set_mp1_state(adev, PP_MP1_STATE_FLR);
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}
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void amdgpu_virt_post_reset(struct amdgpu_device *adev)
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{
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if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(11, 0, 3)) {
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@ -376,6 +376,7 @@ u32 amdgpu_sriov_rreg(struct amdgpu_device *adev,
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u32 offset, u32 acc_flags, u32 hwip, u32 xcc_id);
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bool amdgpu_virt_fw_load_skip_check(struct amdgpu_device *adev,
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uint32_t ucode_id);
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void amdgpu_virt_pre_reset(struct amdgpu_device *adev);
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void amdgpu_virt_post_reset(struct amdgpu_device *adev);
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bool amdgpu_sriov_xnack_support(struct amdgpu_device *adev);
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bool amdgpu_virt_get_rlcg_reg_access_flag(struct amdgpu_device *adev,
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@ -218,6 +218,7 @@ enum pp_mp1_state {
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PP_MP1_STATE_SHUTDOWN,
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PP_MP1_STATE_UNLOAD,
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PP_MP1_STATE_RESET,
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PP_MP1_STATE_FLR,
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};
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enum pp_df_cstate {
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@ -168,7 +168,11 @@ int amdgpu_dpm_set_mp1_state(struct amdgpu_device *adev,
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int ret = 0;
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const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
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if (pp_funcs && pp_funcs->set_mp1_state) {
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if (mp1_state == PP_MP1_STATE_FLR) {
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/* VF lost access to SMU */
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if (amdgpu_sriov_vf(adev))
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adev->pm.dpm_enabled = false;
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} else if (pp_funcs && pp_funcs->set_mp1_state) {
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mutex_lock(&adev->pm.mutex);
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ret = pp_funcs->set_mp1_state(
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