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- Add new Intel CPU models
- Enforce that TDX guests are successfully loaded only on TDX hardware where virtualization exception (#VE) delivery on kernel memory is disabled because handling those in all possible cases is "essentially impossible" - Add the proper include to the syscall wrappers so that BTF can see the real pt_regs definition and not only the forward declaration -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEzv7L6UO9uDPlPSfHEsHwGGHeVUoFAmNnrUgACgkQEsHwGGHe VUoC2w//T6+5SlusY9uYIUpL/cGYj+888b/ysO0H0S37IVATUiI5m0eFAA+pcWON pzn81oBqk1Lstm7x/jT2mzxsZ2fIFbe6EA8hnLAexA4KY70oGhall9Q6O363CmFa DtUjd0LKjH6GkNH1RUcb5icJGVY3vZPCfSuxlYJUD66NBUx2pEF8l5hzZ0W20Yhq cHVY0i1HoCNNDRBOODrH7MEY/kWMSvhFybCYOfRMhoVd3aJhsLlq+7/7Ic5wabyy 2mE8b0GU8or9mluU51OiCDjp+qnpB+BTFjV+88ji5jNEKLIarAXkoHDDD06xLhOK a2L44zZ55RAFxxCBm9L10OE0ta3kUqpq+YKQkh0gGGdDdAylUp8IF0zXRl/6jRDC T76jM1QOvC791HWD6kDf5XizY+PeaVD9LzAREezG6778mZbNNQwOtkECHZF0U3UP n/NIabDlZIncuQQbT0sSshrIyfwtkH5E+epcyLuuchYUYnDGkvNkVU31ndiwFhUG fW8I53XBnIlk5PunJ0jhaq4+Tugr7APipUs75y8IpFEINj6gxuoSdXyezlQVpmQ+ tL1UXqxSlQaCoW295Fr19p3ZBBfqRKXSCS/toCluB/ekhP3ISzIZV7/cB1smmsIR JpgXQtcAMtXjIv9A1ZexQVlp2srk7Y6WrFocMNc47lKxmHZ78KY= =nqZp -----END PGP SIGNATURE----- Merge tag 'x86_urgent_for_v6.1_rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip Pull x86 fixes from Borislav Petkov: - Add new Intel CPU models - Enforce that TDX guests are successfully loaded only on TDX hardware where virtualization exception (#VE) delivery on kernel memory is disabled because handling those in all possible cases is "essentially impossible" - Add the proper include to the syscall wrappers so that BTF can see the real pt_regs definition and not only the forward declaration * tag 'x86_urgent_for_v6.1_rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: x86/cpu: Add several Intel server CPU model numbers x86/tdx: Panic on bad configs that #VE on "private" memory access x86/tdx: Prepare for using "INFO" call for a second purpose x86/syscall: Include asm/ptrace.h in syscall_wrapper header
This commit is contained in:
Linus Torvalds
commit
f6f5204727
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@ -34,6 +34,8 @@
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#define VE_GET_PORT_NUM(e) ((e) >> 16)
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#define VE_IS_IO_STRING(e) ((e) & BIT(4))
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#define ATTR_SEPT_VE_DISABLE BIT(28)
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/*
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* Wrapper for standard use of __tdx_hypercall with no output aside from
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* return code.
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@ -98,10 +100,11 @@ static inline void tdx_module_call(u64 fn, u64 rcx, u64 rdx, u64 r8, u64 r9,
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panic("TDCALL %lld failed (Buggy TDX module!)\n", fn);
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}
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static u64 get_cc_mask(void)
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static void tdx_parse_tdinfo(u64 *cc_mask)
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{
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struct tdx_module_output out;
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unsigned int gpa_width;
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u64 td_attr;
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/*
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* TDINFO TDX module call is used to get the TD execution environment
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@ -109,19 +112,27 @@ static u64 get_cc_mask(void)
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* information, etc. More details about the ABI can be found in TDX
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* Guest-Host-Communication Interface (GHCI), section 2.4.2 TDCALL
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* [TDG.VP.INFO].
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*
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* The GPA width that comes out of this call is critical. TDX guests
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* can not meaningfully run without it.
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*/
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tdx_module_call(TDX_GET_INFO, 0, 0, 0, 0, &out);
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gpa_width = out.rcx & GENMASK(5, 0);
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/*
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* The highest bit of a guest physical address is the "sharing" bit.
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* Set it for shared pages and clear it for private pages.
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*
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* The GPA width that comes out of this call is critical. TDX guests
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* can not meaningfully run without it.
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*/
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return BIT_ULL(gpa_width - 1);
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gpa_width = out.rcx & GENMASK(5, 0);
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*cc_mask = BIT_ULL(gpa_width - 1);
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/*
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* The kernel can not handle #VE's when accessing normal kernel
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* memory. Ensure that no #VE will be delivered for accesses to
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* TD-private memory. Only VMM-shared memory (MMIO) will #VE.
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*/
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td_attr = out.rdx;
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if (!(td_attr & ATTR_SEPT_VE_DISABLE))
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panic("TD misconfiguration: SEPT_VE_DISABLE attibute must be set.\n");
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}
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/*
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@ -758,7 +769,7 @@ void __init tdx_early_init(void)
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setup_force_cpu_cap(X86_FEATURE_TDX_GUEST);
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cc_set_vendor(CC_VENDOR_INTEL);
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cc_mask = get_cc_mask();
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tdx_parse_tdinfo(&cc_mask);
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cc_set_mask(cc_mask);
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/*
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@ -107,6 +107,11 @@
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#define INTEL_FAM6_SAPPHIRERAPIDS_X 0x8F /* Golden Cove */
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#define INTEL_FAM6_EMERALDRAPIDS_X 0xCF
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#define INTEL_FAM6_GRANITERAPIDS_X 0xAD
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#define INTEL_FAM6_GRANITERAPIDS_D 0xAE
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#define INTEL_FAM6_ALDERLAKE 0x97 /* Golden Cove / Gracemont */
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#define INTEL_FAM6_ALDERLAKE_L 0x9A /* Golden Cove / Gracemont */
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#define INTEL_FAM6_ALDERLAKE_N 0xBE
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@ -118,7 +123,7 @@
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#define INTEL_FAM6_METEORLAKE 0xAC
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#define INTEL_FAM6_METEORLAKE_L 0xAA
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/* "Small Core" Processors (Atom) */
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/* "Small Core" Processors (Atom/E-Core) */
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#define INTEL_FAM6_ATOM_BONNELL 0x1C /* Diamondville, Pineview */
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#define INTEL_FAM6_ATOM_BONNELL_MID 0x26 /* Silverthorne, Lincroft */
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@ -145,6 +150,10 @@
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#define INTEL_FAM6_ATOM_TREMONT 0x96 /* Elkhart Lake */
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#define INTEL_FAM6_ATOM_TREMONT_L 0x9C /* Jasper Lake */
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#define INTEL_FAM6_SIERRAFOREST_X 0xAF
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#define INTEL_FAM6_GRANDRIDGE 0xB6
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/* Xeon Phi */
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#define INTEL_FAM6_XEON_PHI_KNL 0x57 /* Knights Landing */
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@ -6,7 +6,7 @@
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#ifndef _ASM_X86_SYSCALL_WRAPPER_H
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#define _ASM_X86_SYSCALL_WRAPPER_H
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struct pt_regs;
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#include <asm/ptrace.h>
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extern long __x64_sys_ni_syscall(const struct pt_regs *regs);
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extern long __ia32_sys_ni_syscall(const struct pt_regs *regs);
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