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pwm: rockchip: Added to support for RK3288 SoC
This patch added to support the PWM controller found on RK3288 SoC. Signed-off-by: Caesar Wang <caesar.wang@rock-chips.com> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
This commit is contained in:
Caesar Wang
Thierry Reding
parent
695d49d941
commit
f630629908
@ -2,6 +2,7 @@
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* PWM driver for Rockchip SoCs
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*
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* Copyright (C) 2014 Beniamino Galvani <b.galvani@gmail.com>
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* Copyright (C) 2014 ROCKCHIP, Inc.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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@ -12,30 +13,81 @@
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/pwm.h>
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#include <linux/time.h>
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#define PWM_CNTR 0x00 /* Counter register */
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#define PWM_HRC 0x04 /* High reference register */
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#define PWM_LRC 0x08 /* Low reference register */
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#define PWM_CTRL 0x0c /* Control register */
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#define PWM_CTRL_TIMER_EN (1 << 0)
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#define PWM_CTRL_OUTPUT_EN (1 << 3)
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#define PRESCALER 2
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#define PWM_ENABLE (1 << 0)
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#define PWM_CONTINUOUS (1 << 1)
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#define PWM_DUTY_POSITIVE (1 << 3)
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#define PWM_INACTIVE_NEGATIVE (0 << 4)
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#define PWM_OUTPUT_LEFT (0 << 5)
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#define PWM_LP_DISABLE (0 << 8)
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struct rockchip_pwm_chip {
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struct pwm_chip chip;
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struct clk *clk;
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const struct rockchip_pwm_data *data;
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void __iomem *base;
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};
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struct rockchip_pwm_regs {
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unsigned long duty;
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unsigned long period;
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unsigned long cntr;
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unsigned long ctrl;
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};
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struct rockchip_pwm_data {
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struct rockchip_pwm_regs regs;
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unsigned int prescaler;
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void (*set_enable)(struct pwm_chip *chip, bool enable);
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};
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static inline struct rockchip_pwm_chip *to_rockchip_pwm_chip(struct pwm_chip *c)
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{
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return container_of(c, struct rockchip_pwm_chip, chip);
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}
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static void rockchip_pwm_set_enable_v1(struct pwm_chip *chip, bool enable)
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{
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struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip);
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u32 enable_conf = PWM_CTRL_OUTPUT_EN | PWM_CTRL_TIMER_EN;
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u32 val;
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val = readl_relaxed(pc->base + pc->data->regs.ctrl);
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if (enable)
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val |= enable_conf;
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else
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val &= ~enable_conf;
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writel_relaxed(val, pc->base + pc->data->regs.ctrl);
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}
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static void rockchip_pwm_set_enable_v2(struct pwm_chip *chip, bool enable)
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{
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struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip);
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u32 enable_conf = PWM_OUTPUT_LEFT | PWM_LP_DISABLE | PWM_ENABLE |
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PWM_CONTINUOUS | PWM_DUTY_POSITIVE |
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PWM_INACTIVE_NEGATIVE;
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u32 val;
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val = readl_relaxed(pc->base + pc->data->regs.ctrl);
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if (enable)
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val |= enable_conf;
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else
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val &= ~enable_conf;
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writel_relaxed(val, pc->base + pc->data->regs.ctrl);
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}
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static int rockchip_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
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int duty_ns, int period_ns)
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{
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@ -52,20 +104,20 @@ static int rockchip_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
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* default prescaler value for all practical clock rate values.
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*/
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div = clk_rate * period_ns;
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do_div(div, PRESCALER * NSEC_PER_SEC);
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do_div(div, pc->data->prescaler * NSEC_PER_SEC);
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period = div;
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div = clk_rate * duty_ns;
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do_div(div, PRESCALER * NSEC_PER_SEC);
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do_div(div, pc->data->prescaler * NSEC_PER_SEC);
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duty = div;
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ret = clk_enable(pc->clk);
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if (ret)
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return ret;
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writel(period, pc->base + PWM_LRC);
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writel(duty, pc->base + PWM_HRC);
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writel(0, pc->base + PWM_CNTR);
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writel(period, pc->base + pc->data->regs.period);
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writel(duty, pc->base + pc->data->regs.duty);
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writel(0, pc->base + pc->data->regs.cntr);
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clk_disable(pc->clk);
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@ -76,15 +128,12 @@ static int rockchip_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
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{
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struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip);
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int ret;
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u32 val;
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ret = clk_enable(pc->clk);
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if (ret)
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return ret;
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val = readl_relaxed(pc->base + PWM_CTRL);
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val |= PWM_CTRL_OUTPUT_EN | PWM_CTRL_TIMER_EN;
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writel_relaxed(val, pc->base + PWM_CTRL);
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pc->data->set_enable(chip, true);
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return 0;
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}
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@ -92,11 +141,8 @@ static int rockchip_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
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static void rockchip_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
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{
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struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip);
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u32 val;
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val = readl_relaxed(pc->base + PWM_CTRL);
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val &= ~(PWM_CTRL_OUTPUT_EN | PWM_CTRL_TIMER_EN);
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writel_relaxed(val, pc->base + PWM_CTRL);
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pc->data->set_enable(chip, false);
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clk_disable(pc->clk);
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}
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@ -108,12 +154,58 @@ static const struct pwm_ops rockchip_pwm_ops = {
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.owner = THIS_MODULE,
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};
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static const struct rockchip_pwm_data pwm_data_v1 = {
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.regs = {
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.duty = 0x04,
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.period = 0x08,
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.cntr = 0x00,
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.ctrl = 0x0c,
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},
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.prescaler = 2,
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.set_enable = rockchip_pwm_set_enable_v1,
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};
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static const struct rockchip_pwm_data pwm_data_v2 = {
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.regs = {
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.duty = 0x08,
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.period = 0x04,
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.cntr = 0x00,
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.ctrl = 0x0c,
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},
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.prescaler = 1,
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.set_enable = rockchip_pwm_set_enable_v2,
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};
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static const struct rockchip_pwm_data pwm_data_vop = {
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.regs = {
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.duty = 0x08,
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.period = 0x04,
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.cntr = 0x0c,
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.ctrl = 0x00,
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},
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.prescaler = 1,
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.set_enable = rockchip_pwm_set_enable_v2,
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};
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static const struct of_device_id rockchip_pwm_dt_ids[] = {
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{ .compatible = "rockchip,rk2928-pwm", .data = &pwm_data_v1},
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{ .compatible = "rockchip,rk3288-pwm", .data = &pwm_data_v2},
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{ .compatible = "rockchip,vop-pwm", .data = &pwm_data_vop},
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{ /* sentinel */ }
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};
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MODULE_DEVICE_TABLE(of, rockchip_pwm_dt_ids);
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static int rockchip_pwm_probe(struct platform_device *pdev)
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{
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const struct of_device_id *id;
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struct rockchip_pwm_chip *pc;
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struct resource *r;
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int ret;
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id = of_match_device(rockchip_pwm_dt_ids, &pdev->dev);
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if (!id)
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return -EINVAL;
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pc = devm_kzalloc(&pdev->dev, sizeof(*pc), GFP_KERNEL);
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if (!pc)
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return -ENOMEM;
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@ -133,6 +225,7 @@ static int rockchip_pwm_probe(struct platform_device *pdev)
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platform_set_drvdata(pdev, pc);
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pc->data = id->data;
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pc->chip.dev = &pdev->dev;
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pc->chip.ops = &rockchip_pwm_ops;
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pc->chip.base = -1;
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@ -156,12 +249,6 @@ static int rockchip_pwm_remove(struct platform_device *pdev)
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return pwmchip_remove(&pc->chip);
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}
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static const struct of_device_id rockchip_pwm_dt_ids[] = {
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{ .compatible = "rockchip,rk2928-pwm" },
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{ /* sentinel */ }
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};
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MODULE_DEVICE_TABLE(of, rockchip_pwm_dt_ids);
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static struct platform_driver rockchip_pwm_driver = {
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.driver = {
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.name = "rockchip-pwm",
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