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ARM: cti: fix manipulation of debug lock registers

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The LOCKSTATUS register for memory-mapped coresight devices indicates
whether or not the device in question implements hardware locking. If
not, locking is not present (i.e. LSR.SLI == 0) and LAR is write-ignore,
so software doesn't actually need to check the status register at all.

This patch removes the broken LSR checks.

Cc: Ming Lei <ming.lei@canonical.com>
Reported-by: Mike Williams <michael.williams@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
This commit is contained in:
Will Deacon 2012-11-15 21:28:43 +00:00
parent f435ab7992
commit f600b9fcd2
1 changed files with 2 additions and 18 deletions
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20
arch/arm/include/asm/cti.h
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@ -146,15 +146,7 @@ static inline void cti_irq_ack(struct cti *cti)
*/
static inline void cti_unlock(struct cti *cti)
{
void __iomem *base = cti->base;
unsigned long val;
val = __raw_readl(base + LOCKSTATUS);
if (val & 1) {
val = LOCKCODE;
__raw_writel(val, base + LOCKACCESS);
}
__raw_writel(LOCKCODE, cti->base + LOCKACCESS);
}
/**
@ -166,14 +158,6 @@ static inline void cti_unlock(struct cti *cti)
*/
static inline void cti_lock(struct cti *cti)
{
void __iomem *base = cti->base;
unsigned long val;
val = __raw_readl(base + LOCKSTATUS);
if (!(val & 1)) {
val = ~LOCKCODE;
__raw_writel(val, base + LOCKACCESS);
}
__raw_writel(~LOCKCODE, cti->base + LOCKACCESS);
}
#endif