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[media] media_tree: Fix spelling errors
Fix various spelling errors in strings and comments throughout the media tree. The majority of these were found using Lucas De Marchi's codespell tool. [m.chehab@samsung.com: discard hunks with conflicts] Signed-off-by: Jonathan McCrohan <jmccrohan@gmail.com> Signed-off-by: Hans Verkuil <hans.verkuil@cisco.com> Signed-off-by: Mauro Carvalho Chehab <m.chehab@samsung.com>
This commit is contained in:
Jonathan McCrohan
Mauro Carvalho Chehab
parent
c1b96a236e
commit
f58c91ce82
@ -955,7 +955,7 @@ struct sms_rx_stats {
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u32 modem_state; /* from SMSHOSTLIB_DVB_MODEM_STATE_ET */
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s32 SNR; /* dB */
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u32 ber; /* Post Viterbi ber [1E-5] */
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u32 ber_error_count; /* Number of erronous SYNC bits. */
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u32 ber_error_count; /* Number of erroneous SYNC bits. */
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u32 ber_bit_count; /* Total number of SYNC bits. */
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u32 ts_per; /* Transport stream PER,
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0xFFFFFFFF indicate N/A */
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@ -981,7 +981,7 @@ struct sms_rx_stats_ex {
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u32 modem_state; /* from SMSHOSTLIB_DVB_MODEM_STATE_ET */
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s32 SNR; /* dB */
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u32 ber; /* Post Viterbi ber [1E-5] */
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u32 ber_error_count; /* Number of erronous SYNC bits. */
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u32 ber_error_count; /* Number of erroneous SYNC bits. */
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u32 ber_bit_count; /* Total number of SYNC bits. */
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u32 ts_per; /* Transport stream PER,
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0xFFFFFFFF indicate N/A */
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@ -95,7 +95,7 @@ struct RECEPTION_STATISTICS_PER_SLICES_S {
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u32 is_demod_locked; /* 0 - not locked, 1 - locked */
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u32 ber_bit_count; /* Total number of SYNC bits. */
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u32 ber_error_count; /* Number of erronous SYNC bits. */
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u32 ber_error_count; /* Number of erroneous SYNC bits. */
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s32 MRC_SNR; /* dB */
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s32 mrc_in_band_pwr; /* In band power in dBM */
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@ -435,7 +435,7 @@ static void dvb_dmx_swfilter_packet(struct dvb_demux *demux, const u8 *buf)
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dprintk_tscheck("TEI detected. "
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"PID=0x%x data1=0x%x\n",
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pid, buf[1]);
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/* data in this packet cant be trusted - drop it unless
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/* data in this packet can't be trusted - drop it unless
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* module option dvb_demux_feed_err_pkts is set */
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if (!dvb_demux_feed_err_pkts)
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return;
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@ -3048,7 +3048,7 @@ static int dib8000_tune(struct dvb_frontend *fe)
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dib8000_set_diversity_in(state->fe[0], state->diversity_onoff);
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locks = (dib8000_read_word(state, 180) >> 6) & 0x3f; /* P_coff_winlen ? */
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/* coff should lock over P_coff_winlen ofdm symbols : give 3 times this lenght to lock */
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/* coff should lock over P_coff_winlen ofdm symbols : give 3 times this length to lock */
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*timeout = dib8000_get_timeout(state, 2 * locks, SYMBOL_DEPENDENT_ON);
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*tune_state = CT_DEMOD_STEP_5;
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break;
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@ -3115,7 +3115,7 @@ static int dib8000_tune(struct dvb_frontend *fe)
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case CT_DEMOD_STEP_9: /* 39 */
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if ((state->revision == 0x8090) || ((dib8000_read_word(state, 1291) >> 9) & 0x1)) { /* fe capable of deinterleaving : esram */
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/* defines timeout for mpeg lock depending on interleaver lenght of longest layer */
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/* defines timeout for mpeg lock depending on interleaver length of longest layer */
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for (i = 0; i < 3; i++) {
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if (c->layer[i].interleaving >= deeper_interleaver) {
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dprintk("layer%i: time interleaver = %d ", i, c->layer[i].interleaving);
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@ -1191,7 +1191,7 @@ static int mpegts_configure_pins(struct drxk_state *state, bool mpeg_enable)
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goto error;
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if (state->m_enable_parallel == true) {
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/* paralel -> enable MD1 to MD7 */
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/* parallel -> enable MD1 to MD7 */
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status = write16(state, SIO_PDR_MD1_CFG__A,
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sio_pdr_mdx_cfg);
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if (status < 0)
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@ -1428,7 +1428,7 @@ static int mpegts_stop(struct drxk_state *state)
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dprintk(1, "\n");
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/* Gracefull shutdown (byte boundaries) */
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/* Graceful shutdown (byte boundaries) */
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status = read16(state, FEC_OC_SNC_MODE__A, &fec_oc_snc_mode);
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if (status < 0)
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goto error;
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@ -2021,7 +2021,7 @@ static int mpegts_dto_setup(struct drxk_state *state,
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fec_oc_dto_burst_len = 204;
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}
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/* Check serial or parrallel output */
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/* Check serial or parallel output */
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fec_oc_reg_ipr_mode &= (~(FEC_OC_IPR_MODE_SERIAL__M));
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if (state->m_enable_parallel == false) {
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/* MPEG data output is serial -> set ipr_mode[0] */
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@ -2908,7 +2908,7 @@ static int adc_synchronization(struct drxk_state *state)
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goto error;
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if (count == 1) {
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/* Try sampling on a diffrent edge */
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/* Try sampling on a different edge */
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u16 clk_neg = 0;
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status = read16(state, IQM_AF_CLKNEG__A, &clk_neg);
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@ -3306,7 +3306,7 @@ static int dvbt_sc_command(struct drxk_state *state,
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if (status < 0)
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goto error;
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/* Retreive results parameters from SC */
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/* Retrieve results parameters from SC */
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switch (cmd) {
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/* All commands yielding 5 results */
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/* All commands yielding 4 results */
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@ -3849,7 +3849,7 @@ static int set_dvbt(struct drxk_state *state, u16 intermediate_freqk_hz,
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break;
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}
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#if 0
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/* No hierachical channels support in BDA */
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/* No hierarchical channels support in BDA */
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/* Priority (only for hierarchical channels) */
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switch (channel->priority) {
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case DRX_PRIORITY_LOW:
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@ -4081,7 +4081,7 @@ error:
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/*============================================================================*/
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/**
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* \brief Retreive lock status .
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* \brief Retrieve lock status .
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* \param demod Pointer to demodulator instance.
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* \param lockStat Pointer to lock status structure.
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* \return DRXStatus_t.
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@ -6174,7 +6174,7 @@ static int init_drxk(struct drxk_state *state)
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goto error;
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/* Stamp driver version number in SCU data RAM in BCD code
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Done to enable field application engineers to retreive drxdriver version
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Done to enable field application engineers to retrieve drxdriver version
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via I2C from SCU RAM.
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Not using SCU command interface for SCU register access since no
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microcode may be present.
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@ -6399,7 +6399,7 @@ static int drxk_set_parameters(struct dvb_frontend *fe)
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fe->ops.tuner_ops.get_if_frequency(fe, &IF);
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start(state, 0, IF);
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/* After set_frontend, stats aren't avaliable */
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/* After set_frontend, stats aren't available */
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p->strength.stat[0].scale = FE_SCALE_RELATIVE;
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p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
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p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
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@ -52,9 +52,9 @@
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#define ADV7183_VS_FIELD_CTRL_1 0x31 /* Vsync field control 1 */
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#define ADV7183_VS_FIELD_CTRL_2 0x32 /* Vsync field control 2 */
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#define ADV7183_VS_FIELD_CTRL_3 0x33 /* Vsync field control 3 */
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#define ADV7183_HS_POS_CTRL_1 0x34 /* Hsync positon control 1 */
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#define ADV7183_HS_POS_CTRL_2 0x35 /* Hsync positon control 2 */
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#define ADV7183_HS_POS_CTRL_3 0x36 /* Hsync positon control 3 */
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#define ADV7183_HS_POS_CTRL_1 0x34 /* Hsync position control 1 */
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#define ADV7183_HS_POS_CTRL_2 0x35 /* Hsync position control 2 */
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#define ADV7183_HS_POS_CTRL_3 0x36 /* Hsync position control 3 */
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#define ADV7183_POLARITY 0x37 /* Polarity */
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#define ADV7183_NTSC_COMB_CTRL 0x38 /* NTSC comb control */
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#define ADV7183_PAL_COMB_CTRL 0x39 /* PAL comb control */
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@ -877,7 +877,7 @@ static void configure_custom_video_timings(struct v4l2_subdev *sd,
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break;
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case ADV7604_MODE_HDMI:
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/* set default prim_mode/vid_std for HDMI
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accoring to [REF_03, c. 4.2] */
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according to [REF_03, c. 4.2] */
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io_write(sd, 0x00, 0x02); /* video std */
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io_write(sd, 0x01, 0x06); /* prim mode */
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break;
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@ -1013,7 +1013,7 @@ static void configure_custom_video_timings(struct v4l2_subdev *sd,
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break;
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case ADV7842_MODE_HDMI:
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/* set default prim_mode/vid_std for HDMI
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accoring to [REF_03, c. 4.2] */
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according to [REF_03, c. 4.2] */
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io_write(sd, 0x00, 0x02); /* video std */
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io_write(sd, 0x01, 0x06); /* prim mode */
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break;
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@ -394,7 +394,7 @@ static int ir_probe(struct i2c_client *client, const struct i2c_device_id *id)
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if (!rc) {
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/*
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* If platform_data doesn't specify rc_dev, initilize it
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* If platform_data doesn't specify rc_dev, initialize it
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* internally
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*/
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rc = rc_allocate_device();
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@ -544,7 +544,7 @@ int m5mols_init_controls(struct v4l2_subdev *sd)
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u16 zoom_step;
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int ret;
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/* Determine the firmware dependant control range and step values */
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/* Determine the firmware dependent control range and step values */
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ret = m5mols_read_u16(sd, AE_MAX_GAIN_MON, &exposure_max);
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if (ret < 0)
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return ret;
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@ -1460,7 +1460,7 @@ static int s5c73m3_oif_registered(struct v4l2_subdev *sd)
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mutex_unlock(&state->lock);
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v4l2_dbg(1, s5c73m3_dbg, sd, "%s: Booting %s (%d)\n",
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__func__, ret ? "failed" : "succeded", ret);
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__func__, ret ? "failed" : "succeeded", ret);
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return ret;
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}
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@ -393,7 +393,7 @@ struct s5c73m3 {
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/* External master clock frequency */
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u32 mclk_frequency;
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/* Video bus type - MIPI-CSI2/paralell */
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/* Video bus type - MIPI-CSI2/parallel */
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enum v4l2_mbus_type bus_type;
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const struct s5c73m3_frame_size *sensor_pix_size[2];
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@ -1699,7 +1699,7 @@ static void saa711x_write_platform_data(struct saa711x_state *state,
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* the analog demod.
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* If the tuner is not found, it returns -ENODEV.
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* If auto-detection is disabled and the tuner doesn't match what it was
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* requred, it returns -EINVAL and fills 'name'.
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* required, it returns -EINVAL and fills 'name'.
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* If the chip is found, it returns the chip ID and fills 'name'.
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*/
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static int saa711x_detect_chip(struct i2c_client *client,
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@ -642,7 +642,7 @@ static const struct ov5642_datafmt
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static int reg_read(struct i2c_client *client, u16 reg, u8 *val)
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{
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int ret;
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/* We have 16-bit i2c addresses - care for endianess */
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/* We have 16-bit i2c addresses - care for endianness */
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unsigned char data[2] = { reg >> 8, reg & 0xff };
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ret = i2c_master_send(client, data, 2);
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@ -262,7 +262,7 @@ struct cx18_options {
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};
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/* per-mdl bit flags */
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#define CX18_F_M_NEED_SWAP 0 /* mdl buffer data must be endianess swapped */
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#define CX18_F_M_NEED_SWAP 0 /* mdl buffer data must be endianness swapped */
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/* per-stream, s_flags */
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#define CX18_F_S_CLAIMED 3 /* this stream is claimed */
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@ -427,7 +427,7 @@ int mc417_register_read(struct cx23885_dev *dev, u16 address, u32 *value)
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cx_write(MC417_RWD, regval);
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/* Transition RD to effect read transaction across bus.
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* Transtion 0x5000 -> 0x9000 correct (RD/RDY -> WR/RDY)?
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* Transition 0x5000 -> 0x9000 correct (RD/RDY -> WR/RDY)?
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* Should it be 0x9000 -> 0xF000 (also why is RDY being set, its
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* input only...)
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*/
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@ -401,7 +401,7 @@ static int pluto_hw_init(struct pluto *pluto)
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/* set automatic LED control by FPGA */
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pluto_rw(pluto, REG_MISC, MISC_ALED, MISC_ALED);
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/* set data endianess */
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/* set data endianness */
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#ifdef __LITTLE_ENDIAN
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pluto_rw(pluto, REG_PIDn(0), PID0_END, PID0_END);
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#else
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@ -1434,7 +1434,7 @@ static void coda_buf_queue(struct vb2_buffer *vb)
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if (q_data->fourcc == V4L2_PIX_FMT_H264 &&
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vb->vb2_queue->type == V4L2_BUF_TYPE_VIDEO_OUTPUT) {
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/*
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* For backwards compatiblity, queuing an empty buffer marks
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* For backwards compatibility, queuing an empty buffer marks
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* the stream end
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*/
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if (vb2_get_plane_payload(vb, 0) == 0)
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@ -1039,7 +1039,7 @@ static int fimc_runtime_resume(struct device *dev)
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dbg("fimc%d: state: 0x%lx", fimc->id, fimc->state);
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/* Enable clocks and perform basic initalization */
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/* Enable clocks and perform basic initialization */
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clk_enable(fimc->clock[CLK_GATE]);
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fimc_hw_reset(fimc);
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@ -759,7 +759,7 @@ static int fimc_md_register_platform_entity(struct fimc_md *fmd,
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goto dev_unlock;
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drvdata = dev_get_drvdata(dev);
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/* Some subdev didn't probe succesfully id drvdata is NULL */
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/* Some subdev didn't probe successfully id drvdata is NULL */
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if (drvdata) {
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switch (plat_entity) {
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case IDX_FIMC:
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@ -1673,7 +1673,7 @@ void omap3isp_print_status(struct isp_device *isp)
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* ISP clocks get disabled in suspend(). Similarly, the clocks are reenabled in
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* resume(), and the the pipelines are restarted in complete().
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*
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* TODO: PM dependencies between the ISP and sensors are not modeled explicitly
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* TODO: PM dependencies between the ISP and sensors are not modelled explicitly
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* yet.
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*/
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static int isp_pm_prepare(struct device *dev)
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@ -382,7 +382,7 @@
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#define S5P_FIMV_R2H_CMD_EDFU_INIT_RET 16
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#define S5P_FIMV_R2H_CMD_ERR_RET 32
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/* Dummy definition for MFCv6 compatibilty */
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/* Dummy definition for MFCv6 compatibility */
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#define S5P_FIMV_CODEC_H264_MVC_DEC -1
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#define S5P_FIMV_R2H_CMD_FIELD_DONE_RET -1
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#define S5P_FIMV_MFC_RESET -1
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@ -239,7 +239,7 @@ static void s5p_mfc_handle_frame_copy_time(struct s5p_mfc_ctx *ctx)
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frame_type = s5p_mfc_hw_call(dev->mfc_ops, get_dec_frame_type, dev);
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/* Copy timestamp / timecode from decoded src to dst and set
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appropraite flags */
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appropriate flags */
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src_buf = list_entry(ctx->src_queue.next, struct s5p_mfc_buf, list);
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list_for_each_entry(dst_buf, &ctx->dst_queue, list) {
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if (vb2_dma_contig_plane_dma_addr(dst_buf->b, 0) == dec_y_addr) {
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@ -428,7 +428,7 @@ static void s5p_mfc_handle_error(struct s5p_mfc_dev *dev,
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case MFCINST_FINISHING:
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case MFCINST_FINISHED:
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case MFCINST_RUNNING:
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/* It is higly probable that an error occured
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/* It is highly probable that an error occurred
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* while decoding a frame */
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clear_work_bit(ctx);
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ctx->state = MFCINST_ERROR;
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@ -611,7 +611,7 @@ static irqreturn_t s5p_mfc_irq(int irq, void *priv)
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mfc_debug(1, "Int reason: %d (err: %08x)\n", reason, err);
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switch (reason) {
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case S5P_MFC_R2H_CMD_ERR_RET:
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/* An error has occured */
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/* An error has occurred */
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if (ctx->state == MFCINST_RUNNING &&
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s5p_mfc_hw_call(dev->mfc_ops, err_dec, err) >=
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dev->warn_start)
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@ -840,7 +840,7 @@ static int s5p_mfc_open(struct file *file)
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mutex_unlock(&dev->mfc_mutex);
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mfc_debug_leave();
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return ret;
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/* Deinit when failure occured */
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/* Deinit when failure occurred */
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err_queue_init:
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if (dev->num_inst == 1)
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s5p_mfc_deinit_hw(dev);
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@ -881,14 +881,14 @@ static int s5p_mfc_release(struct file *file)
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/* Mark context as idle */
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clear_work_bit_irqsave(ctx);
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/* If instance was initialised then
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* return instance and free reosurces */
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* return instance and free resources */
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if (ctx->inst_no != MFC_NO_INSTANCE_SET) {
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mfc_debug(2, "Has to free instance\n");
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ctx->state = MFCINST_RETURN_INST;
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set_work_bit_irqsave(ctx);
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s5p_mfc_clean_ctx_int_flags(ctx);
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s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
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/* Wait until instance is returned or timeout occured */
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/* Wait until instance is returned or timeout occurred */
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if (s5p_mfc_wait_for_done_ctx
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(ctx, S5P_MFC_R2H_CMD_CLOSE_INSTANCE_RET, 0)) {
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s5p_mfc_clock_off();
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@ -69,7 +69,7 @@ int s5p_mfc_alloc_firmware(struct s5p_mfc_dev *dev)
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} else {
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/* In this case bank2 can point to the same address as bank1.
|
||||
* Firmware will always occupy the beggining of this area so it is
|
||||
* Firmware will always occupy the beginning of this area so it is
|
||||
* impossible having a video frame buffer with zero address. */
|
||||
dev->bank2 = dev->bank1;
|
||||
}
|
||||
|
||||
@ -65,7 +65,7 @@ struct mxr_format {
|
||||
int num_subframes;
|
||||
/** specifies to which subframe belong given plane */
|
||||
int plane2subframe[MXR_MAX_PLANES];
|
||||
/** internal code, driver dependant */
|
||||
/** internal code, driver dependent */
|
||||
unsigned long cookie;
|
||||
};
|
||||
|
||||
|
||||
@ -528,7 +528,7 @@ static int mxr_s_dv_timings(struct file *file, void *fh,
|
||||
mutex_lock(&mdev->mutex);
|
||||
|
||||
/* timings change cannot be done while there is an entity
|
||||
* dependant on output configuration
|
||||
* dependent on output configuration
|
||||
*/
|
||||
if (mdev->n_output > 0) {
|
||||
mutex_unlock(&mdev->mutex);
|
||||
@ -585,7 +585,7 @@ static int mxr_s_std(struct file *file, void *fh, v4l2_std_id norm)
|
||||
mutex_lock(&mdev->mutex);
|
||||
|
||||
/* standard change cannot be done while there is an entity
|
||||
* dependant on output configuration
|
||||
* dependent on output configuration
|
||||
*/
|
||||
if (mdev->n_output > 0) {
|
||||
mutex_unlock(&mdev->mutex);
|
||||
|
||||
@ -1495,7 +1495,7 @@ static int omap1_cam_set_bus_param(struct soc_camera_device *icd)
|
||||
if (ctrlclock & LCLK_EN)
|
||||
CAM_WRITE(pcdev, CTRLCLOCK, ctrlclock);
|
||||
|
||||
/* select bus endianess */
|
||||
/* select bus endianness */
|
||||
xlate = soc_camera_xlate_by_fourcc(icd, pixfmt);
|
||||
fmt = xlate->host_fmt;
|
||||
|
||||
|
||||
@ -1108,7 +1108,7 @@ static int vidioc_s_input(struct file *file, void *priv, unsigned int i)
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* timeperframe is arbitrary and continous */
|
||||
/* timeperframe is arbitrary and continuous */
|
||||
static int vidioc_enum_frameintervals(struct file *file, void *priv,
|
||||
struct v4l2_frmivalenum *fival)
|
||||
{
|
||||
@ -1125,7 +1125,7 @@ static int vidioc_enum_frameintervals(struct file *file, void *priv,
|
||||
|
||||
fival->type = V4L2_FRMIVAL_TYPE_CONTINUOUS;
|
||||
|
||||
/* fill in stepwise (step=1.0 is requred by V4L2 spec) */
|
||||
/* fill in stepwise (step=1.0 is required by V4L2 spec) */
|
||||
fival->stepwise.min = tpf_min;
|
||||
fival->stepwise.max = tpf_max;
|
||||
fival->stepwise.step = (struct v4l2_fract) {1, 1};
|
||||
|
||||
@ -323,7 +323,7 @@ static void vsp1_clocks_disable(struct vsp1_device *vsp1)
|
||||
* Increment the VSP1 reference count and initialize the device if the first
|
||||
* reference is taken.
|
||||
*
|
||||
* Return a pointer to the VSP1 device or NULL if an error occured.
|
||||
* Return a pointer to the VSP1 device or NULL if an error occurred.
|
||||
*/
|
||||
struct vsp1_device *vsp1_device_get(struct vsp1_device *vsp1)
|
||||
{
|
||||
|
||||
@ -268,8 +268,8 @@ struct si476x_radio;
|
||||
*
|
||||
* @tune_freq: Tune chip to a specific frequency
|
||||
* @seek_start: Star station seeking
|
||||
* @rsq_status: Get Recieved Signal Quality(RSQ) status
|
||||
* @rds_blckcnt: Get recived RDS blocks count
|
||||
* @rsq_status: Get Received Signal Quality(RSQ) status
|
||||
* @rds_blckcnt: Get received RDS blocks count
|
||||
* @phase_diversity: Change phase diversity mode of the tuner
|
||||
* @phase_div_status: Get phase diversity mode status
|
||||
* @acf_status: Get the status of Automatically Controlled
|
||||
|
||||
@ -1370,7 +1370,7 @@ static void imon_pad_to_keys(struct imon_context *ictx, unsigned char *buf)
|
||||
* 0x68nnnnB7 to 0x6AnnnnB7, the left mouse button generates
|
||||
* 0x688301b7 and the right one 0x688481b7. All other keys generate
|
||||
* 0x2nnnnnnn. Position coordinate is encoded in buf[1] and buf[2] with
|
||||
* reversed endianess. Extract direction from buffer, rotate endianess,
|
||||
* reversed endianness. Extract direction from buffer, rotate endianness,
|
||||
* adjust sign and feed the values into stabilize(). The resulting codes
|
||||
* will be 0x01008000, 0x01007F00, which match the newer devices.
|
||||
*/
|
||||
|
||||
@ -118,7 +118,7 @@ static int debug;
|
||||
#define RR3_IR_IO_LENGTH_FUZZ 0x04
|
||||
/* Timeout for end of signal detection */
|
||||
#define RR3_IR_IO_SIG_TIMEOUT 0x05
|
||||
/* Minumum value for pause recognition. */
|
||||
/* Minimum value for pause recognition. */
|
||||
#define RR3_IR_IO_MIN_PAUSE 0x06
|
||||
|
||||
/* Clock freq. of EZ-USB chip */
|
||||
|
||||
@ -1195,7 +1195,7 @@ static u32 mt2063_set_dnc_output_enable(struct mt2063_state *state,
|
||||
* DNC Output is selected, the other is always off)
|
||||
*
|
||||
* @state: ptr to mt2063_state structure
|
||||
* @Mode: desired reciever delivery system
|
||||
* @Mode: desired receiver delivery system
|
||||
*
|
||||
* Note: Register cache must be valid for it to work
|
||||
*/
|
||||
@ -2119,7 +2119,7 @@ static int mt2063_set_analog_params(struct dvb_frontend *fe,
|
||||
|
||||
/*
|
||||
* As defined on EN 300 429, the DVB-C roll-off factor is 0.15.
|
||||
* So, the amount of the needed bandwith is given by:
|
||||
* So, the amount of the needed bandwidth is given by:
|
||||
* Bw = Symbol_rate * (1 + 0.15)
|
||||
* As such, the maximum symbol rate supported by 6 MHz is given by:
|
||||
* max_symbol_rate = 6 MHz / 1.15 = 5217391 Bauds
|
||||
|
||||
@ -119,7 +119,7 @@
|
||||
#define V4L2_STD_A2 (V4L2_STD_A2_A | V4L2_STD_A2_B)
|
||||
#define V4L2_STD_NICAM (V4L2_STD_NICAM_A | V4L2_STD_NICAM_B)
|
||||
|
||||
/* To preserve backward compatibilty,
|
||||
/* To preserve backward compatibility,
|
||||
(std & V4L2_STD_AUDIO) = 0 means that ALL audio stds are supported
|
||||
*/
|
||||
|
||||
|
||||
@ -266,7 +266,7 @@ static int mxl111sf_adap_fe_init(struct dvb_frontend *fe)
|
||||
struct mxl111sf_adap_state *adap_state = &state->adap_state[fe->id];
|
||||
int err;
|
||||
|
||||
/* exit if we didnt initialize the driver yet */
|
||||
/* exit if we didn't initialize the driver yet */
|
||||
if (!state->chip_id) {
|
||||
mxl_debug("driver not yet initialized, exit.");
|
||||
goto fail;
|
||||
@ -322,7 +322,7 @@ static int mxl111sf_adap_fe_sleep(struct dvb_frontend *fe)
|
||||
struct mxl111sf_adap_state *adap_state = &state->adap_state[fe->id];
|
||||
int err;
|
||||
|
||||
/* exit if we didnt initialize the driver yet */
|
||||
/* exit if we didn't initialize the driver yet */
|
||||
if (!state->chip_id) {
|
||||
mxl_debug("driver not yet initialized, exit.");
|
||||
goto fail;
|
||||
|
||||
@ -438,7 +438,7 @@ static void sd_pkt_scan(struct gspca_dev *gspca_dev,
|
||||
s32 nToSkip =
|
||||
sd->swapRB * (gspca_dev->cam.cam_mode[mode].bytesperline + 1);
|
||||
|
||||
/* Test only against 0202h, so endianess does not matter */
|
||||
/* Test only against 0202h, so endianness does not matter */
|
||||
switch (*(s16 *) data) {
|
||||
case 0x0202: /* End of frame, start a new one */
|
||||
gspca_frame_add(gspca_dev, LAST_PACKET, NULL, 0);
|
||||
|
||||
@ -416,7 +416,7 @@ static void sd_pkt_scan(struct gspca_dev *gspca_dev,
|
||||
#if IS_ENABLED(CONFIG_INPUT)
|
||||
static int sd_int_pkt_scan(struct gspca_dev *gspca_dev,
|
||||
u8 *data, /* interrupt packet data */
|
||||
int len) /* interrput packet length */
|
||||
int len) /* interrupt packet length */
|
||||
{
|
||||
int ret = -EINVAL;
|
||||
|
||||
|
||||
@ -874,7 +874,7 @@ static int sd_dbg_s_register(struct gspca_dev *gspca_dev,
|
||||
#if IS_ENABLED(CONFIG_INPUT)
|
||||
static int sd_int_pkt_scan(struct gspca_dev *gspca_dev,
|
||||
u8 *data, /* interrupt packet data */
|
||||
int len) /* interrput packet length */
|
||||
int len) /* interrupt packet length */
|
||||
{
|
||||
int ret = -EINVAL;
|
||||
u8 data0, data1;
|
||||
|
||||
@ -139,7 +139,7 @@ static int sd_config(struct gspca_dev *gspca_dev,
|
||||
struct sd *sd = (struct sd *) gspca_dev;
|
||||
struct cam *cam = &gspca_dev->cam;
|
||||
|
||||
/* Give the camera some time to settle, otherwise initalization will
|
||||
/* Give the camera some time to settle, otherwise initialization will
|
||||
fail on hotplug, and yes it really needs a full second. */
|
||||
msleep(1000);
|
||||
|
||||
|
||||
@ -6905,7 +6905,7 @@ static int sd_get_jcomp(struct gspca_dev *gspca_dev,
|
||||
#if IS_ENABLED(CONFIG_INPUT)
|
||||
static int sd_int_pkt_scan(struct gspca_dev *gspca_dev,
|
||||
u8 *data, /* interrupt packet data */
|
||||
int len) /* interrput packet length */
|
||||
int len) /* interrupt packet length */
|
||||
{
|
||||
if (len == 8 && data[4] == 1) {
|
||||
input_report_key(gspca_dev->input_dev, KEY_CAMERA, 1);
|
||||
|
||||
@ -1039,7 +1039,7 @@ static int usb_pwc_probe(struct usb_interface *intf, const struct usb_device_id
|
||||
/* Set the leds off */
|
||||
pwc_set_leds(pdev, 0, 0);
|
||||
|
||||
/* Setup intial videomode */
|
||||
/* Setup initial videomode */
|
||||
rc = pwc_set_video_mode(pdev, MAX_WIDTH, MAX_HEIGHT,
|
||||
V4L2_PIX_FMT_YUV420, 30, &compression, 1);
|
||||
if (rc)
|
||||
|
||||
@ -556,7 +556,7 @@ static u16 uvc_video_clock_host_sof(const struct uvc_clock_sample *sample)
|
||||
*
|
||||
* SOF = ((SOF2 - SOF1) * PTS + SOF1 * STC2 - SOF2 * STC1) / (STC2 - STC1) (1)
|
||||
*
|
||||
* to avoid loosing precision in the division. Similarly, the host timestamp is
|
||||
* to avoid losing precision in the division. Similarly, the host timestamp is
|
||||
* computed with
|
||||
*
|
||||
* TS = ((TS2 - TS1) * PTS + TS1 * SOF2 - TS2 * SOF1) / (SOF2 - SOF1) (2)
|
||||
|
||||
@ -420,7 +420,7 @@ const char * const *v4l2_ctrl_get_menu(u32 id)
|
||||
"Advanced Simple",
|
||||
"Core",
|
||||
"Simple Scalable",
|
||||
"Advanced Coding Efficency",
|
||||
"Advanced Coding Efficiency",
|
||||
NULL,
|
||||
};
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user