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drm/amd/display: Add source select helper functions
[why & how] Add source select helpers based on DCCG spec Reviewed-by: Daniel Miess <daniel.miess@amd.com> Signed-off-by: Hansen Dsouza <hansen.dsouza@amd.com> Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Hansen Dsouza
Alex Deucher
parent
aaa21e6a33
commit
f52ea01925
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@ -418,6 +418,320 @@ static void dccg35_set_smclk32_se_rcg(
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}
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}
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static void dccg35_set_dsc_clk_src_new(struct dccg *dccg, int inst, enum dsc_clk_source src)
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{
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struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
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/* DSCCLK#_EN=0 switches to refclock from functional clock */
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switch (inst) {
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case 0:
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REG_UPDATE(DSCCLK_DTO_CTRL, DSCCLK0_EN, src);
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break;
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case 1:
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REG_UPDATE(DSCCLK_DTO_CTRL, DSCCLK1_EN, src);
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break;
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case 2:
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REG_UPDATE(DSCCLK_DTO_CTRL, DSCCLK2_EN, src);
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break;
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case 3:
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REG_UPDATE(DSCCLK_DTO_CTRL, DSCCLK3_EN, src);
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break;
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default:
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BREAK_TO_DEBUGGER();
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return;
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}
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}
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static void dccg35_set_symclk32_se_src_new(
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struct dccg *dccg,
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int inst,
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enum symclk32_se_clk_source src
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)
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{
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struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
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switch (inst) {
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case 0:
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REG_UPDATE_2(SYMCLK32_SE_CNTL,
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SYMCLK32_SE0_SRC_SEL, (src == SYMCLK32_SE_REFCLK) ? 0 : src,
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SYMCLK32_SE0_EN, (src == SYMCLK32_SE_REFCLK) ? 0 : 1);
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break;
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case 1:
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REG_UPDATE_2(SYMCLK32_SE_CNTL,
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SYMCLK32_SE1_SRC_SEL, (src == SYMCLK32_SE_REFCLK) ? 0 : src,
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SYMCLK32_SE1_EN, (src == SYMCLK32_SE_REFCLK) ? 0 : 1);
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break;
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case 2:
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REG_UPDATE_2(SYMCLK32_SE_CNTL,
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SYMCLK32_SE2_SRC_SEL, (src == SYMCLK32_SE_REFCLK) ? 0 : src,
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SYMCLK32_SE2_EN, (src == SYMCLK32_SE_REFCLK) ? 0 : 1);
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break;
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case 3:
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REG_UPDATE_2(SYMCLK32_SE_CNTL,
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SYMCLK32_SE3_SRC_SEL, (src == SYMCLK32_SE_REFCLK) ? 0 : src,
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SYMCLK32_SE3_EN, (src == SYMCLK32_SE_REFCLK) ? 0 : 1);
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break;
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default:
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BREAK_TO_DEBUGGER();
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return;
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}
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}
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static int
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dccg35_is_symclk32_se_src_functional_le_new(struct dccg *dccg, int symclk_32_se_inst, int symclk_32_le_inst)
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{
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uint32_t en;
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uint32_t src_sel;
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struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
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REG_GET_2(SYMCLK32_SE_CNTL, SYMCLK32_SE3_SRC_SEL, &src_sel, SYMCLK32_SE3_EN, &en);
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if (en == 1 && src_sel == symclk_32_le_inst)
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return 1;
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return 0;
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}
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static void dccg35_set_symclk32_le_src_new(
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struct dccg *dccg,
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int inst,
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enum symclk32_le_clk_source src)
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{
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struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
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switch (inst) {
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case 0:
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REG_UPDATE_2(SYMCLK32_LE_CNTL,
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SYMCLK32_LE0_SRC_SEL, (src == SYMCLK32_LE_REFCLK) ? 0 : src,
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SYMCLK32_LE0_EN, (src == SYMCLK32_LE_REFCLK) ? 0 : 1);
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break;
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case 1:
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REG_UPDATE_2(SYMCLK32_LE_CNTL,
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SYMCLK32_LE1_SRC_SEL, (src == SYMCLK32_LE_REFCLK) ? 0 : src,
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SYMCLK32_LE1_EN, (src == SYMCLK32_LE_REFCLK) ? 0 : 1);
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break;
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default:
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BREAK_TO_DEBUGGER();
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return;
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}
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}
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static void dcn35_set_dppclk_src_new(struct dccg *dccg,
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int inst, enum dppclk_clock_source src)
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{
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struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
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switch (inst) {
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case 0:
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REG_UPDATE(DPPCLK_CTRL, DPPCLK0_EN, src);
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break;
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case 1:
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REG_UPDATE(DPPCLK_CTRL, DPPCLK1_EN, src);
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break;
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case 2:
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REG_UPDATE(DPPCLK_CTRL, DPPCLK2_EN, src);
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break;
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case 3:
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REG_UPDATE(DPPCLK_CTRL, DPPCLK3_EN, src);
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break;
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default:
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BREAK_TO_DEBUGGER();
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break;
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}
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}
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static void dccg35_set_dtbclk_p_src_new(
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struct dccg *dccg,
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enum dtbclk_source src,
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int inst)
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{
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struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
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/* If DTBCLK_P#_EN is 0 refclock is selected as functional clock
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* If DTBCLK_P#_EN is 1 functional clock is selected as DTBCLK_P#_SRC_SEL
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*/
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switch (inst) {
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case 0:
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REG_UPDATE_2(DTBCLK_P_CNTL,
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DTBCLK_P0_SRC_SEL, (src == DTBCLK_REFCLK) ? 0 : src,
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DTBCLK_P0_EN, (src == DTBCLK_REFCLK) ? 0 : 1);
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break;
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case 1:
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REG_UPDATE_2(DTBCLK_P_CNTL,
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DTBCLK_P1_SRC_SEL, (src == DTBCLK_REFCLK) ? 0 : src,
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DTBCLK_P1_EN, (src == DTBCLK_REFCLK) ? 0 : 1);
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break;
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case 2:
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REG_UPDATE_2(DTBCLK_P_CNTL,
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DTBCLK_P2_SRC_SEL, (src == DTBCLK_REFCLK) ? 0 : src,
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DTBCLK_P2_EN, (src == DTBCLK_REFCLK) ? 0 : 1);
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break;
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case 3:
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REG_UPDATE_2(DTBCLK_P_CNTL,
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DTBCLK_P3_SRC_SEL, (src == DTBCLK_REFCLK) ? 0 : src,
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DTBCLK_P3_EN, (src == DTBCLK_REFCLK) ? 0 : 1);
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break;
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default:
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BREAK_TO_DEBUGGER();
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return;
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}
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}
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static void dccg35_set_dpstreamclk_src_new(
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struct dccg *dccg,
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enum dp_stream_clk_source src,
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int inst)
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{
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struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
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switch (inst) {
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case 0:
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REG_UPDATE_2(DPSTREAMCLK_CNTL, DPSTREAMCLK0_EN,
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(src == DP_STREAM_REFCLK) ? 0 : 1,
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DPSTREAMCLK0_SRC_SEL,
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(src == DP_STREAM_REFCLK) ? 0 : src);
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break;
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case 1:
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REG_UPDATE_2(DPSTREAMCLK_CNTL, DPSTREAMCLK1_EN,
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(src == DP_STREAM_REFCLK) ? 0 : 1,
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DPSTREAMCLK1_SRC_SEL,
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(src == DP_STREAM_REFCLK) ? 0 : src);
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break;
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case 2:
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REG_UPDATE_2(DPSTREAMCLK_CNTL, DPSTREAMCLK2_EN,
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(src == DP_STREAM_REFCLK) ? 0 : 1,
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DPSTREAMCLK2_SRC_SEL,
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(src == DP_STREAM_REFCLK) ? 0 : src);
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break;
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case 3:
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REG_UPDATE_2(DPSTREAMCLK_CNTL, DPSTREAMCLK3_EN,
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(src == DP_STREAM_REFCLK) ? 0 : 1,
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DPSTREAMCLK3_SRC_SEL,
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(src == DP_STREAM_REFCLK) ? 0 : src);
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break;
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default:
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BREAK_TO_DEBUGGER();
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return;
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}
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}
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static void dccg35_set_physymclk_src_new(
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struct dccg *dccg,
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enum physymclk_source src,
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int inst)
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{
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struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
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switch (inst) {
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case 0:
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REG_UPDATE_2(PHYASYMCLK_CLOCK_CNTL, PHYASYMCLK_EN,
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(src == PHYSYMCLK_REFCLK) ? 0 : 1,
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PHYASYMCLK_SRC_SEL,
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(src == PHYSYMCLK_REFCLK) ? 0 : src);
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break;
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case 1:
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REG_UPDATE_2(PHYBSYMCLK_CLOCK_CNTL, PHYBSYMCLK_EN,
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(src == PHYSYMCLK_REFCLK) ? 0 : 1,
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PHYBSYMCLK_SRC_SEL,
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(src == PHYSYMCLK_REFCLK) ? 0 : src);
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break;
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case 2:
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REG_UPDATE_2(PHYCSYMCLK_CLOCK_CNTL, PHYCSYMCLK_EN,
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(src == PHYSYMCLK_REFCLK) ? 0 : 1,
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PHYCSYMCLK_SRC_SEL,
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(src == PHYSYMCLK_REFCLK) ? 0 : src);
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break;
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case 3:
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REG_UPDATE_2(PHYDSYMCLK_CLOCK_CNTL, PHYDSYMCLK_EN,
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(src == PHYSYMCLK_REFCLK) ? 0 : 1,
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PHYDSYMCLK_SRC_SEL,
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(src == PHYSYMCLK_REFCLK) ? 0 : src);
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break;
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case 4:
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REG_UPDATE_2(PHYESYMCLK_CLOCK_CNTL, PHYESYMCLK_EN,
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(src == PHYSYMCLK_REFCLK) ? 0 : 1,
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PHYESYMCLK_SRC_SEL,
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(src == PHYSYMCLK_REFCLK) ? 0 : src);
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break;
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default:
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BREAK_TO_DEBUGGER();
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return;
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}
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}
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static int dccg35_is_symclk_fe_src_functional_be(struct dccg *dccg,
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int symclk_fe_inst,
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int symclk_be_inst)
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{
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uint32_t en = 0;
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uint32_t src_sel = 0;
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struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
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switch (symclk_fe_inst) {
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case 0:
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REG_GET_2(SYMCLKA_CLOCK_ENABLE, SYMCLKA_FE_SRC_SEL, &src_sel, SYMCLKA_FE_EN, &en);
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break;
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case 1:
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REG_GET_2(SYMCLKB_CLOCK_ENABLE, SYMCLKB_FE_SRC_SEL, &src_sel, SYMCLKB_FE_EN, &en);
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break;
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case 2:
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REG_GET_2(SYMCLKC_CLOCK_ENABLE, SYMCLKC_FE_SRC_SEL, &src_sel, SYMCLKC_FE_EN, &en);
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break;
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case 3:
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REG_GET_2(SYMCLKD_CLOCK_ENABLE, SYMCLKD_FE_SRC_SEL, &src_sel, SYMCLKD_FE_EN, &en);
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break;
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case 4:
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REG_GET_2(SYMCLKE_CLOCK_ENABLE, SYMCLKE_FE_SRC_SEL, &src_sel, SYMCLKE_FE_EN, &en);
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break;
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}
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if (en == 1 && src_sel == symclk_be_inst)
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return 1;
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return 0;
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}
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static void dccg35_set_symclk_fe_src_new(struct dccg *dccg, enum physymclk_fe_source src, int inst)
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{
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struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
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switch (inst) {
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case 0:
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REG_UPDATE_2(SYMCLKA_CLOCK_ENABLE,
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SYMCLKA_FE_EN, (src == PHYSYMCLK_FE_REFCLK) ? 0 : 1,
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SYMCLKA_FE_SRC_SEL, (src == PHYSYMCLK_FE_REFCLK) ? 0 : src);
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break;
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case 1:
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REG_UPDATE_2(SYMCLKB_CLOCK_ENABLE,
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SYMCLKB_FE_EN, (src == PHYSYMCLK_FE_REFCLK) ? 0 : 1,
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SYMCLKB_FE_SRC_SEL, (src == PHYSYMCLK_FE_REFCLK) ? 0 : src);
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break;
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case 2:
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REG_UPDATE_2(SYMCLKC_CLOCK_ENABLE,
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SYMCLKC_FE_EN, (src == PHYSYMCLK_FE_REFCLK) ? 0 : 1,
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SYMCLKC_FE_SRC_SEL, (src == PHYSYMCLK_FE_REFCLK) ? 0 : src);
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break;
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case 3:
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REG_UPDATE_2(SYMCLKD_CLOCK_ENABLE,
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SYMCLKD_FE_EN, (src == PHYSYMCLK_FE_REFCLK) ? 0 : 1,
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SYMCLKD_FE_SRC_SEL, (src == PHYSYMCLK_FE_REFCLK) ? 0 : src);
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break;
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case 4:
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REG_UPDATE_2(SYMCLKE_CLOCK_ENABLE,
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SYMCLKE_FE_EN, (src == PHYSYMCLK_FE_REFCLK) ? 0 : 1,
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SYMCLKE_FE_SRC_SEL, (src == PHYSYMCLK_FE_REFCLK) ? 0 : src);
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break;
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}
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}
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static void dccg35_trigger_dio_fifo_resync(struct dccg *dccg)
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{
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struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
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@ -1429,6 +1743,16 @@ struct dccg *dccg35_create(
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(void)&dccg35_set_dppclk_rcg;
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(void)&dccg35_set_dpstreamclk_rcg;
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(void)&dccg35_set_smclk32_se_rcg;
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(void)&dccg35_set_dsc_clk_src_new;
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(void)&dccg35_set_symclk32_se_src_new;
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(void)&dccg35_is_symclk32_se_src_functional_le_new;
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(void)&dccg35_set_symclk32_le_src_new;
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(void)&dcn35_set_dppclk_src_new;
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(void)&dccg35_set_dtbclk_p_src_new;
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(void)&dccg35_set_dpstreamclk_src_new;
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(void)&dccg35_set_physymclk_src_new;
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(void)&dccg35_is_symclk_fe_src_functional_be;
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(void)&dccg35_set_symclk_fe_src_new;
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base = &dccg_dcn->base;
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base->ctx = ctx;
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