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ARM: mach-shmobile: sh7372 INTCS support
Add support for the sh7372 INTCS interrupt controller. INTCS is the interrupt controller for the sh7372 SuperH processor core. It is tied into the INTCA interrupt controller which interfaces to the ARM processor. INTCS support is implemented using a new INTC table together with a chained interrupt handler that ties into the already supported INTCA controller. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This commit is contained in:
Magnus Damm
Paul Mundt
parent
9b7c23adb3
commit
f4dd61853e
@ -363,7 +363,227 @@ static struct intc_desc intca_desc __initdata = {
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intca_sense_registers, intca_ack_registers),
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};
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enum {
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UNUSED_INTCS = 0,
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INTCS,
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/* interrupt sources INTCS */
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VEU_VEU0, VEU_VEU1, VEU_VEU2, VEU_VEU3,
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RTDMAC_1_DEI0, RTDMAC_1_DEI1, RTDMAC_1_DEI2, RTDMAC_1_DEI3,
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CEU, BEU_BEU0, BEU_BEU1, BEU_BEU2,
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VPU,
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TSIF1,
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_3DG_SGX530,
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_2DDMAC,
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IIC2_ALI2, IIC2_TACKI2, IIC2_WAITI2, IIC2_DTEI2,
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IPMMU_IPMMUR, IPMMU_IPMMUR2,
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RTDMAC_2_DEI4, RTDMAC_2_DEI5, RTDMAC_2_DADERR,
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MSIOF,
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IIC0_ALI0, IIC0_TACKI0, IIC0_WAITI0, IIC0_DTEI0,
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TMU_TUNI0, TMU_TUNI1, TMU_TUNI2,
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CMT0,
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TSIF0,
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LMB,
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CTI,
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ICB,
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JPU_JPEG,
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LCDC,
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LCRC,
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RTDMAC2_1_DEI0, RTDMAC2_1_DEI1, RTDMAC2_1_DEI2, RTDMAC2_1_DEI3,
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RTDMAC2_2_DEI4, RTDMAC2_2_DEI5, RTDMAC2_2_DADERR,
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ISP,
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LCDC1,
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CSIRX,
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DSITX_DSITX0,
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DSITX_DSITX1,
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TMU1_TUNI0, TMU1_TUNI1, TMU1_TUNI2,
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CMT4,
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DSITX1_DSITX1_0,
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DSITX1_DSITX1_1,
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CPORTS2R,
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JPU6E,
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/* interrupt groups INTCS */
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RTDMAC_1, RTDMAC_2, VEU, BEU, IIC0, IPMMU, IIC2,
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RTDMAC2_1, RTDMAC2_2, TMU1, DSITX,
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};
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static struct intc_vect intcs_vectors[] = {
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INTCS_VECT(VEU_VEU0, 0x700), INTCS_VECT(VEU_VEU1, 0x720),
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INTCS_VECT(VEU_VEU2, 0x740), INTCS_VECT(VEU_VEU3, 0x760),
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INTCS_VECT(RTDMAC_1_DEI0, 0x800), INTCS_VECT(RTDMAC_1_DEI1, 0x820),
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INTCS_VECT(RTDMAC_1_DEI2, 0x840), INTCS_VECT(RTDMAC_1_DEI3, 0x860),
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INTCS_VECT(CEU, 0x880), INTCS_VECT(BEU_BEU0, 0x8a0),
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INTCS_VECT(BEU_BEU1, 0x8c0), INTCS_VECT(BEU_BEU2, 0x8e0),
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INTCS_VECT(VPU, 0x980),
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INTCS_VECT(TSIF1, 0x9a0),
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INTCS_VECT(_3DG_SGX530, 0x9e0),
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INTCS_VECT(_2DDMAC, 0xa00),
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INTCS_VECT(IIC2_ALI2, 0xa80), INTCS_VECT(IIC2_TACKI2, 0xaa0),
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INTCS_VECT(IIC2_WAITI2, 0xac0), INTCS_VECT(IIC2_DTEI2, 0xae0),
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INTCS_VECT(IPMMU_IPMMUR, 0xb00), INTCS_VECT(IPMMU_IPMMUR2, 0xb20),
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INTCS_VECT(RTDMAC_2_DEI4, 0xb80), INTCS_VECT(RTDMAC_2_DEI5, 0xba0),
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INTCS_VECT(RTDMAC_2_DADERR, 0xbc0),
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INTCS_VECT(IIC0_ALI0, 0xe00), INTCS_VECT(IIC0_TACKI0, 0xe20),
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INTCS_VECT(IIC0_WAITI0, 0xe40), INTCS_VECT(IIC0_DTEI0, 0xe60),
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INTCS_VECT(TMU_TUNI0, 0xe80), INTCS_VECT(TMU_TUNI1, 0xea0),
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INTCS_VECT(TMU_TUNI2, 0xec0),
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INTCS_VECT(CMT0, 0xf00),
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INTCS_VECT(TSIF0, 0xf20),
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INTCS_VECT(LMB, 0xf60),
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INTCS_VECT(CTI, 0x400),
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INTCS_VECT(ICB, 0x480),
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INTCS_VECT(JPU_JPEG, 0x560),
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INTCS_VECT(LCDC, 0x580),
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INTCS_VECT(LCRC, 0x5a0),
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INTCS_VECT(RTDMAC2_1_DEI0, 0x1300), INTCS_VECT(RTDMAC2_1_DEI1, 0x1320),
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INTCS_VECT(RTDMAC2_1_DEI2, 0x1340), INTCS_VECT(RTDMAC2_1_DEI3, 0x1360),
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INTCS_VECT(RTDMAC2_2_DEI4, 0x1380), INTCS_VECT(RTDMAC2_2_DEI5, 0x13a0),
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INTCS_VECT(RTDMAC2_2_DADERR, 0x13c0),
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INTCS_VECT(ISP, 0x1720),
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INTCS_VECT(LCDC1, 0x1780),
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INTCS_VECT(CSIRX, 0x17a0),
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INTCS_VECT(DSITX_DSITX0, 0x17c0),
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INTCS_VECT(DSITX_DSITX1, 0x17e0),
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INTCS_VECT(TMU1_TUNI0, 0x1900), INTCS_VECT(TMU1_TUNI1, 0x1920),
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INTCS_VECT(TMU1_TUNI2, 0x1940),
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INTCS_VECT(CMT4, 0x1980),
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INTCS_VECT(DSITX1_DSITX1_0, 0x19a0),
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INTCS_VECT(DSITX1_DSITX1_1, 0x19c0),
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INTCS_VECT(CPORTS2R, 0x1a20),
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INTCS_VECT(JPU6E, 0x1a80),
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INTC_VECT(INTCS, 0xf80),
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};
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static struct intc_group intcs_groups[] __initdata = {
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INTC_GROUP(RTDMAC_1, RTDMAC_1_DEI0, RTDMAC_1_DEI1,
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RTDMAC_1_DEI2, RTDMAC_1_DEI3),
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INTC_GROUP(RTDMAC_2, RTDMAC_2_DEI4, RTDMAC_2_DEI5, RTDMAC_2_DADERR),
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INTC_GROUP(VEU, VEU_VEU0, VEU_VEU1, VEU_VEU2, VEU_VEU3),
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INTC_GROUP(BEU, BEU_BEU0, BEU_BEU1, BEU_BEU2),
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INTC_GROUP(IIC0, IIC0_ALI0, IIC0_TACKI0, IIC0_WAITI0, IIC0_DTEI0),
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INTC_GROUP(IPMMU, IPMMU_IPMMUR, IPMMU_IPMMUR2),
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INTC_GROUP(IIC2, IIC2_ALI2, IIC2_TACKI2, IIC2_WAITI2, IIC2_DTEI2),
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INTC_GROUP(RTDMAC2_1, RTDMAC2_1_DEI0, RTDMAC2_1_DEI1,
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RTDMAC2_1_DEI2, RTDMAC2_1_DEI3),
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INTC_GROUP(RTDMAC2_2, RTDMAC2_2_DEI4,
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RTDMAC2_2_DEI5, RTDMAC2_2_DADERR),
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INTC_GROUP(TMU1, TMU1_TUNI2, TMU1_TUNI1, TMU1_TUNI0),
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INTC_GROUP(DSITX, DSITX_DSITX0, DSITX_DSITX1),
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};
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static struct intc_mask_reg intcs_mask_registers[] = {
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{ 0xffd20184, 0xffd201c4, 8, /* IMR1SA / IMCR1SA */
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{ BEU_BEU2, BEU_BEU1, BEU_BEU0, CEU,
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VEU_VEU3, VEU_VEU2, VEU_VEU1, VEU_VEU0 } },
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{ 0xffd20188, 0xffd201c8, 8, /* IMR2SA / IMCR2SA */
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{ 0, 0, 0, VPU,
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0, 0, 0, 0 } },
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{ 0xffd2018c, 0xffd201cc, 8, /* IMR3SA / IMCR3SA */
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{ 0, 0, 0, _2DDMAC,
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0, 0, 0, ICB } },
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{ 0xffd20190, 0xffd201d0, 8, /* IMR4SA / IMCR4SA */
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{ 0, 0, 0, CTI,
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JPU_JPEG, 0, LCRC, LCDC } },
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{ 0xffd20194, 0xffd201d4, 8, /* IMR5SA / IMCR5SA */
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{ 0, RTDMAC_2_DADERR, RTDMAC_2_DEI5, RTDMAC_2_DEI4,
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RTDMAC_1_DEI3, RTDMAC_1_DEI2, RTDMAC_1_DEI1, RTDMAC_1_DEI0 } },
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{ 0xffd20198, 0xffd201d8, 8, /* IMR6SA / IMCR6SA */
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{ 0, 0, MSIOF, 0,
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_3DG_SGX530, 0, 0, 0 } },
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{ 0xffd2019c, 0xffd201dc, 8, /* IMR7SA / IMCR7SA */
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{ 0, TMU_TUNI2, TMU_TUNI1, TMU_TUNI0,
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0, 0, 0, 0 } },
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{ 0xffd201a4, 0xffd201e4, 8, /* IMR9SA / IMCR9SA */
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{ 0, 0, 0, CMT0,
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IIC2_DTEI2, IIC2_WAITI2, IIC2_TACKI2, IIC2_ALI2 } },
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{ 0xffd201a8, 0xffd201e8, 8, /* IMR10SA / IMCR10SA */
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{ 0, 0, IPMMU_IPMMUR2, IPMMU_IPMMUR,
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0, 0, 0, 0 } },
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{ 0xffd201ac, 0xffd201ec, 8, /* IMR11SA / IMCR11SA */
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{ IIC0_DTEI0, IIC0_WAITI0, IIC0_TACKI0, IIC0_ALI0,
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0, TSIF1, LMB, TSIF0 } },
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{ 0xffd50180, 0xffd501c0, 8, /* IMR0SA3 / IMCR0SA3 */
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{ 0, RTDMAC2_2_DADERR, RTDMAC2_2_DEI5, RTDMAC2_2_DEI4,
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RTDMAC2_1_DEI3, RTDMAC2_1_DEI2, RTDMAC2_1_DEI1, RTDMAC2_1_DEI0 } },
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{ 0xffd50190, 0xffd501d0, 8, /* IMR4SA3 / IMCR4SA3 */
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{ 0, ISP, 0, 0,
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LCDC1, CSIRX, DSITX_DSITX0, DSITX_DSITX1 } },
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{ 0xffd50198, 0xffd501d8, 8, /* IMR6SA3 / IMCR6SA3 */
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{ 0, TMU1_TUNI2, TMU1_TUNI1, TMU1_TUNI0,
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CMT4, DSITX1_DSITX1_0, DSITX1_DSITX1_1, 0 } },
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{ 0xffd5019c, 0xffd501dc, 8, /* IMR7SA3 / IMCR7SA3 */
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{ 0, CPORTS2R, 0, 0,
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JPU6E, 0, 0, 0 } },
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{ 0xffd20104, 0, 16, /* INTAMASK */
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{ 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, INTCS } },
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};
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/* Priority is needed for INTCA to receive the INTCS interrupt */
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static struct intc_prio_reg intcs_prio_registers[] = {
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{ 0xffd20000, 0, 16, 4, /* IPRAS */ { CTI, 0, _2DDMAC, ICB } },
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{ 0xffd20004, 0, 16, 4, /* IPRBS */ { JPU_JPEG, LCDC, 0, LCRC } },
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{ 0xffd20010, 0, 16, 4, /* IPRES */ { RTDMAC_1, CEU, 0, VPU } },
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{ 0xffd20014, 0, 16, 4, /* IPRFS */ { 0, RTDMAC_2, 0, CMT0 } },
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{ 0xffd20018, 0, 16, 4, /* IPRGS */ { TMU_TUNI0, TMU_TUNI1,
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TMU_TUNI2, TSIF1 } },
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{ 0xffd2001c, 0, 16, 4, /* IPRHS */ { 0, 0, VEU, BEU } },
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{ 0xffd20020, 0, 16, 4, /* IPRIS */ { 0, MSIOF, TSIF0, IIC0 } },
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{ 0xffd20024, 0, 16, 4, /* IPRJS */ { 0, _3DG_SGX530, 0, 0 } },
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{ 0xffd20028, 0, 16, 4, /* IPRKS */ { 0, 0, LMB, 0 } },
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{ 0xffd2002c, 0, 16, 4, /* IPRLS */ { IPMMU, 0, 0, 0 } },
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{ 0xffd20030, 0, 16, 4, /* IPRMS */ { IIC2, 0, 0, 0 } },
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{ 0xffd50000, 0, 16, 4, /* IPRAS3 */ { RTDMAC2_1, 0, 0, 0 } },
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{ 0xffd50004, 0, 16, 4, /* IPRBS3 */ { RTDMAC2_2, 0, 0, 0 } },
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{ 0xffd50020, 0, 16, 4, /* IPRIS3 */ { 0, ISP, 0, 0 } },
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{ 0xffd50024, 0, 16, 4, /* IPRJS3 */ { LCDC1, CSIRX, DSITX, 0 } },
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{ 0xffd50030, 0, 16, 4, /* IPRMS3 */ { TMU1, 0, 0, 0 } },
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{ 0xffd50034, 0, 16, 4, /* IPRNS3 */ { CMT4, DSITX1_DSITX1_0,
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DSITX1_DSITX1_1, 0 } },
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{ 0xffd50038, 0, 16, 4, /* IPROS3 */ { 0, CPORTS2R, 0, 0 } },
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{ 0xffd5003c, 0, 16, 4, /* IPRPS3 */ { JPU6E, 0, 0, 0 } },
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};
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static struct resource intcs_resources[] __initdata = {
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[0] = {
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.start = 0xffd20000,
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.end = 0xffd201ff,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = 0xffd50000,
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.end = 0xffd501ff,
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.flags = IORESOURCE_MEM,
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}
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};
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static struct intc_desc intcs_desc __initdata = {
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.name = "sh7372-intcs",
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.resource = intcs_resources,
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.num_resources = ARRAY_SIZE(intcs_resources),
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.hw = INTC_HW_DESC(intcs_vectors, intcs_groups, intcs_mask_registers,
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intcs_prio_registers, NULL, NULL),
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};
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static void intcs_demux(unsigned int irq, struct irq_desc *desc)
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{
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void __iomem *reg = (void *)get_irq_data(irq);
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unsigned int evtcodeas = ioread32(reg);
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generic_handle_irq(intcs_evt2irq(evtcodeas));
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}
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void __init sh7372_init_irq(void)
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{
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void __iomem *intevtsa = ioremap_nocache(0xffd20100, PAGE_SIZE);
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register_intc_controller(&intca_desc);
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register_intc_controller(&intcs_desc);
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/* demux using INTEVTSA */
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set_irq_data(evt2irq(0xf80), (void *)intevtsa);
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set_irq_chained_handler(evt2irq(0xf80), intcs_demux);
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}
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