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dt-bindings: watchdog: arm,sp805: document the reset signal
The reset signal needs to be deasserted before operation of sp805 module. Document in the binding. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Yang Xiwen <forbidden405@outlook.com> Reviewed-by: Guenter Roeck <linux@roeck-us.net> Link: https://lore.kernel.org/r/20240221-hisi-wdt-v3-2-9642613dc2e6@outlook.com Signed-off-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Wim Van Sebroeck <wim@linux-watchdog.org>
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@ -50,6 +50,10 @@ properties:
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- const: wdog_clk
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- const: apb_pclk
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resets:
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maxItems: 1
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description: WDOGRESn input reset signal for sp805 module.
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required:
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- compatible
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- reg
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@ -67,4 +71,5 @@ examples:
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interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&wdt_clk>, <&apb_pclk>;
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clock-names = "wdog_clk", "apb_pclk";
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resets = <&wdt_rst>;
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};
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