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drivers: iio: ti_am335x_adc: add dma support
This patch adds the required pieces to ti_am335x_adc driver for DMA support Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Jonathan Cameron <jic23@kernel.org>
This commit is contained in:
Mugunthan V N
Jonathan Cameron
parent
c9329d8638
commit
f438b9da75
@ -30,10 +30,28 @@
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#include <linux/iio/buffer.h>
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#include <linux/iio/kfifo_buf.h>
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#include <linux/dmaengine.h>
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#include <linux/dma-mapping.h>
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#define DMA_BUFFER_SIZE SZ_2K
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struct tiadc_dma {
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struct dma_slave_config conf;
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struct dma_chan *chan;
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dma_addr_t addr;
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dma_cookie_t cookie;
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u8 *buf;
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int current_period;
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int period_size;
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u8 fifo_thresh;
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};
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struct tiadc_device {
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struct ti_tscadc_dev *mfd_tscadc;
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struct tiadc_dma dma;
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struct mutex fifo1_lock; /* to protect fifo access */
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int channels;
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int total_ch_enabled;
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u8 channel_line[8];
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u8 channel_step[8];
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int buffer_en_ch_steps;
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@ -198,6 +216,67 @@ static irqreturn_t tiadc_worker_h(int irq, void *private)
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return IRQ_HANDLED;
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}
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static void tiadc_dma_rx_complete(void *param)
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{
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struct iio_dev *indio_dev = param;
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struct tiadc_device *adc_dev = iio_priv(indio_dev);
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struct tiadc_dma *dma = &adc_dev->dma;
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u8 *data;
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int i;
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data = dma->buf + dma->current_period * dma->period_size;
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dma->current_period = 1 - dma->current_period; /* swap the buffer ID */
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for (i = 0; i < dma->period_size; i += indio_dev->scan_bytes) {
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iio_push_to_buffers(indio_dev, data);
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data += indio_dev->scan_bytes;
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}
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}
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static int tiadc_start_dma(struct iio_dev *indio_dev)
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{
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struct tiadc_device *adc_dev = iio_priv(indio_dev);
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struct tiadc_dma *dma = &adc_dev->dma;
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struct dma_async_tx_descriptor *desc;
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dma->current_period = 0; /* We start to fill period 0 */
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/*
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* Make the fifo thresh as the multiple of total number of
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* channels enabled, so make sure that cyclic DMA period
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* length is also a multiple of total number of channels
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* enabled. This ensures that no invalid data is reported
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* to the stack via iio_push_to_buffers().
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*/
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dma->fifo_thresh = rounddown(FIFO1_THRESHOLD + 1,
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adc_dev->total_ch_enabled) - 1;
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/* Make sure that period length is multiple of fifo thresh level */
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dma->period_size = rounddown(DMA_BUFFER_SIZE / 2,
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(dma->fifo_thresh + 1) * sizeof(u16));
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dma->conf.src_maxburst = dma->fifo_thresh + 1;
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dmaengine_slave_config(dma->chan, &dma->conf);
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desc = dmaengine_prep_dma_cyclic(dma->chan, dma->addr,
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dma->period_size * 2,
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dma->period_size, DMA_DEV_TO_MEM,
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DMA_PREP_INTERRUPT);
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if (!desc)
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return -EBUSY;
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desc->callback = tiadc_dma_rx_complete;
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desc->callback_param = indio_dev;
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dma->cookie = dmaengine_submit(desc);
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dma_async_issue_pending(dma->chan);
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tiadc_writel(adc_dev, REG_FIFO1THR, dma->fifo_thresh);
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tiadc_writel(adc_dev, REG_DMA1REQ, dma->fifo_thresh);
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tiadc_writel(adc_dev, REG_DMAENABLE_SET, DMA_FIFO1);
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return 0;
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}
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static int tiadc_buffer_preenable(struct iio_dev *indio_dev)
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{
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struct tiadc_device *adc_dev = iio_priv(indio_dev);
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@ -218,20 +297,30 @@ static int tiadc_buffer_preenable(struct iio_dev *indio_dev)
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static int tiadc_buffer_postenable(struct iio_dev *indio_dev)
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{
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struct tiadc_device *adc_dev = iio_priv(indio_dev);
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struct tiadc_dma *dma = &adc_dev->dma;
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unsigned int irq_enable;
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unsigned int enb = 0;
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u8 bit;
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tiadc_step_config(indio_dev);
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for_each_set_bit(bit, indio_dev->active_scan_mask, adc_dev->channels)
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for_each_set_bit(bit, indio_dev->active_scan_mask, adc_dev->channels) {
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enb |= (get_adc_step_bit(adc_dev, bit) << 1);
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adc_dev->total_ch_enabled++;
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}
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adc_dev->buffer_en_ch_steps = enb;
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if (dma->chan)
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tiadc_start_dma(indio_dev);
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am335x_tsc_se_set_cache(adc_dev->mfd_tscadc, enb);
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tiadc_writel(adc_dev, REG_IRQSTATUS, IRQENB_FIFO1THRES
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| IRQENB_FIFO1OVRRUN | IRQENB_FIFO1UNDRFLW);
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tiadc_writel(adc_dev, REG_IRQENABLE, IRQENB_FIFO1THRES
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| IRQENB_FIFO1OVRRUN);
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irq_enable = IRQENB_FIFO1OVRRUN;
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if (!dma->chan)
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irq_enable |= IRQENB_FIFO1THRES;
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tiadc_writel(adc_dev, REG_IRQENABLE, irq_enable);
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return 0;
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}
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@ -239,12 +328,18 @@ static int tiadc_buffer_postenable(struct iio_dev *indio_dev)
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static int tiadc_buffer_predisable(struct iio_dev *indio_dev)
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{
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struct tiadc_device *adc_dev = iio_priv(indio_dev);
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struct tiadc_dma *dma = &adc_dev->dma;
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int fifo1count, i, read;
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tiadc_writel(adc_dev, REG_IRQCLR, (IRQENB_FIFO1THRES |
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IRQENB_FIFO1OVRRUN | IRQENB_FIFO1UNDRFLW));
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am335x_tsc_se_clr(adc_dev->mfd_tscadc, adc_dev->buffer_en_ch_steps);
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adc_dev->buffer_en_ch_steps = 0;
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adc_dev->total_ch_enabled = 0;
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if (dma->chan) {
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tiadc_writel(adc_dev, REG_DMAENABLE_CLEAR, 0x2);
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dmaengine_terminate_async(dma->chan);
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}
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/* Flush FIFO of leftover data in the time it takes to disable adc */
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fifo1count = tiadc_readl(adc_dev, REG_FIFO1CNT);
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@ -430,6 +525,41 @@ static const struct iio_info tiadc_info = {
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.driver_module = THIS_MODULE,
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};
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static int tiadc_request_dma(struct platform_device *pdev,
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struct tiadc_device *adc_dev)
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{
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struct tiadc_dma *dma = &adc_dev->dma;
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dma_cap_mask_t mask;
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/* Default slave configuration parameters */
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dma->conf.direction = DMA_DEV_TO_MEM;
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dma->conf.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
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dma->conf.src_addr = adc_dev->mfd_tscadc->tscadc_phys_base + REG_FIFO1;
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dma_cap_zero(mask);
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dma_cap_set(DMA_CYCLIC, mask);
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/* Get a channel for RX */
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dma->chan = dma_request_chan(adc_dev->mfd_tscadc->dev, "fifo1");
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if (IS_ERR(dma->chan)) {
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int ret = PTR_ERR(dma->chan);
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dma->chan = NULL;
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return ret;
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}
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/* RX buffer */
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dma->buf = dma_alloc_coherent(dma->chan->device->dev, DMA_BUFFER_SIZE,
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&dma->addr, GFP_KERNEL);
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if (!dma->buf)
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goto err;
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return 0;
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err:
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dma_release_channel(dma->chan);
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return -ENOMEM;
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}
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static int tiadc_parse_dt(struct platform_device *pdev,
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struct tiadc_device *adc_dev)
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{
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@ -512,8 +642,14 @@ static int tiadc_probe(struct platform_device *pdev)
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platform_set_drvdata(pdev, indio_dev);
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err = tiadc_request_dma(pdev, adc_dev);
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if (err && err == -EPROBE_DEFER)
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goto err_dma;
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return 0;
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err_dma:
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iio_device_unregister(indio_dev);
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err_buffer_unregister:
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tiadc_iio_buffered_hardware_remove(indio_dev);
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err_free_channels:
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@ -525,8 +661,14 @@ static int tiadc_remove(struct platform_device *pdev)
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{
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struct iio_dev *indio_dev = platform_get_drvdata(pdev);
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struct tiadc_device *adc_dev = iio_priv(indio_dev);
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struct tiadc_dma *dma = &adc_dev->dma;
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u32 step_en;
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if (dma->chan) {
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dma_free_coherent(dma->chan->device->dev, DMA_BUFFER_SIZE,
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dma->buf, dma->addr);
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dma_release_channel(dma->chan);
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}
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iio_device_unregister(indio_dev);
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tiadc_iio_buffered_hardware_remove(indio_dev);
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tiadc_channels_remove(indio_dev);
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@ -23,6 +23,8 @@
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#define REG_IRQENABLE 0x02C
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#define REG_IRQCLR 0x030
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#define REG_IRQWAKEUP 0x034
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#define REG_DMAENABLE_SET 0x038
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#define REG_DMAENABLE_CLEAR 0x03c
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#define REG_CTRL 0x040
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#define REG_ADCFSM 0x044
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#define REG_CLKDIV 0x04C
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@ -36,6 +38,7 @@
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#define REG_FIFO0THR 0xE8
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#define REG_FIFO1CNT 0xF0
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#define REG_FIFO1THR 0xF4
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#define REG_DMA1REQ 0xF8
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#define REG_FIFO0 0x100
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#define REG_FIFO1 0x200
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@ -126,6 +129,10 @@
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#define FIFOREAD_DATA_MASK (0xfff << 0)
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#define FIFOREAD_CHNLID_MASK (0xf << 16)
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/* DMA ENABLE/CLEAR Register */
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#define DMA_FIFO0 BIT(0)
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#define DMA_FIFO1 BIT(1)
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/* Sequencer Status */
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#define SEQ_STATUS BIT(5)
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#define CHARGE_STEP 0x11
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