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drm/amdgpu/cz: implement voltage validation properly
CZ uses a different set of registers compared to previous asics and supports separate NB and GFX planes. Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -494,6 +494,13 @@ static void cz_dpm_fini(struct amdgpu_device *adev)
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amdgpu_free_extended_power_table(adev);
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}
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#define ixSMUSVI_NB_CURRENTVID 0xD8230044
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#define CURRENT_NB_VID_MASK 0xff000000
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#define CURRENT_NB_VID__SHIFT 24
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#define ixSMUSVI_GFX_CURRENTVID 0xD8230048
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#define CURRENT_GFX_VID_MASK 0xff000000
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#define CURRENT_GFX_VID__SHIFT 24
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static void
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cz_dpm_debugfs_print_current_performance_level(struct amdgpu_device *adev,
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struct seq_file *m)
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@ -505,18 +512,20 @@ cz_dpm_debugfs_print_current_performance_level(struct amdgpu_device *adev,
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TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX_MASK) >>
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TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX__SHIFT;
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u32 sclk, tmp;
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u16 vddc;
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u16 vddnb, vddgfx;
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if (current_index >= NUM_SCLK_LEVELS) {
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seq_printf(m, "invalid dpm profile %d\n", current_index);
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} else {
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sclk = table->entries[current_index].clk;
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tmp = (RREG32_SMC(ixSMU_VOLTAGE_STATUS) &
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SMU_VOLTAGE_STATUS__SMU_VOLTAGE_CURRENT_LEVEL_MASK) >>
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SMU_VOLTAGE_STATUS__SMU_VOLTAGE_CURRENT_LEVEL__SHIFT;
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vddc = cz_convert_8bit_index_to_voltage(adev, (u16)tmp);
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seq_printf(m, "power level %d sclk: %u vddc: %u\n",
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current_index, sclk, vddc);
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tmp = (RREG32_SMC(ixSMUSVI_NB_CURRENTVID) &
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CURRENT_NB_VID_MASK) >> CURRENT_NB_VID__SHIFT;
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vddnb = cz_convert_8bit_index_to_voltage(adev, (u16)tmp);
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tmp = (RREG32_SMC(ixSMUSVI_GFX_CURRENTVID) &
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CURRENT_GFX_VID_MASK) >> CURRENT_GFX_VID__SHIFT;
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vddgfx = cz_convert_8bit_index_to_voltage(adev, (u16)tmp);
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seq_printf(m, "power level %d sclk: %u vddnb: %u vddgfx: %u\n",
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current_index, sclk, vddnb, vddgfx);
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}
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}
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